JP4575944B2 - 高密度記憶デバイス - Google Patents
高密度記憶デバイス Download PDFInfo
- Publication number
- JP4575944B2 JP4575944B2 JP2007237825A JP2007237825A JP4575944B2 JP 4575944 B2 JP4575944 B2 JP 4575944B2 JP 2007237825 A JP2007237825 A JP 2007237825A JP 2007237825 A JP2007237825 A JP 2007237825A JP 4575944 B2 JP4575944 B2 JP 4575944B2
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- JP
- Japan
- Prior art keywords
- circuit board
- storage device
- attached
- circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Information Transfer Systems (AREA)
Description
Claims (9)
- ハウジング、及びハウジングに取り付けられるメモリとコントローラのアセンブリを有する記憶デバイスであって、
前記ハウジングが、貫通孔、プラグ部、及び他の記憶デバイスのプラグ部を受け入れるために適用されるソケット部、を有し、
前記プラグ部が、上内面、及び底内面、を有し、
前記ソケット部が、上内面、及び底内面、を有し、
前記メモリとコントローラのアセンブリが、貫通孔に取り付けられた前記回路基板、ソースコントローラ集積回路(ソースコントローラIC)、及びメモリ集積回路(メモリIC)、を有し、
前記回路基板が、上面、底面、ハウジングのプラグ部に取り付けられる第1のセクション、ハウジングのソケット部に対応して取り付けられる第2のセクション、当該回路基板に取り付けられる回路、回路から伸長し、間隔を置いて上面に形成され、回路基板の第1のセクションに取り付けられる複数の第1の電気接点、及び回路から伸長し、間隔を置いて上面に形成され、回路基板の第2のセクションに取り付けられる複数の第2の電気接点、を有し、
前記回路基板の底面に取り付けられ、回路基板の回路と電気的に接続するソースコントローラ集積回路(ソースコントローラIC)、及び
前記回路基板の底面に取り付けられ、回路基板の回路と電気的に接続するメモリ集積回路(メモリIC)、を備える、
記憶デバイス。 - ハウジングのプラグ部内にあって、プラグ部の上内面と第1の電気接点との間に形成されるプラグスペース、及びハウジングのソケット部内にあって、ソケット部の上内面と第2の電気接点との間に形成されるソケットスペース、を更に備える、請求項1に記載の記憶デバイス。
- ソースコントローラIC及びメモリICを覆って保持するために、回路基板の底面上であって、回路基板の底面とプラグ部及びソケット部の底内面との間に取り付けられる位置決めグリューを更に有する、請求項1に記載の記憶デバイス。
- 回路基板の底面に取り付けられ、回路基板の回路と電気的に接続し、位置決めグリューによって覆われる複数の受動コンポーネントを更に有する、請求項3に記載の記憶デバイス。
- ソケット部が、ソケット部の上内面及び底内面にそれぞれ取り付けられる2つの弾性突起を更に有する、請求項1に記載の記憶デバイス。
- 各第2の電気接点が電気的弾性シートを有する、請求項1に記載の記憶デバイス。
- 位置決めグリューが、底面、及びプラグ部の底内面と回路基板の底面との間の高さに等しい、位置決めグリューの底面と回路基板の底面との間の高さ、を有する、請求項3に記載の記憶デバイス。
- 各電気的弾性シートが2つの側面を有し、側面の内の少なくとも1つが第2の電気接点の内の対応する1つと接続する、請求項6に記載の記憶デバイス。
- 各電気的弾性シートが逆V型の突起部を更に有する、請求項8に記載の記憶デバイス。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007237825A JP4575944B2 (ja) | 2007-09-13 | 2007-09-13 | 高密度記憶デバイス |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007237825A JP4575944B2 (ja) | 2007-09-13 | 2007-09-13 | 高密度記憶デバイス |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009070138A JP2009070138A (ja) | 2009-04-02 |
JP4575944B2 true JP4575944B2 (ja) | 2010-11-04 |
Family
ID=40606319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007237825A Expired - Fee Related JP4575944B2 (ja) | 2007-09-13 | 2007-09-13 | 高密度記憶デバイス |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4575944B2 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH048596A (ja) * | 1990-04-20 | 1992-01-13 | Rohm Co Ltd | Icメモリカード |
US20050086413A1 (en) * | 2003-10-15 | 2005-04-21 | Super Talent Electronics Inc. | Capacity Expansion of Flash Memory Device with a Daisy-Chainable Structure and an Integrated Hub |
JP2007179093A (ja) * | 2005-12-26 | 2007-07-12 | Toshiba Corp | Usb装置およびusb装置の制御方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060047880A1 (en) * | 2004-08-27 | 2006-03-02 | Imation Corp. | Memory device with HUB capability |
-
2007
- 2007-09-13 JP JP2007237825A patent/JP4575944B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH048596A (ja) * | 1990-04-20 | 1992-01-13 | Rohm Co Ltd | Icメモリカード |
US20050086413A1 (en) * | 2003-10-15 | 2005-04-21 | Super Talent Electronics Inc. | Capacity Expansion of Flash Memory Device with a Daisy-Chainable Structure and an Integrated Hub |
JP2007179093A (ja) * | 2005-12-26 | 2007-07-12 | Toshiba Corp | Usb装置およびusb装置の制御方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2009070138A (ja) | 2009-04-02 |
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