JP4575147B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4575147B2
JP4575147B2 JP2004381896A JP2004381896A JP4575147B2 JP 4575147 B2 JP4575147 B2 JP 4575147B2 JP 2004381896 A JP2004381896 A JP 2004381896A JP 2004381896 A JP2004381896 A JP 2004381896A JP 4575147 B2 JP4575147 B2 JP 4575147B2
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JP
Japan
Prior art keywords
base substrate
semiconductor element
heat generating
dielectric substrate
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004381896A
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English (en)
Japanese (ja)
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JP2006190711A (ja
JP2006190711A5 (enExample
Inventor
一考 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2004381896A priority Critical patent/JP4575147B2/ja
Priority to US11/317,182 priority patent/US7605465B2/en
Publication of JP2006190711A publication Critical patent/JP2006190711A/ja
Publication of JP2006190711A5 publication Critical patent/JP2006190711A5/ja
Application granted granted Critical
Publication of JP4575147B2 publication Critical patent/JP4575147B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2004381896A 2004-12-28 2004-12-28 半導体装置 Expired - Fee Related JP4575147B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004381896A JP4575147B2 (ja) 2004-12-28 2004-12-28 半導体装置
US11/317,182 US7605465B2 (en) 2004-12-28 2005-12-27 Semiconductor device for high frequency power amplification

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004381896A JP4575147B2 (ja) 2004-12-28 2004-12-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2006190711A JP2006190711A (ja) 2006-07-20
JP2006190711A5 JP2006190711A5 (enExample) 2010-05-20
JP4575147B2 true JP4575147B2 (ja) 2010-11-04

Family

ID=36610509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004381896A Expired - Fee Related JP4575147B2 (ja) 2004-12-28 2004-12-28 半導体装置

Country Status (2)

Country Link
US (1) US7605465B2 (enExample)
JP (1) JP4575147B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8357942B2 (en) * 2006-10-02 2013-01-22 Kabushiki Kaisha Toshiba Semiconductor device with a peripheral circuit formed therein
JP4558012B2 (ja) * 2007-07-05 2010-10-06 株式会社東芝 半導体パッケージ用放熱プレート及び半導体装置
US20100091477A1 (en) * 2008-10-14 2010-04-15 Kabushiki Kaisha Toshiba Package, and fabrication method for the package
JP5631607B2 (ja) * 2009-08-21 2014-11-26 株式会社東芝 マルチチップモジュール構造を有する高周波回路
JP5450313B2 (ja) * 2010-08-06 2014-03-26 株式会社東芝 高周波半導体用パッケージおよびその作製方法
US8471382B2 (en) * 2010-11-18 2013-06-25 Kabushiki Kaisha Toshiba Package and high frequency terminal structure for the same
TWI895109B (zh) * 2024-09-19 2025-08-21 同欣電子工業股份有限公司 複合式板材封裝結構

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0452748U (enExample) * 1990-09-12 1992-05-06
JP2863678B2 (ja) * 1992-09-28 1999-03-03 三菱電機株式会社 半導体レーザ装置及びその製造方法
DE4343121A1 (de) * 1993-12-17 1995-06-22 Abb Patent Gmbh Verfahren zur Herstellung einer Gießkeramik
JP3216482B2 (ja) * 1995-06-22 2001-10-09 三菱電機株式会社 高周波回路装置
US6784541B2 (en) * 2000-01-27 2004-08-31 Hitachi, Ltd. Semiconductor module and mounting method for same
US6653730B2 (en) * 2000-12-14 2003-11-25 Intel Corporation Electronic assembly with high capacity thermal interface
JP2002190540A (ja) 2000-12-20 2002-07-05 Kyocera Corp 半導体素子収納用パッケージ
JP2003007928A (ja) * 2001-06-27 2003-01-10 Nissan Motor Co Ltd 半導体装置
KR100432715B1 (ko) * 2001-07-18 2004-05-24 엘지전자 주식회사 방열부재를 갖는 인쇄회로기판 및 그 제조방법

Also Published As

Publication number Publication date
JP2006190711A (ja) 2006-07-20
US20060138655A1 (en) 2006-06-29
US7605465B2 (en) 2009-10-20

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