JP4559244B2 - Display panel drive device - Google Patents

Description

  The present invention relates to a display panel driving device including a capacitive light emitting element such as a plasma display panel (hereinafter referred to as “PDP”).

  Today, a thin display device using a self-luminous flat display panel such as a PDP has been commercialized as a so-called wall-mounted television. As a display panel driving device in such a thin display device, for example, as shown in Patent Document 1 Technology is disclosed.

Here, a schematic configuration of a display panel driving device disclosed in Patent Document 1 is shown in a block diagram of FIG. In the figure, a PDP 10 that is a display panel includes row electrodes X _{1 to} X _n that form a row electrode pair corresponding to each row (first row to n-th row) of one screen with a pair of X electrode and Y electrode. Row electrodes Y _{1 to} Y _n are provided. Further, in the PDP 10, a column electrode Z ₁ corresponding to each column (first column to m-th column) of one screen with a dielectric layer and a discharge space layer (not shown) interposed between the pair of row electrodes. to Z _m are formed. Incidentally, one discharge cell C _{(i, j)} is formed at the intersection of one pair of row electrodes (X _i , Y _i ) and one column electrode Z _j . Each electrode of the PDP 10 is connected to the column electrode drive circuit 20 and the row electrode drive circuit 30 or 40, and these electrode drive circuits are driven and controlled by commands from the drive control circuit 50.

  Next, a schematic operation of the display panel driving device shown in FIG. 1 will be described based on an operation time chart shown in FIG.

First, the row electrode drive circuit 30 simultaneously applies it to generate a reset pulse RP _y of but such positive voltage shown in FIG. 2 to each of the row electrodes Y ₁ to Y _n. At the same time, the row electrode drive circuit 40 simultaneously applies to all this by generating a reset pulse RP _x of negative voltage on the row electrodes X ₁ to X _n. The simultaneous application of these reset pulses RP _x and RP _y, all the discharge cells of the PDP10 are discharged excited charged particles are generated. After the end of the discharge, a predetermined amount of wall charges are uniformly formed in the dielectric layers of all the discharge cells. Incidentally, this process process is called a reset process.

After completion of the reset process, the column electrode drive circuit 20 generates pixel data pulses DP _{1 to} DP _n corresponding to the pixel data corresponding to each of the first to nth rows of the screen. These pixel data pulses are sequentially applied to the column electrodes Z _{1 to} Z _m as shown in FIG. On the other hand, the row electrode drive circuit 30 generates a negative voltage scan pulse SP in accordance with the application timing of each of the pixel data pulses DP _{1 to} DP _n , and sequentially generates the row electrode Y ₁ at the timing shown in FIG. go applied to ~Y _n.

  Among the discharge cells belonging to the row electrode to which the scan pulse SP is applied, a discharge occurs in the discharge cells to which the positive pixel data pulse DP is simultaneously applied, and most of the wall charges are lost. On the other hand, in the discharge cells to which the scanning pulse SP is applied but the positive pixel data pulse DP is not applied, no discharge occurs, so that the wall charges remain. At this time, the discharge cells in which the wall charges remain remain as light emitting discharge cells, and the discharge cells in which the wall charges have disappeared become non-light emitting discharge cells. Incidentally, such a process process is referred to as an address process.

When the addressing process is completed, the row electrode driving circuit 30 continuously applies a positive voltage sustain pulse IP _Y to each of the row electrodes Y _{1 to} Y _n as shown in FIG. At the same time, the row electrode drive circuit 40 continuously applies the positive voltage sustain pulse IP _X to each of the row electrodes X _{1 to} X _{n at} a timing having a predetermined phase difference from the application timing of the sustain pulse IP _Y. To do. The light emitting discharge cell in which the wall charges remain for the period in which the sustain pulses IP _X and IP _Y are alternately applied repeats the discharge light emission and maintains the light emission state. Incidentally, this process process is called a sustain process.

  The series of processing steps described above is repeated for each subfield of the display image in the display panel driving apparatus of FIG.

  The drive control circuit 50 shown in FIG. 1 generates various switching signals for generating various drive pulses as shown in FIG. 2 based on the synchronization timing included in the video signal supplied to the apparatus. . The circuit supplies these switching signals to the column electrode drive circuit 20 and the row electrode drive circuits 30 and 40, respectively. That is, each of the column electrode drive circuit 20 and the row electrode drive circuits 30 and 40 generates various drive pulses shown in FIG. 2 in accordance with the switching signal supplied from the drive control circuit 50.

On the other hand, in each of the electrode drive circuits 30 to 50 described above, a pulse generation circuit that generates various drive pulses such as a reset pulse RP _Y and sustain pulses IP _X and IP _Y includes electrodes in each row or each column. It is provided for each. Each of these pulse generation circuits generates the above-described various drive pulses by utilizing the charging / discharging of the capacitor by the LC resonance circuit including the inductor L and the capacitor C.

That is, paying attention to the fact that the discharge cell C _{(i, j)} formed on the PDP 10 is a capacitive load, a resonance circuit is formed by combining this with an inductor as an inductive element and a capacitor for power recovery. It forms. Then, a switching element such as an FET is opened / closed according to the switching signal supplied from the drive control circuit 50, and a desired drive pulse is generated by exciting the resonance circuit at a predetermined timing.

  An example of such a pulse generation circuit is shown in FIG. The operation of the circuit shown in the figure will be briefly described as follows.

First, when the switch S2 is turned on by a predetermined switching signal supplied from the drive control circuit 50, the power recovery capacitor C0 is connected to the panel capacitance Cp of the discharge cell C _{(i, j)} via the diode D1 and the inductor L1. Connected to. As a result, Cp is charged by the electric charge stored in C0, and this charging current flows through L1. Thereafter, after a predetermined processing operation is performed, the switch S3 is turned on instead of S2. As a result, C0 and Cp are connected via the diode D2 and the inductor L2, and a discharge current from Cp to C0 flows through L2 this time. Then, by repeating this process at a predetermined timing, the discharge cell C _{(i, j)} is driven.

The peak value of the power recovery current that flows when the discharge cell C _{(i, j)} is driven and the effective value thereof are relatively large current values. Therefore, as the power recovery capacitor C0, a film capacitor suitable for such use conditions is generally used.

  By the way, in a film capacitor in which a polymer film and a metal foil film for an electrode are formed by winding, vibration is generated in a dipole moment generated by a polarization phenomenon when a voltage is applied due to characteristics of the polymer film used as a dielectric. There may be a roaring noise in the dielectric. Furthermore, in order to increase the mounting efficiency on a circuit board, a general film capacitor is often formed by further pressing a concentric winding shape and forming its outer shape into a flat shape. Such press working tends to cause stress distortion in the dielectric polymer film and increase the above-mentioned beat sound.

  On the other hand, the sustain pulse period in the sustain process is generally several microseconds. Therefore, an audible beat sound is not generated in the dielectric of the film condenser used as C0 due to the power recovery current flowing through the power recovery capacitor C0 in response to the sustain pulse.

  However, as described above, the display light emission driving sequence in the PDP is configured by dividing one field period into a plurality of subfields including an address process and a sustain process. As shown in FIG. 4, the power recovery current corresponding to the sustain pulse does not flow in the address process but flows only in the sustain process. Therefore, the power recovery current flowing through C0 becomes a tone burst current signal that flows every time the address process and the sustain process are repeated.

In other words, the power recovery current flowing through the C0 film capacitor includes an audible frequency component consisting of a repetition of an address process and a sustain process, and the frequency component causes the audible frequency of the capacitor to be audible. Sound is generated.
JP 2003-140602 A

  The present invention has been made to solve such a problem, and provides a display panel driving device in which beat noise and the like during driving of a display panel including a capacitive light emitting element such as a PDP are reduced.

The invention according to claim 1 is arranged at each of a plurality of row electrode pairs, a plurality of column electrodes arranged to cross the row electrode pairs, and intersections of the row electrode pairs and the column electrodes. A display panel driving apparatus comprising: a display panel comprising capacitive light emitting elements; and a pulse generating means for supplying a driving pulse to each of the capacitive light emitting elements, wherein the pulse generating means is applied to the capacitive light emitting elements. A switching circuit that performs charging and discharging via an inductor element, and a charge storage circuit that is connected to the switching circuit and supplies charges to the capacitive light emitting element and collects charges from the capacitive light emitting element. An impedance that is connected in parallel with the charge storage circuit and exhibits an impedance value equal to or lower than that of the charge storage circuit within an audible frequency band. Look including a road, wherein the impedance circuit is a series circuit of the one capacitor element of the inductor element and the resistor, the capacitor element is characterized in that an electrolytic capacitor.

  FIG. 5 shows the configuration of a display panel driving apparatus according to the first embodiment of the present invention.

In the figure, a PDP 11 serving as a display panel includes row electrodes X _{1 to} X _n that form a row electrode pair corresponding to each row (first row to n-th row) of one screen with a pair of X electrode and Y electrode. and a row electrode Y ₁ to Y _n. Further, the PDP 11 includes column electrodes Z ₁ to Z ₁ corresponding to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space layer (not shown) perpendicular to the row electrode pair. Z _m is formed. Note that one discharge cell C _{(i, j)} is formed at the intersection between one pair of row electrodes (X _i , Y _i ) and one column electrode Z _j .

  Each electrode in the PDP 11 is connected to the column electrode drive circuit 21 and the row electrode drive circuit 31 or 41, and these electrode drive circuits are driven and controlled by commands from the drive control circuit 51.

The row electrode drive circuit 31 generates various drive pulses such as the aforementioned reset pulse and sustain pulse, and applies these pulses to each of the row electrodes Y _{1 to} Y _{n at} a predetermined timing. Similarly, the row electrode drive circuit 41 also generates various drive pulses and applies these pulses to each of the row electrodes X _{1 to} X _{n at} a predetermined timing. The column electrode driving circuit 21 generates a pixel data pulse corresponding to the pixel data corresponding to each of the first row to the n-th row of the screen successively these pixel data pulses to the column electrodes Z ₁ to Z _m Apply. Note that, in each of the row electrode drive circuits 31 and 41 and the column electrode drive circuit 21, a pulse generation circuit that generates various drive pulses is provided for each electrode of each row and each column.

  The drive control circuit 51 generates various switching signals for controlling the various driving pulses based on the synchronization timing of the video signal supplied to the display panel driving device. These switching signals are supplied to a pulse generation circuit provided in each of the column electrode drive circuit 21 and the row electrode drive circuits 31 and 41.

Next, in each of the column electrode drive circuit 21 and the row electrode drive circuits 31 and 41, the column electrodes Z _{1 to} Z _m of the PDP 11 or the row electrodes X _{1 to} X _n and the row electrodes Y _{1 to} Y _n. The configuration of the pulse generation circuit provided for each is shown in FIG.

  In the figure, line 1 represents an output line to each of the X, Y, or Z electrodes in the PDP 11. The panel capacitance Cp indicates a capacitor that each discharge cell on the PDP 11 has for each electrode, and is connected to the line 1 through each electrode (not shown).

  In FIG. 6, one end of the switch S1 is connected to the line 1, the other end of S1 is connected to the positive terminal of the DC power supply Vsus, and the negative terminal of the power supply is connected to the reference potential of the display panel driving device. Has been. Note that the switch S <b> 1 is a switching element such as a transistor or an FET, and is on / off controlled by a switching signal supplied from the drive control circuit 51.

  The line 1 is connected to one end of a Cp charging resonance circuit composed of a series circuit of an inductor L1, a diode D1, and a switch S2. The other end of the series circuit is a power recovery capacitor C0 and an impedance circuit. It is connected to one end of Za.

  Similarly, the line 1 is connected to one end of a discharge resonance circuit of Cp composed of a series circuit of an inductor L2, a diode D2, and a switch S3, and the other end of the series circuit is connected to a power recovery capacitor C0 and It is connected to one end of the impedance circuit Za.

  Further, the line 1 is connected to one end of the switch S4, and the other end of S4 is connected to the reference potential. The power recovery capacitor C0 and the other end of the impedance circuit Za are also connected to the reference potential in the same manner.

  The impedance circuit Za is composed of a series circuit of an inductor La and a capacitor Ca. In the circuit shown in FIG. 6, one end of the inductor La is connected to one end of the power recovery capacitor C0 and one end of the capacitor Ca is connected to the reference potential. However, the present invention is not limited to such a case. Alternatively, the positions of the inductor La and the capacitor Ca may be reversed.

  Next, the operation of the pulse generation circuit shown in FIG. 6 will be described.

  First, when S2 is turned on at a predetermined timing by a switching signal from the drive control circuit 51, the charge stored in the power recovery capacitor C0 moves to Cp and Cp is charged. When the terminal voltage Vout of Cp rises and reaches a predetermined voltage due to charging, S2 is turned off by the switching signal from the drive control circuit 51, and the switch S1 is turned on instead, and the terminal voltage Vout of Cp becomes DC. It is fixed to the voltage Vsus of the power supply. Thereafter, after a predetermined time has elapsed, S1 is turned off and the switch S3 is turned on instead. As a result, the charge of Cp is recovered by the power recovery capacitor C0, and the terminal voltage Vout of Cp decreases. Thereafter, S3 is turned off after a lapse of a predetermined time, and the switch S4 is turned on instead, and the terminal voltage Vout of Cp is reduced to the reference potential.

  By repeating the charge / discharge cycle described above, for example, a sustain pulse as shown in the time chart of FIG. 4 is applied to the panel capacitance Cp from each pulse generation circuit. In the figure, the power recovery current is drawn on the positive side when charging Cp and on the negative side when discharging from Cp.

  The power recovery current shown in FIG. 4 constitutes a waveform sequence in which current waveforms of charge and discharge of Cp are temporally connected, and such a waveform sequence appears according to the repetition cycle of the sustain process and the address process. It can be regarded as a burst signal. Therefore, the power recovery current includes a frequency component that depends on the repetition cycle of the sustain process and the address process, the original frequency component of the sustain pulse, and its harmonic component.

  As described above, since the cycle of the sustain pulse itself is a value of several microseconds, the latter frequency component does not fall within the range of the audible frequency band. However, the repetition cycle of the sustain process and the address process is a repetition for each subfield and has a value of about several milliseconds. Therefore, the former frequency component appears within the audible frequency band. Accordingly, when a signal having such a frequency component flows through the power recovery capacitor C0, it becomes a cause for the generation of a beat sound in the film capacitor.

  Incidentally, in this embodiment, as shown in FIG. 6, an impedance circuit Za is connected in parallel with the power recovery capacitor C0. Since the impedance circuit Za is composed of a series circuit of an inductor La and a capacitor Ca, the impedance of the circuit with respect to the frequency f is expressed by the following equation.

Za = ra + j (2πfLa−1 / 2πfCa)... [Formula 1]
Note that ra in the above equation is a resistance component of the circuit generated by the loss of the inductor La and the capacitor Ca.

  As is clear from Equation 1, the impedance of Za shows a minimum value at the resonance frequency fa = 1 / 2π√ (La × Ca) determined from the inductor La and the capacitor Ca.

On the other hand, the impedance Zco of the power recovery capacitor C0 is theoretically
Zco = −j (1 / 2πfC0)... [Formula 2]
Although it should be decreased in proportion to an increase in the frequency f, it actually has a specific self-resonant frequency fco due to the influence of the lead inductance and the like. That is, the frequency characteristic of Zco decreases in proportion to the increase in frequency f, but tends to increase conversely when the frequency value exceeds the self-resonant frequency fco.

  In order to arrange the above description, FIG. 7 shows the frequency characteristics of Za and Zco. Incidentally, the vertical axis of the figure represents the absolute value of each impedance, and the horizontal axis represents the frequency.

Here, since element values such as La and Ca constituting Za can be selected as appropriate, the resonance frequency fa is set within an audible frequency band as shown in FIG.
Za <Zco ... [Formula 3]
Each element value such as La and Ca can be selected so that

  By performing such setting, the signal component in the audible frequency band of the power recovery current flowing in the parallel circuit of Za and C0 mainly flows through Za, bypassing C0. As a result, the signal of the audible frequency component that flows through the power recovery capacitor C0 is reduced, and the generation of the beat sound peculiar to the plastic film capacitor can be suppressed.

  In this case, a signal including an audible frequency component flows through Ca constituting the impedance circuit Za. However, if a capacitor having a dielectric structure such as an electrolytic capacitor is used as Ca, for example, the cause of the roaring sound is caused. Therefore, there is no vibration of the dielectric. Furthermore, since the electrolytic capacitor is a relatively large-capacity capacitor, the setting of Ca >> C0 can be easily performed, and the condition of Expression 3 can be sufficiently satisfied.

  In addition, according to the present embodiment, the frequency component in the audible frequency band flowing through the power recovery capacitor can be bypassed, so that the multilayer ceramic capacitor that could not be conventionally used due to its roaring sound, like the plastic film capacitor. Can be used as a power recovery capacitor. Since the multilayer ceramic capacitor is leadless, its high frequency characteristics are good, and its equivalent series resistance (ESR) is small and low loss. Therefore, the performance of the pulse generation circuit can be improved by using the capacitor. . Further, since the capacitor has a chip shape, high-density mounting is possible, and the space for the pulse generation circuit can be saved.

  Further, the present embodiment is not limited to the configuration shown in FIG. 6. For example, the circuit configuration shown in FIG. 8 may be obtained by replacing the inductor La with the resistor Ra. In this case, the characteristics of the impedance circuit Za within the audible frequency band are relatively flat. However, by appropriately selecting the value of each element, the signal of the audible frequency component included in the power recovery current is sufficiently supplied to the impedance circuit Za. Can be bypassed. Further, since the ferrite bead exhibits the same characteristics as the inductor within the audible frequency band, the ferrite bead may be used as the inductor La. This also saves circuit space.

  Further, impedance is obtained by utilizing the inductance component of the wiring pattern (copper foil pattern) of the circuit board (printed board) on which each element constituting the pulse generating circuit such as the power recovery capacitor C0 and the inductors L1 and L2 is mounted. The inductor La of the circuit Za may be configured. In this case, since the current value flowing through the inductor La is small, a relatively narrow wiring pattern can be used. Further, by mounting the capacitor Ca constituting the impedance circuit Za at a relatively distant position on the circuit board and extending the pattern length, an inductance value required as the inductor La can be secured.

  Further, in the circuit of FIG. 6 and the like, the capacitor Ca of the impedance circuit Za does not necessarily need to be connected to the reference potential (ground). For example, as shown in FIG. 9, the capacitor Ca is connected to the positive potential side of the power source Vsus. May be. In this case, since the internal impedance of the power supply can be regarded as a short circuit with respect to a signal in the audible frequency band, the same effect as the circuit described above can be obtained. That is, the impedance circuit Za may be connected to any position in the pulse generation circuit as long as it is equivalently connected in parallel with the power recovery capacitor C0 in the audible frequency band.

  Next, a second embodiment of the display panel driving apparatus according to the present invention will be described. The overall configuration of the display panel driving apparatus according to the second embodiment is the same as that of the first embodiment shown in FIG. 5, and the configuration of the pulse generation circuit included in each of the electrode driving circuits 21 to 41 is the first. The only difference is from one embodiment. Therefore, description and description of the entire configuration of the display panel driving device are omitted.

  FIG. 10 shows the configuration of a pulse generation circuit according to the second embodiment of the present invention.

  In the figure, the circuit block 2 is a column electrode pulse generation circuit included in the column electrode drive circuit 21, the circuit block 3 is an X row electrode pulse generation circuit included in the row electrode drive circuit 41, and the circuit block 4 is a row. 2 is a Y-row electrode pulse generation circuit included in the electrode drive circuit 31. FIG. In each electrode drive circuit, it goes without saying that these pulse generation circuits are provided for the column electrodes Z1 to Zm, the row electrodes X1 to Xn, and Y1 to Yn.

  In each of the pulse generation circuits described above, the capacitors C1 to C3 correspond to power recovery capacitors, respectively, and the impedance circuits Z1 to Z3 connected in parallel to the respective capacitors have been described in the first embodiment. This corresponds to the impedance circuit Za.

  That is, in the time chart of FIG. 11 showing the outline of the operation in the present embodiment, for example, when a power recovery current corresponding to the sustain pulse IPx in the sustain period is applied to the capacitor C1, the signal of the audio frequency component included therein is included. Is bypassed to the impedance circuit Z1. As a result, even when a plastic film capacitor or a multilayer ceramic capacitor is used as the capacitor C1, there is no risk that a dielectric noise will occur.

In each of the embodiments described above, the PDP is taken as an example of the display panel of the display device. However, the embodiment of the present invention is not limited to such a case. For example, inorganic or organic EL The present invention can also be applied to a display panel having a capacitive display light emitting cell.

FIG. 1 is a block diagram showing a configuration of a display panel driving apparatus using a conventional PDP. FIG. 2 is a time chart showing application timings of various drive pulses in the apparatus of FIG. FIG. 3 is a circuit diagram showing a configuration of a pulse generation circuit included in each electrode drive circuit in the apparatus of FIG. FIG. 4 is a time chart showing the relationship between the sustain pulse and the power recovery current. FIG. 5 is a block diagram showing a configuration of a display panel driving apparatus which is an embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a pulse generation circuit according to the first embodiment of the present invention. FIG. 7 is a diagram showing frequency characteristics of impedances of Za and C0 shown in FIG. FIG. 8 is a circuit diagram showing another configuration example of the pulse generation circuit shown in FIG. FIG. 9 is a circuit diagram showing another configuration example of the pulse generation circuit shown in FIG. FIG. 10 is a circuit diagram showing a configuration of a pulse generation circuit according to the second embodiment of the present invention. FIG. 11 is a time chart showing an outline of the operation of the pulse generation circuit shown in FIG.

Explanation of symbols

2 ... Column electrode pulse generation circuit 3 ... X row electrode pulse generation circuit 4 ... Y row electrode pulse generation circuits 10, 11 ... PDP display panels 20, 21 ... Column electrode drive circuits 30, 31 ... Y row electrode drive circuits 40, 41 ... X-row electrode drive circuits 50, 51 ... Drive control circuit

Claims (5)

A display panel comprising a plurality of row electrode pairs, a plurality of column electrodes arranged so as to cross the row electrode pairs, and a capacitive light emitting element disposed at each intersection of the row electrode pairs and the column electrodes And a display panel driving device having pulse generation means for supplying a driving pulse to each of the capacitive light emitting elements,
The pulse generation means includes
A switching circuit for charging and discharging the capacitive light emitting element via an inductor element;
A charge storage circuit connected to the switching circuit for supplying charge to the capacitive light emitting element and recovering charge from the capacitive light emitting element;
Connected in parallel with the charge storage circuit, we saw including a impedance circuit exhibiting values of impedance equal to or lower than the impedance exhibited by said charge accumulation circuitry within the audible frequency range,
The impedance circuit is a series circuit of one of an inductor element and a resistor element and a capacitor element,
The display panel driving apparatus , wherein the capacitor element is an electrolytic capacitor . The display panel driving apparatus according to claim 1, wherein the inductor element is a ferrite bead. The display panel driving apparatus according to claim 1, wherein the inductor element is an inductor component formed by a wiring pattern on a circuit board on which the pulse generation unit is mounted. The display panel driving apparatus according to claim 1, wherein the impedance circuit exhibits a minimum value of impedance within an audible frequency band. The display panel driving apparatus according to claim 1, wherein the impedance circuit exhibits a substantially constant value in an audible frequency band.

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