JP4372191B2 - Charging / discharging device, display device, plasma display panel, and charging / discharging method - Google Patents

Description

  The present invention relates to recovery of electrical energy stored in a capacitance, and more particularly, a charge stored by applying a pulse voltage to a capacitor formed in a cell constituting a screen of a plasma panel display (PDP). The present invention relates to a charge / discharge device, a plasma display panel, and a charge / discharge method.

  By applying a sustain pulse voltage between the display electrodes of a pair of PDPs, electric charge, that is, electric energy is accumulated in the capacitance (capacitance) between the display electrodes. A technique for recovering the electrical energy using a recovery capacitor is known. The electric energy recovered by the capacitor is used for applying a sustain pulse voltage between the next display electrodes.

Japanese Patent Application Laid-Open No. 11-338416 (A) published on December 10, 1999 describes a method for driving a plasma display panel. In this driving method, the potential of the electrode is changed at high speed without using an inductor, and stable power recovery is performed regardless of the pattern of voltage application to a plurality of cells to reduce power consumption. In this driving method, the first terminal of the capacitive element for recovering power is connected to the electrode, and the second terminal of the capacitive element is set lower than the second potential line GND and the potential difference from the second potential line is the first potential. Power recovery is performed by temporarily fixing the potential (−2 Vs), which is larger than the potential difference between the line Vs and the second potential line GND. Charging the cell by connecting the first terminal of the capacitive element in a charged state to the electrode and temporarily fixing the potential of the second terminal so that the potential of the first terminal is higher than the first potential line I do. The address electrodes may be divided into a plurality of groups, and an address driver LSI and a power recovery circuit may be provided for each group. As a result, the sum of the capacitance between the address electrodes per power recovery circuit can be reduced, and the capacity charging / discharging speed can be increased.
Japanese Patent Laid-Open No. 11-338416

Japanese Patent Application Laid-Open No. 11-338418 (A) published on December 10, 1999 describes a method for driving a plasma display panel and a plasma display panel apparatus. In this apparatus, a low-cost reactive power recovery circuit is provided in a PDP divided into a plurality of blocks. Two X electrodes are connected via FET and coil, two Y electrodes are connected via FET and coil, and first X electrode and second Y electrode are connected via FET and coil The second Y electrode and the first X electrode are connected to the FET via a coil. Through the path through the coil between the first and second X electrodes, the energy stored in the capacitance between the first X electrode and the first Y electrode forming a pair is changed to the second X forming another pair. Release into the capacitance between the electrode and the second Y electrode. During the energy release, the potential of the second X electrode reaches the potential Vs. The first X electrode is grounded.
JP 11-338418 A

Japanese Laid-Open Patent Publication No. 2000-338934 (A) published on December 8, 2000 describes a method for driving a capacitive load. In this driving method, in driving a capacitive load that binaryly controls each electrode potential of an electrode pair, one electrode of the electrode pair is connected to a bias potential line via a primary winding of the transformer, and In addition to being connected to the ground potential line through the secondary winding, the other electrode of the electrode pair is connected to the ground potential line, and the capacitance between the electrodes of the electrode pair is charged.
JP 2000-338934 A

Japanese Unexamined Patent Publication No. 2003-76321 (A) published on March 14, 2003 describes a plasma display panel display device. In this display device, in the pair of display electrodes, the sustaining period is a driving waveform process in which the rising period of one electrode is temporally overlapped with the falling period of the other electrode. The interval between the sustain pulses applied to the pair of display electrodes is shortened without making the slope of the rise and fall of the pulse waveform steep.
JP 2003-76321 A

  When the sustain pulse is applied to the display electrode of the PDP through the inductor by the recovery capacitor that stores the recovered electrical energy, the rise time of the sustain pulse tends to be long. The inductor requires an inductance having a required magnitude in order to resonately supply electric energy to the display electrode. If the inductance of the inductor is reduced, the electrical energy recovery efficiency is lowered.

  In order to reduce the width of the pulse applied between the display electrodes and to further shorten the delay from the start of pulse application to the display electrode in the driving of the PDP, the inventors have recovered electric energy. It is desirable to shorten the rise time of the pulse applied to the display electrode without reducing the efficiency, and increase the recovery efficiency of electrical energy without increasing the rise time of the pulse applied to the display electrode. Recognized that is desirable.

  An object of the present invention is to realize a circuit that applies a pulse having a short rise time to an electrode.

  Another object of the present invention is to shorten the delay from the start of pulse application to the electrode until discharge.

  Yet another object of the present invention is to reduce the width of the pulse applied to the electrode.

  Yet another object of the present invention is to increase the recovery efficiency of the electrical energy stored in the charge / discharge capacitance.

  According to the characteristics of the present invention, the charging / discharging device charges / discharges a plurality of capacitances divided into a plurality of groups of g by applying a voltage, and further, an electrical device having one terminal coupled to a common conductor potential. And a plurality of resonant inductors respectively associated with the g groups. One terminal of each of the plurality of resonant inductors is coupled to the capacitance of each of the g groups, and the other terminal of each of the plurality of resonant inductors is coupled to the other terminal of the recovery capacitor. The charging / discharging apparatus further discharges the capacitances of the g groups from the recovery capacitor through first resonant inductors, charging the capacitances of the g groups, respectively. And a second path forming means for recovering electrical energy to the recovery capacitor through g resonance inductances, and a control means for controlling the first and second path forming means. Yeah.

  The present invention also relates to a display device and a plasma display panel including the above-described charging / discharging device.

  Moreover, this invention relates to the method of charging / discharging which implement | achieves the function of the above-mentioned charging / discharging apparatus.

  According to the present invention, the rise time of the pulse applied to the electrode can be shortened, the width of the pulse applied to the electrode can be reduced, and the display can be achieved by ensuring the position of a larger number of pulses within a predetermined period. The display quality of the apparatus can be improved, and the recovery efficiency of the electrical energy accumulated in the charge / discharge capacitance can be increased.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

  FIG. 1 shows a configuration of a typical display device 60 according to an embodiment of the present invention. The display device 60 includes a three-electrode surface discharge type PDP 10 having a display surface composed of an array of n × m cells, and a drive unit 50 for selectively emitting light from the cell array. Used for television receivers, computer system monitors, etc.

  In the PDP 10, display electrodes X and Y (X1, Y1,... Xj, Yj,... Xm, Ym) constituting an electrode pair for generating display discharge are arranged in parallel. Address electrodes A (A1,... Ai,... Am) are arranged so as to be orthogonal to Y. The display electrode X is a sustain electrode, and the display electrode Y is a scan electrode. The display electrodes X and Y typically extend in the row direction or the horizontal direction of the screen, and the address electrodes A extend in the column direction or the vertical direction.

  The drive unit 50 includes a driver control circuit 51, a data conversion circuit 52, a power supply circuit 53, an X electrode driver circuit or X driver circuit 61, a Y electrode driver circuit or Y driver circuit 64, and an address electrode driver circuit or A driver circuit 68. And is optionally implemented in the form of an integrated circuit that may include a ROM. The drive unit 50 is supplied with field data Df indicating the light emission intensities of the three primary colors of R, G, and B, together with various synchronization signals, from an external device such as a TV tuner or a computer. Field data Df is temporarily stored in a field memory in data conversion circuit 52. The data conversion circuit 52 converts the field data Df into subfield data Dsf for gradation display and supplies it to the A driver circuit 68. The subfield data Dsf is a set of 1-bit display data per cell, and the value of each bit represents whether or not each cell needs to emit light in the corresponding subfield SF.

  The X driver circuit 61 includes a reset circuit 62 that applies a voltage for initialization to the display electrode X in order to equalize the wall voltages of a plurality of cells constituting the PDP display surface, and a display discharge in the cells. And a sustain circuit 63 for applying a sustain pulse to the display electrode X. The Y driver circuit 64 includes a reset circuit 65 that applies a voltage for initialization to the display electrode Y, a scan circuit 66 that applies a scan pulse to the display electrode Y in addressing, and a display for generating a display discharge in the cell. And a sustain circuit 67 for applying a sustain pulse to the electrode Y. The A driver circuit 68 applies an address pulse to the address electrode A designated by the subfield data Dsf according to the display data.

  The driver control circuit 51 controls the application of the pulse voltage and the transfer of the subfield data Dsf. The power supply circuit 53 supplies driving power to a required part in the unit.

One picture (screen) is typically composed of one frame period. In interlaced scanning, one frame is composed of two fields, and in progressive scanning, one frame is composed of one field. In the display by the PDP 10, in order to perform color reproduction by binary light emission control, typically one field F in the time series of the input image in such one field period is divided into a predetermined number q of subfields SF. . Typically, each field F is replaced with a set of q subfields SF. Often, these subfields SF are in turn 2 ⁰ , 2 ¹ , 2 ² ,. . . 2 Set the number of display discharges in each subfield SF with different weights such as ^q-1 . The luminance setting of N (= 1 + 2 ¹ +2 ² + ... + 2 ^q-1 ) steps can be performed for each color of R, G, and B by a combination of light emission / non-light emission in subfield units. A field period Tf, which is a field transfer period, is divided into q subfield periods Tsf in accordance with such a field configuration, and one subfield period Tsf is assigned to each subfield SF. Further, the subfield period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission. Typically, the length of the reset period TR and the address period TA is constant regardless of the weight, whereas the number of pulses in the display period TS increases as the weight increases, and the length of the display period TS increases. So long. In this case, the length of the subfield period Tsf is longer as the weight of the corresponding subfield SF is larger.

  FIG. 2 illustrates a schematic drive sequence of output drive voltage waveforms of the X driver circuit 61, the Y driver circuit 64, and the A driver circuit 68 according to an embodiment of the present invention. The illustrated waveform is an example, and the amplitude, polarity, and timing can be changed variously.

  The order of the reset period TR, the address period TA, and the sustain period TS is the same in the q subfields SF, and the driving sequence is repeated for each subfield SF. In the reset period TR of each subfield SF, a negative pulse Prx1 and a positive pulse Prx2 are sequentially applied to all the display electrodes X, and a positive pulse Pry1 is applied to all the display electrodes Y. A negative pulse Pry2 is applied in order. The pulses Prx1, Pry1, and Pry2 are ramp waveforms or blunt waves that gradually increase in amplitude at the rate of change at which microdischarge occurs. The first applied pulses Prx1 and Pry1 are applied to generate appropriate wall voltages of the same polarity in all cells regardless of light emission / non-light emission in the previous subfield SF. By applying the pulses Prx2 and Pry2 to a cell having an appropriate wall charge, the wall voltage can be adjusted to a value corresponding to the difference between the discharge start voltage and the pulse amplitude. The drive voltage applied to the cell is a combined voltage representing the difference in the amplitude of the pulses applied to the display electrodes X and Y.

  In the address period TA, wall charges necessary for maintaining light emission are formed only in the cells that emit light. With all the display electrodes X and all the display electrodes Y biased to a predetermined potential, a negative scan pulse -Vy is applied to the display electrodes Y corresponding to the selected row for each row selection period (scanning time for one row). Apply. Simultaneously with this row selection, the address pulse Va is applied only to the address electrode A corresponding to the selected cell in which the address discharge is to be generated. That is, the potentials of the address electrodes A1 to Am are subjected to binary control based on the subfield data Dsf for m columns of the selected row j. In the selected cell, a discharge occurs between the display electrode Y and the address electrode A. The address discharge is a trigger, and subsequent surface discharge between the display electrodes XY occurs.

  In the sustain period TS, first, a sustain pulse Ps having a predetermined polarity (positive polarity in the illustrated example) is applied to all the display electrodes Y. Thereafter, the sustain pulse Ps is alternately applied to the display electrode X and the display electrode Y. The amplitude of the sustain pulse Ps is the sustain voltage Vs. By applying the sustain pulse Ps, a surface discharge occurs in a cell in which a predetermined wall charge remains. The number of times the sustain pulse Ps is applied corresponds to the weight of the subfield SF as described above. Note that the address electrode A is biased to the voltage Vas having the same polarity as the sustain pulse Ps in order to prevent unnecessary counter discharge throughout the sustain period TS.

  In FIG. 1, a capacitance C formed by each pair of display electrodes Xj and Yj has a capacitance C. The sustain circuits 63 and 67 in FIG. 1 apply the voltages Vs of the two series of sustain pulses Ps in FIG. 2 between the pair of display electrodes Xj and Yj, respectively.

  FIG. 3 shows a normal pulse power supply and recovery circuit 11 having an electrical energy recovery or power recovery function and a clamp circuit 14 used in the sustain circuits 63 and 67 for the PDP 10. The total capacity or the total panel capacity Cpa of all n pairs of display electrodes has a total capacity Cpa = nC, which is formed between all n pairs of display electrodes X and Y, for example on the order of 200 nF.

  In FIG. 3, the pulse power supply and recovery circuit 11 has a capacity Cr (for example, 100 times or more of Cpa) sufficiently larger than the total panel capacity Cpa between the n pairs of display electrodes X and Y, and one terminal is connected to the grounding point. Power recovery capacitor Cr coupled to GND, diodes D1 and D2 each having one terminal connected in series with each other in reverse polarity via switches SW1 and SW3 in series with recovery capacitor Cr, and diodes D1 and D2 And a common resonant inductor L1 having one terminal coupled to the connection point of the other terminal and the other terminal coupled to one (X or Y) of each of the n pairs of display electrodes of the capacitance Cpa. The inductance L of the resonant inductor L1 is typically 200 to 500 nH.

  The clamp circuit 14 includes a constant voltage source Vs of a predetermined voltage Vs coupled via a switch SW2 to a connection point between the other terminal of the resonant inductor L1 and one display electrode (X or Y). The point is coupled to ground point GND through switch SW4.

Referring to FIG. 3, it is assumed that charges of the voltage Vs / 2 are first accumulated in the recovery capacitor Cr, and no charges are accumulated in the total panel capacitance Cpa of n pairs of display electrodes. Therefore, the value of the panel capacitance Cpa, that is, the voltage V _Cpa at each capacitance C is zero (0). When the switch SW1 is turned on at the start of the rise of the pulse Ps, the supply current flows from the recovery capacitor to the total panel capacitance Cpa = nC of the n capacitors C through the switch SW1, the diode D1, and the resonant inductor L1, and the charge q˜ CpaVs is accumulated in the total panel capacitance Cpa, the panel capacitance Cpa, that is, the voltage V _Cpa of each capacitance C rises, and the rise of the pulse Ps is formed. Upon reaching a voltage _{V Cpa} approximately peak voltage Vpmax of the panel capacitance Cpa, switch SW2 of the clamp circuit 14 is turned on. The peak voltage Vpmax is slightly lower than the voltage Vs. Thereafter, the switch SW1 is turned off. The voltage source Vs of the clamp circuit 14 clamps the voltage of the panel capacitance Cpa to the voltage Vs and maintains the panel capacitance Cpa at the voltage Vs. The clamp circuit 14 compensates the voltage V _Cpa of the panel capacitance Cpa so as to become a predetermined voltage Vs. Thereafter, a sustain discharge occurs, and the switch SW2 is turned off.

When the switch SW3 is turned on at the start of the fall of the pulse Ps, a return current flows from the total panel capacitance Cp to the recovery capacitor Cr via the resonant inductor L1, the diode D2, and the switch SW3, and the charges q to CpaVs are recovered. The voltage V _Cpa of the panel capacitance Cpa is additionally accumulated in Cr, and the falling of the pulse Ps is formed. When the voltage _{V Cpa} of the panel capacitance Cpa is almost reached in the negative direction of the peak voltage Vpmin, switch SW4 is turned on. The peak voltage Vpmin is slightly higher than the ground potential GND or 0V. Thereafter, the switch SW3 is turned off. The ground point GND of the clamp circuit 14 clamps the voltage V _Cpa of the panel capacitance _Cpa to the ground potential GND or 0V. Thereafter, the switch SW4 is turned off. In this way, most of the electric charge supplied from the recovery capacitor Cr to the total panel capacitance Cpa, that is, electric power is recovered.

In FIG. 3, the resistor R represents the resistance inherent in the display electrode, and can be regarded as being coupled in series between the inductor L1 and the panel capacitance Cpa. When the value of the panel capacitance Cpa is Cpa = Cp and the value of the inductor L1 is L1 = L, the voltage V _{C p} of the panel capacitance Cp is generally expressed by the following equation.

  The rise time Tr and the peak voltage Vpmax are expressed by the following equations.

Therefore, the rise time Tr is proportional to the square root of the product LCp. The fall time is similarly represented by Tr. Therefore, Cp is divided into g group capacities so that each group capacity Cpa = Cp / g, and the inductance L for each capacity Cpa is multiplied by g ′ which is smaller than g times to be inductance L ₂ = g′L. Then, the rise time and the fall time Tr are shortened (Tr = (g ′ / g) ^1/2 · π (LCp) ^1/2 ).

  In this case, the power recovery efficiency η is expressed by the following equation.

Accordingly, the recovery efficiency η increases approximately according to g or g ′ according to Q = (1 / R) (gg′L / Cp) ^1/2 .

  FIG. 4 shows a pulse voltage application circuit 602 used in the sustain circuits 63 and 67 for the PDP 10 according to an embodiment of the present invention.

  In FIG. 4, the n pairs of display electrodes X and Y of the PDP 10 have a plurality of g groups G1, G2,. . . It is divided into Gg (2 ≦ g ≦ n). The number g is preferably g = 8 to 10, for example, but may be smaller or larger. Groups G1, G2,. . . The number of each display electrode pair in Gg is substantially equal to each other, but it may not be exactly equal to each other. Here, for simplification, the number of display electrode pairs in each group G1 to Gg is assumed to be equal. Accordingly, the n / g pairs of display electrodes X and Y of each group have a total capacitance Cpb = nC / g, for example, a total capacitance Cpb on the order of 25 nF for g = 8.

  The pulse voltage application circuit 602 includes a pulse power supply and recovery circuit 110 having an electrical energy recovery, that is, a power recovery function, clamp circuits 141, 142,. And a signal generation circuit 160.

The pulse power supply and recovery circuit 110 supplies power to the n / g pairs of electrodes X and Y of each group G1 to Gg at the rising edge of the pulse Ps, and recovers power at the falling edge of the pulse Ps. Each of the clamp circuits 141 to 148 clamps the voltage V _Cpb between the n / g pairs of display electrodes X and Y connected in parallel to each other to a predetermined voltage Vs.

  The pulse power supply and recovery circuit 110 includes a power recovery capacitor Cr having one terminal coupled to a common conductor potential or a ground point GND, and a recovery capacitor Cr connected in series to the recovery capacitor Cr and forming a path 1. A diode D1 having an anode (anode) coupled to the terminal via a switch SW1 and a switch SW2 connected to the other terminal of the recovery capacitor Cr so as to form a path 2 connected in series to the capacitor Cr and in parallel with the diode D1. And a diode D2 to which the cathode (cathode) is coupled, and one terminal is coupled to the connection point between the cathode of the diode D1 and the anode of the diode D2, and n / g pairs of display electrodes X of the respective groups G1 to Gg A common resonance in which the other terminal is coupled to one display electrode (X or Y) of Y and Y And inductor L21~L28, contains.

Common resonant inductors L21 to L28 are provided for the n / g pairs of electrodes X and Y of the groups G1 to Gg, respectively. Resonant inductor L21~L28 have equal inductance _{L 2} each other. Inductance _{L 2} is set to a somewhat smaller value g'L (g '<g) than g times the inductance L of the inductor L1 of FIG. 3, for example, a value of 400NH～5mH. For example, when g is 8, the value of g ′ may be 7.

  Each of the power clamp circuits 141-148 has a corresponding group G1, G2,. . . Or switches SW21, SW22,... Corresponding to the connection point of one display electrode X or Y of the display electrode pair X and Y of Gg. . . A constant voltage source Vs of a predetermined voltage Vs coupled through SW28 and switches SW41, SW42,. . . And a common conductor potential or ground point GND coupled via SW48. The clamp circuits 141, 142,... 148 have the same configuration.

The control signal generation circuit 160 is a signal C _SW1 that controls the on / off operation of the switches SW1, SW21,... SW28, SW3, SW41, ... SW48 in the pulse power supply and recovery circuit 110 and the clamp circuits 141 to 148. , C _SW21 ,... C _{SW 28} , C _SW3 , C _{SW41 ,.} The switches SW1, SW21 to SW28, SW3, and SW41 to SW48 may be transistors.

FIG. 5 _shows the on / off states of the control signals C _{SW1 to} C _SW48 of the control signal generation circuit 160 of FIG. 4 for controlling the switches _SW1 to _SW48 and the display electrodes at the time of pulse application according to the embodiment of the present invention. The schematic waveforms of the voltages V _Cpb and V _Cr across the capacitor Cpb and the recovery capacitor Cr are shown.

4 and 5, in the pulse voltage application circuit 602, in the steady operation state after the display device 60 of FIG. 1 is turned on and the recovery capacitor repeats charging and discharging, the voltage Vs / It is assumed that 2 charges are accumulated and no charge is accumulated in the display electrode capacitance Cpb of each group. Therefore, the value of the voltage V _Cpb at each group display electrode capacitance Cpb, that is, each capacitance C is zero (0).

In the timing t1 of the start of the rise of the pulse Ps, the switch SW1 is turned on according to the control signal _{C SW1,} path 1 is formed, each from the recovery capacitor Cr via the respective switches SW1, diode D1 and the resonant inductor L21~L28 group display electrode capacitance Cpb supply current flows, the charge q~CpbVs are accumulated in each group display electrode capacitance Cpb, the voltage _{V Cpb} rises of each group display electrode capacitance Cpb, the rise of the pulse Ps is formed. When the voltage _{V Cpb} of each group display electrode capacitance Cpb peaked voltage Vpmax, switch SW21~SW28 clamp circuit 141-148 is turned in the timing t2 in accordance with the control signal _C SW21 _{-C SW28.} Note that no current flows in the direction opposite to the supply current by the diode D1. Therefore, the switch SW1 may be turned off at an arbitrary timing after reaching the peak voltage until the turn-off timing of the switches SW21 to SW28. The peak voltage Vpmax is slightly lower than the voltage Vs. In this case, the rise time Tr is shorter than in the case of the conventional pulse power supply and recovery circuit 11 of FIG. Voltage source Vs of the clamp circuit 141 to 148 clamps the voltage _{V Cpb} the voltage Vs of each group display electrode capacitance Cpb, to maintain the voltage _{V Cpb} of each group display electrode capacitance Cpb the voltage Vs. Clamp circuit 141 to 148 is compensated so that the voltage _{V Cpb} of the panel capacitance Cpb to a predetermined voltage Vs. Thereafter, sustain discharge occurs, and _SW21 to _SW28 are turned off in accordance with control signals _CSW21 to _CSW28 .

In the timing t3 of the start of the fall of the pulse Ps, the switch SW3 is turned on according to the control signal _{C SW3,} resonant inductor L21~L28 from each group display electrode capacitance Cpb, the recovery capacitor Cr through diode D2 and the switch SW3 A reflux current flows, charges q to gCpbVs are accumulated in the recovery capacitor Cr, the voltage of each group display electrode capacitor Cpb is lowered, and the falling of the pulse Ps is formed. When the voltage _{V Cpb} of each group display electrode capacitance Cpb reaches approximately negative peak voltage Vpmin, switch SW41~SW48 is turned in accordance with the control signal _C SW41 _{-C SW48} at the timing t4. Note that no current flows in the direction opposite to the return current by the diode D2. Therefore, the switch SW3 may be turned off at an arbitrary timing after reaching the peak voltage until the turn-off timing of the switches SW41 to SW48. The peak voltage Vpmin is slightly higher than the ground potential GND or 0V. In this case, the fall time Tr is shorter than that of the conventional pulse power supply and recovery circuit 11 of FIG. Ground point GND of the clamp circuit 141 to 148 is clamped to the ground potential GND or 0V voltage _{V Cpb} of each group display electrode capacitance Cpb. Thereafter, before the next timing t1, the switches _SW41 to _SW48 are turned off in accordance with the control signals _CSW41 to CSW48. Thereafter, the same operation is repeated.

    6A and 6B show a comparison of the waveform of the pulse Ps by the pulse power supply and recovery circuit 11 of FIG. 3 and the pulse power supply and recovery circuit 110 of FIG. In this case, in the pulse power supply and recovery circuit 110, the value L2 of the inductors L21 to L28 is made as small as possible than gL (L2 = g′L <gL). The rise time and fall time Tr of the pulse Ps are shorter than the pulse Ps of the pulse power supply and recovery circuit 11 of FIG.

  7A and 7B show a comparison of the waveforms of another pulse Ps by the pulse power supply and recovery circuit 11 of FIG. 3 and the pulse power supply and recovery circuit 110 of FIG. In this case, in the pulse power supply and recovery circuit 110, the value L2 of the inductors L21 to L28 is set to gL (L2 = gL). The rise time and fall time Tr of the pulse Ps are the same as the pulse Ps of the pulse power supply and recovery circuit 11 of FIG. 3, but the peak voltage Vpmax is higher than the pulse Ps of the pulse power supply and recovery circuit 11 of FIG. The peak voltage Vpmin is low, and the power supply efficiency and the power recovery efficiency η are higher.

  FIG. 8 shows a pulse voltage application circuit 604 according to another embodiment of the present invention, which is a modification of the pulse voltage application circuit 602 of FIG. In the pulse voltage application circuit 604, the inductors L21 to L28 coupled to the cathode of the diode D1 are the same as those in FIG. 4, but the inductors L31, L32,. . . Each inductance L of L38₃Is the inductance L of the inductors L21 to L28₂Greater than (L₃> L ₂). In this case, the rise time Tr of the pulse Ps can be shortened, and the negative peak Vpmin at the fall of the pulse Ps can be further lowered to increase the power recovery efficiency η.

  As an alternative configuration, the arrangement of switch SW1 and diode D1 in FIGS. 4 and 8 may be interchanged. Similarly, the arrangement of the switch SW3 and the diode D2 may be switched.

  FIG. 9 shows the pulse voltage application circuit 602 of FIG. 4 and another pulse voltage application circuit 603 of the same configuration used in the sustain circuits 63 and 67 for the PDP 10 according to another embodiment of the present invention. ing. In this case, the n pairs of display electrodes X and Y have a plurality of 2g groups G1, G2,. . . It is divided into G2g (2 ≦ g ≦ n / 4). A pulse voltage application circuit 602 is provided for the display electrode pairs X and Y of the first g groups G1 to Gg, and a pulse is applied to the display electrode pairs X and Y of the second g groups Gg + 1 to G2g. A voltage application circuit 603 is provided. Similarly, the n pairs of display electrodes X and Y are divided into 3 g or more groups, and three or more pulse voltage application circuits having the same configuration as the pulse voltage application circuit 602 are provided. One pulse voltage application circuit may be associated with each other.

  Similarly, the n pairs of display electrodes X and Y are divided into 2g or more groups, and two or more pulse voltage application circuits having the same configuration as those of the pulse voltage application circuit 604 in FIG. 8 are provided. One pulse voltage application circuit may be associated with each group.

  Although the PDP has been described above, the present invention is not limited to this, and can be applied to, for example, organic and inorganic EL, and electronic paper that displays characters by storing charges by applying voltage. is there.

  The embodiments described above are merely given as typical examples, and it is obvious to those skilled in the art to combine the components of each embodiment, and variations and variations thereof will be apparent to those skilled in the art. Obviously, various modifications may be made to the above-described embodiments without departing from the scope of the invention as set forth in the scope.

FIG. 1 shows the configuration of a typical display device according to an embodiment of the present invention. FIG. 2 illustrates a schematic drive sequence of output drive voltage waveforms of an X driver circuit, a Y driver circuit, and an A driver circuit according to an embodiment of the present invention. FIG. 3 shows a normal pulse power supply and recovery circuit having an electrical energy recovery, that is, a power recovery function, and a clamp circuit used in a sustain circuit for a PDP. FIG. 4 shows a pulse voltage application circuit used in a sustain circuit for PDP according to an embodiment of the present invention. FIG. 5 shows the ON / OFF state of the control signal of the control signal generation circuit of FIG. 4 for controlling the switch and the voltage across the display electrode capacitor and the recovery capacitor when a pulse is applied according to an embodiment of the present invention. The outline waveform of is shown. 6A and 6B show a comparison of the pulse waveforms by the pulse power supply and recovery circuit of FIG. 3 and the pulse power supply and recovery circuit of FIG. 7A and 7B show a comparison of the waveform of another pulse by the pulse power supply and recovery circuit of FIG. 3 and the pulse power supply and recovery circuit of FIG. FIG. 8 shows a pulse voltage application circuit according to another embodiment of the present invention, which is a modification of the pulse voltage application circuit of FIG. FIG. 9 shows the pulse voltage application circuit of FIG. 4 and another pulse voltage application circuit having the same configuration used in the sustain circuit for PDP according to another embodiment of the present invention.

Claims (7)

A charging / discharging device that charges and discharges a plurality of capacitances by applying a voltage,
The plurality of capacitances are divided into a plurality of g groups;
A recovery capacitor for electrical energy recovery in which one terminal is coupled to a common conductor potential;
A plurality of resonant inductors respectively associated with the g groups,
One terminal of each of the plurality of resonant inductors is coupled to the capacitance of each of the g groups, and the other terminal of each of the plurality of resonant inductors is connected to the other terminal of the recovery capacitor with a first switch and Coupled through a second switch ,
A first path forming means for charging the capacitance of each of the g groups from the recovery capacitor via the g resonant inductors by turning on the first switch ;
A second path forming means for discharging the g groups of capacitances by turning on the second switch and recovering electrical energy to the recovery capacitors via the g resonant inductors; ,
Control means for controlling the first and second path forming means,
The electrodes of each group in the g groups are connected to the first voltage source via a third switch, and connected to the common conductor potential via a fourth switch, respectively.
The control means controls the first switch and the second switch provided in common for the capacitances of the g groups, and controls the third switch and the fourth switch to the g A charge / discharge device that controls each group at the same timing . Wherein g-number of the resonance inductor of the first path forming means is characterized in that it is one that has the g-number of less inductance than the resonant inductor in the second path forming unit, according to claim 1 Charge / discharge device. 3. The charging according to claim 1, wherein the g resonant inductors in the first path forming unit are the same as the g resonant inductors in the second path forming unit. 4. Discharge device. The display apparatus containing the charging / discharging apparatus in any one of Claim 1, 2 or 3 . A plasma display panel that performs charging to transfer electrical energy from a recovery capacitor for recovering electrical energy to a cell constituting a screen and power recovery to transfer electrical energy from the cell to the recovery capacitor. There,
A plurality of electrodes are provided corresponding to the cells,
The plurality of electrodes are divided into a plurality of g groups,
The recovery capacitor has one terminal coupled to a common conductor potential,
A plurality of resonant inductors are respectively associated with the g groups,
One terminal of each of the plurality of resonant inductors is coupled to the respective electrodes of the g groups, and the other terminal of each of the plurality of resonant inductors is connected to the other terminal of the recovery capacitor with a first switch and Coupled through a second switch ,
By turning on the first switch, first path forming means for supplying electrical energy from the recovery capacitor to the cells corresponding to the respective electrodes of the g groups via the g resonant inductors. When,
By turning on the second switch, the capacitance of the cells corresponding to the g groups of electrodes is discharged, and electrical energy is recovered in the recovery capacitor via the g resonant inductors. Two path forming means;
Control means for controlling the first and second path forming means ,
The electrodes of each group in the g groups are connected to the first voltage source via a third switch, and connected to the common conductor potential via a fourth switch, respectively.
The control means controls the first switch and the second switch provided in common for the capacitances of the g groups, and controls the third switch and the fourth switch to the g A plasma display panel , wherein each group is controlled at the same timing . Electrodes of the g number of groups is a display electrode which contributes voltage discharge is applied for display, and wherein the voltage to be the applied is the sustain pulse voltage, according to claim 5 Plasma display panel. A charge / discharge method for charging / discharging cells constituting a screen of a plasma display panel,
A plurality of electrodes are provided corresponding to the cells,
The plurality of electrodes are divided into a plurality of g groups,
The recovery capacitor has one terminal coupled to a common conductor potential,
A plurality of resonant inductors are respectively associated with the g groups,
One terminal of each of the plurality of resonant inductors is coupled to the capacitance of each of the g groups, and the other terminal of each of the plurality of resonant inductors is connected to the other terminal of the recovery capacitor with a first switch and Coupled through a second switch,
A first path forming means, a second path forming means,
Control means for controlling the first and second path forming means,
The electrodes of each group in the g groups are connected to the first voltage source via a third switch, and connected to the common conductor potential via a fourth switch, respectively.
The control means controls the first switch and the second switch provided in common for the capacitances of the g groups, and controls the third switch and the fourth switch to the g Control each group at the same time,
The first path forming means turns on the first switch during a rising period of a pulse applied to the cell, thereby allowing g from the other terminals of the recovery capacitor to pass through the g resonance inductors. Charging the capacitance of each of the g groups of electrodes;
The second path forming means turns on the second switch during the falling period of the pulse, thereby discharging the capacitances of the respective electrodes of the g groups through the g resonant inductors. And charging and discharging the electrical energy to the recovery capacitor.

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