JP2003233343A - Display panel driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel driving circuit for driving a display panel capable of being reduced in power consumption at the time of switching. <P>SOLUTION: The display panel driving circuit is provided with a plurality of stages of resonance circuits for exciting to drive capacitance elements of the display panel. Driving pulses having a gradual leading edge part and a gradual trailing edge are generated by making each resonance circuit sequentially operate by changing it over by switching elements. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive for driving a plasma display panel (hereinafter referred to as "PDP") or a display panel having a capacitive load such as electroluminescence (hereinafter referred to as "EL"). The present invention relates to a pulse generation circuit.

[0002]

2. Description of the Related Art Currently, PDs are used as so-called wall-mounted TVs.
A display device using a self-luminous flat panel such as P and EL has been commercialized. FIG. 1 is a block diagram showing a schematic configuration of such a display device. In FIG. 1, a PDP 10 as a display panel includes row electrodes Y _{1 to} Y _n and X ₁ that form a row electrode pair corresponding to each row (first row to nth row) of one screen with a pair of X and Y. .About.X _n . Furthermore, PDP1
0 is each column (first column to m-th column) of one screen which is orthogonal to the row electrode pair and which sandwiches a dielectric layer and a discharge space (not shown).
Corresponding column electrodes Z _{1 to} Z _m are formed. Note that one discharge cell C _{(i, j)} is formed at the intersection of one pair of row electrodes (X, Y) and one column electrode Z.

The row electrode driving circuit 30 first generates a positive voltage reset pulse RP _y as shown in FIG. 2 and applies it to each of the row electrodes Y _{1 to} Y _n at the same time. At the same time, the row electrode drive circuit 40 generates a negative voltage reset pulse RP _x and applies it to all the row electrodes X _{1 to} X _n at the same time. By simultaneously applying the reset pulses RP _x and RP _y , all discharge cells of the PDP 10 are discharge-excited to generate charged particles. After the end of this discharge, a predetermined amount of wall charges are uniformly formed on the dielectric layers of all the discharge cells (reset process).

After the reset process is completed, the column electrode drive circuit 20 generates pixel data pulses DP _{1 to} DP _n according to the pixel data corresponding to each of the first row to the nth row of the screen. Then, these pixel data pulses are sequentially applied to the column electrodes Z _{1 to} Z _m as shown in FIG. on the other hand,
The row electrode drive circuit 30 uses the pixel data pulses DP _{1 to} DP _n.
Scan pulse SP of negative voltage according to each application timing
To generate. Then, as shown in FIG. 2, this is sequentially applied to the row electrodes Y ₁ to Y _n .

Among the discharge cells belonging to the row electrode to which the scan pulse SP is applied, discharge is generated in the discharge cell to which the positive voltage pixel data pulse is further applied at the same time, and most of the wall charges are lost. On the other hand, since discharge does not occur in the discharge cells to which the scan pulse SP is applied but the positive voltage pixel data pulse is not applied, the wall charges remain. At this time, the discharge cells in which the wall charges remain are the light emitting discharge cells, and the discharge cells in which the wall charges have disappeared are the non-light emitting discharge cells (addressing process).

When the address process is completed, the row electrode drive circuit 30 continuously applies a positive voltage sustaining pulse IP _Y to each of the row electrodes Y _{1 to} Y _n , as shown in FIG. At the same time, the row electrode drive circuit 40 continuously applies a positive voltage sustain pulse IP _X to each of the row electrodes X _{1 to} X _n at a timing deviated from the application timing of the sustain pulse IP _Y. During the period in which the sustain pulses IP _X and IP _Y are alternately applied, the light emitting discharge cells in which the wall charge remains remain discharge and emit light and maintain the light emitting state (sustain discharge step).

The drive control circuit 50 shown in FIG. 1 generates various switching signals for generating various drive pulses as shown in FIG. 2 based on the timing of the supplied video signal. Then, these are supplied to each of the column electrode drive circuit 20 and the row electrode drive circuits 30 and 40. That is, the column electrode drive circuit 20 and the row electrode drive circuit 3
Each of 0 and 40 generates various drive pulses shown in FIG. 2 according to the switching signal supplied from the drive control circuit 50.

Each of these electrode drive circuits is provided inside.
And the reset pulse RP _YAnd sustain pulse I
P_YDisplay panel drive circuit that generates various drive pulses
An example of the path is shown in FIGS. Any of these circuits
The resonance of the LC circuit consisting of inductor and capacitor
Using the charge and discharge of the capacitor by
Is generated. That is, each discharge of the PDP 10
Note that the cell is a capacitive load,
Inductor, which is a conductive element, and a capacitor for power recovery
To form a resonance circuit. And FET etc.
Using such switching elements,
Generate desired pulse by exciting at timing
It is.

Incidentally, the circuit of FIG. 3 is conventionally widely used as such a display panel driving circuit, and will be referred to as a "single-stage resonance circuit" hereinafter for convenience of explanation. Also, FIG.
The circuit shown in (1) is intended to reduce the breakdown voltage of the element used in the one-stage resonant circuit, and will be hereinafter referred to as "double resonant circuit".

[0010]

By the way, as a voltage for driving a capacitive load such as a PDP with a resonance current, a relatively high voltage value of several tens to one hundred and several tens of volts is generally used. Therefore, in the conventional display panel drive circuit shown in FIGS. 3 and 4, the resonance current that flows when charging and discharging a capacitive load also increases, and a large power loss occurs when the load is driven. there were.

In particular, in the double resonance circuit shown in FIG. 4, although the breakdown voltage of the elements used in the circuit is reduced as compared with the one-stage resonance circuit, there is a possibility that the following problems may occur. That is, in the double resonance circuit, in order to increase the potential applied to the resonance circuit step by step, a potential transition circuit including a switching element and a capacitor is added to the one-stage resonance circuit shown in FIG. Therefore, the switching element S forming the potential transition circuit to which the resonance current is applied
After passing through W1 or SW2, extra power loss will occur due to the ON resistance of the element. Further, a parasitic capacitance Ck is generated between the positive and negative potential lines (OUTa and OUTb in FIG. 4) of the pulse output and the ground or the power supply, and the Ck is excited by the power supply voltage V / 2, so that n × There is a possibility that reactive power of Ck × (V / 2) ² may be further generated. In the above equation, n represents the number of repetitions of the drive pulse per unit time.

The present invention has been made in order to solve these problems, and provides a display panel drive circuit which can use a low breakdown voltage switching element and can reduce power consumption when a load is driven. With the goal.

[0013]

The present invention includes a row electrode group,
In driving a display panel having a column electrode group arranged to intersect the row electrode group and a capacitive light emitting element arranged at each intersection of the row electrode group and the column electrode group, the capacitive light emission is performed. A display panel drive circuit that supplies a drive pulse to each of the elements through an output terminal, and a reference potential generation circuit that sequentially generates a plurality of reference potentials, and the capacitive light emitting element is connected through the output terminal. A resonance circuit that forms a resonance circuit and generates a plurality of resonance voltages on the output terminal that rise and fall at different timings from each of the plurality of reference potentials, and respective peak voltages of the resonance voltage. Is clamped to any of the plurality of reference potentials, and a rising edge that gradually rises and a falling edge that gradually falls with the maximum value of the plurality of reference potentials as its amplitude. Characterized in that a pulse having and a clamp circuit for generating on said output terminals for generating as the driving pulse.

[0014]

FIG. 5 is a block diagram showing the structure of a display panel drive device having a display panel drive circuit according to the present invention. In FIG. 5, P as a display panel
The DP 10 includes row electrodes Y _{1 to} Y _n and X _{1 to} X _n that form a pair of row electrodes corresponding to each row (first row to nth row) of one screen with a pair of X and Y. Further, the PDP 10 has column electrodes Z _{1 to} Z that are orthogonal to the row electrode pairs and correspond to each column (first column to m-th column) of one screen with a dielectric layer and a discharge space (not shown) in between. _m is formed. One discharge cell C _{(i, j)} is formed at the intersection of one pair of row electrodes (X, Y) and one column electrode Z.

The row electrode drive circuit 31 generates each of the positive voltage reset pulse RP _y , the negative voltage scan pulse SP, and the sustain pulse IP _y as shown in FIG.
These are row electrodes Y _{1 to} Y _n at the timing shown in FIG.
To each of. On the other hand, the row electrode drive circuit 41 is shown in FIG.
, A negative voltage reset pulse RP _x and a positive voltage sustain pulse IP _x are generated, and these are applied to each of the row electrodes X _{1 to} X _n at the timing of FIG.

The column electrode driving circuit 21 is arranged in the first row to the n-th screen of the screen.
Pixel data pulses DP _{1 to} DP _n corresponding to the pixel data corresponding to each row are generated, and these are sequentially applied to the column electrodes Z _{1 to} Z _m as shown in FIG. Drive control circuit 51
Generates various switching signals for generating various drive pulses as shown in FIG. 2 based on the supplied video signal. Then, these signals are supplied to each of the column electrode drive circuit 21 and the row electrode drive circuits 31 and 41.

Incidentally, these row electrode drive circuits 31 and 4
1. Inside each of the column electrode drive circuits 21, a display panel drive circuit for driving a display panel according to the present invention is provided, as shown in FIG. 6 or FIG. 11 described later. FIG. 6 shows a first embodiment of the display panel drive circuit according to the present invention, and the configuration of the circuit will be described below.

In FIG. 6, the negative terminal (0 [V]) of the DC power source (not shown) that generates the DC voltage + V [V] is the PDP.
It is connected to the ground potential G (0 [V]) which is the ground potential of 10. In addition, the positive side terminal (+ V
[V]) is connected to the first power supply terminal Vmax of this circuit. On the other hand, the switch B2- is connected to the power supply terminal Vmax.
One end of SW is connected, and the other end of the switch B2-SW is connected to the anode of the diode G2-Di, the output terminal OUT,
It is connected to the serial branch U2 and the serial branch D2.

The output terminal OUT is an output terminal for a pulse signal reaching each row electrode or column electrode of the PDP 10, and is the PDP.
The capacitance component C0 of the discharge cell C _{(i, j)} in 10 will be connected. In addition, the capacitance component C from the output terminal OUT
In the path reaching 0, an output driver circuit may be inserted as necessary. Also, the serial branch U
2 is an inductor U2-L, a diode U2-Di,
And a switch U2-SW. Similarly, the series branch D2 refers to a series circuit including an inductor D2-L, a diode D2-Di, and a switch D2-SW.

The other ends of the series branch U2 and the series branch D2 are both connected to one end of the capacitor C2, and the portion composed of the series branch U2, the series branch D2, and the capacitor C2 is the first in the present embodiment. 2 resonance circuits are configured. On the other hand, the cathode of the diode G2-Di is the switch G.
It is connected to one end of 2-SW. And switch G
The other end of 2-SW is connected to the anode of the diode B1-Di, the other end of the capacitor C2, one end of the capacitor C3, and the second power supply terminal Vmid of this circuit. In this embodiment, Vmid is the first power supply terminal Vmax.
It is assumed that + V / 2 [V], which is a potential of 1/2 of the above, is supplied.

The cathode of the diode B1-Di is connected to one end of the switch B1-SW, and the switch B1-S
The other end of W is one end of the switch G1-SW, the series branch U1,
It is connected to the series branch D1 and the output terminal OUT. The series branch U1 includes an inductor U1-L and a diode U1-.
A serial circuit composed of Di and switches U1-SW. Similarly, the series branch D1 refers to a series circuit including an inductor D1-L, a diode D1-Di, and a switch D1-SW.

The other ends of the series branch U1 and the series branch D1 are both connected to one end of the capacitor C1.
Similar to the second resonance circuit, the series branch U1 and the series branch D
1 and the capacitor C1 form a first resonance circuit in this embodiment. On the other hand, the other end of the switch G1-SW is connected to the other end of the capacitor C1, the other end of the capacitor C3, and the ground potential G (0 [V]).

Next, regarding the operation of the display panel drive circuit according to the first embodiment of the present invention, the circuit diagram of FIG. 6 and FIG.
The description will be given with reference to the time chart shown in FIG. Incidentally, the switching element included in the circuit is, for example, F
It may be configured by utilizing between the drain terminal and the source terminal of ET, or other switching elements may be used.
When the FET is used, it is assumed that the switching element is turned on / off by a control signal applied to the gate terminal of the FET.

Further, all the switches shown in FIG. 6 are controlled in their on / off states by the logic level of the control signal supplied from the drive control circuit 51 shown in FIG. However, in the following description, in order to simplify the description, description of each control signal supplied from the drive control circuit 51 is omitted, and only changes in ON / OFF state of each switch are shown in time series. To do.

In the following description, all the names of the respective switches will be represented by only reference numerals such as U1-SW. Similarly, other elements such as capacitors and inductors will be indicated only by the reference numerals such as C1 and U1-L. First, immediately before time t0 shown in the time chart of FIG. 7, U1-SW, B1-
The switches SW, U2-SW, B2-SW are off, and D2-SW, G2-SW, D1-SW, G1-SW
Is on. Figure 8 shows the circuit connection in this case.
Is shown in the connection diagram. As is clear from the figure, the output terminal OUT is connected to the ground potential via G1-SW, and the potential is the ground potential of the PDP, that is, 0 [V].

In the present embodiment, C1 and C2
Is + V / 4 by means not shown when the power of this circuit is turned on.
It is assumed that the battery is charged to the potential [V]. Also, C3, which is connected between Vmid and ground,
It goes without saying that the battery is charged to + V / 2 [V] which is the potential of Vmid. Therefore, a positive potential is applied to all the cathodes of the diodes shown in FIG. On the other hand, since the output terminal OUT is grounded as described above, the anodes of the diodes are all 0 [V]. Therefore, all the diodes shown in FIG. 8 are non-conductive, and the potential on the cathode side of each diode is the output terminal O.
There is no risk of affecting the UT.

Next, at time t0, the D2-SW, G2-SW, D1-SW, and G1- that have been on until now are turned on.
Each switch of SW is turned off and U1-SW is turned on. As a result, the output terminal OUT is U1-L, U1-
It is connected to C1 via the serial branch U1 of the first resonant circuit consisting of Di and U1-SW. As mentioned above, C1 is +
It is charged to a potential of V / 4 [V], and the output terminal OU
The potential of T is 0 [V]. Therefore, the charge charged in C1 passes through the above-mentioned series branch U1 to the output terminal OU.
It moves from T to the capacitance component C0 of the discharge cell C _{(i, j)} of the PDP 10. That is, the current for charging C0 starts to flow via the serial branch U1.

As C0 is charged, the potential of C0, that is, the potential of the output terminal OUT gradually rises from the ground potential 0 [V]. Incidentally, such an increase in potential is caused by a resonance phenomenon due to U1-L and C0. Therefore, the rate of increase in potential during the period of increase in resonance current is large, and the rate of increase in potential during the period of decrease in resonance current tends to saturate. Further, the increase in the potential due to the resonance phenomenon occurs beyond the initial charge potential + V / 4 [V] in C1.

The potential of the output terminal OUT continues to rise again, but cannot rise to + V / 2 [V] due to the loss due to the resistance component, and the diode U1 is reached when the resonance current becomes zero.
-Di turns off and is clamped at a potential lower than + V / 2 [V]. At time t1 after this clamp, B
1-SW is turned on, and the output terminal OUT is connected to Vmid via B1-SW and B1-Di. As a result, the potential of the output terminal OUT rises all the way to the potential of Vmid, + V / 2 [V], and is clamped to the potential of + V / 2 [V].

At the subsequent time t2, U2-
SW is turned on and the output terminals OUT are U2-L and U2-
A series branch U of the second resonance circuit composed of Di and U2-SW
It is connected to C2 via 2. As described above, the initial charging potential of C2 is + V / 4 [V]. However, in the circuit of FIG. 6, C2 has a charging potential of + V, which is the charging potential of C3.
/ 2 [V] is superposed as the bias potential. That is, a bias potential is added to the potential of C2 viewed from the output terminal OUT, and (+ V / 4 [V]) + (+ V / 2 [V]) = + 3V /
It becomes 4 [V]. Therefore, at the time t2 shown in the time chart of FIG. 7, the potential of C2 is higher by + V / 4 [V] than the potential of the output terminal OUT (+ V / 2 [V]). Due to this potential difference, C2 to the serial branch U
The charging current again starts to flow in C0 via 2 and the output terminal OUT.

As C0 is charged again, the output terminal O
The potential of UT starts to rise gradually from + V / 2 [V].
Incidentally, such a rise in potential is caused by a resonance phenomenon due to U2-L and C0. Therefore, if the circuit constants of the inductors and the like in the first and second resonance circuits are set to be the same, the rise in the potential of the output terminal OUT causes the resonance phenomenon due to the first resonance circuit shown at the time points t0 to t1. The same tendency as the case is shown.

In the time chart of FIG. 7, B1-SW which plays a role of clamping the potential of the output terminal OUT to + V / 2 [V] is not turned off at the time of t2. This is because when U2-SW is turned on, the potential of the cathode of B1-Di becomes higher than + V / 2 [V] which is the potential of the anode thereof, and B1-SW becomes non-conductive and the output terminal OU.
This is because the T clamp is automatically released.

The potential of the output terminal OUT continues to rise again, but cannot rise to + V [V] due to the loss due to the resistance component, and the diode U2-D is reached when the resonance current becomes zero.
i is turned off and clamped to a potential lower than + V [V]. B2-SW is turned on at time t3 after this clamping. As a result, the output terminal OUT becomes B2-
It is directly connected to the power supply terminal Vmax via SW. Therefore, the potential of the output terminal OUT rises all the way to + V [V] which is the potential of Vmax, and the maximum potential of the circuit + V.
It is clamped to [V].

FIG. 9 shows the connection state of the display panel drive circuit when the output terminal OUT is clamped to the maximum potential + V [V] after the time point t3. In the figure,
All switches U1-SW, B1-SW, U2-SW, B2-SW are turned on, but the positive maximum potential + V [V] is applied to the cathodes of the diodes shown in the figure. Has become. Therefore, all of these diodes are non-conductive, and there is no possibility that the potential on the anode side of each diode affects the output terminal OUT.

Next, the fall of the pulse waveform from the output terminal OUT will be described. First, at time t4 in the time chart shown in FIG. 7, the U1-SW, B1-SW, U2-SW, and B2-SW switches that have been on until now are turned off, and the D2-SW is turned on. As a result, the output terminal OUT becomes D2-L, D2-D.
i and a series branch D2 of the second resonance circuit composed of D2-SW
Is connected to C2 via. That is, C0 connected to the output terminal OUT is connected to C2 via the series branch D2.

As described above, the potential of the output terminal OUT, that is, C2 as viewed from C0 is + 3V / 4 [V] including the bias potential of C3. On the other hand, C0 is charged to the maximum potential + V [V] in the process from time t3 to t4. Therefore, in this case, the charge stored in C0 is changed to C2.
Will be collected. That is, the resonance current due to D2-L and C2 of the second resonance circuit starts to flow in the form of discharging from C0 to C2. Then, the output terminal OUT has a maximum potential + V [V] when the B2-SW is turned off.
Clamp has been released, so with the discharge of C0,
The potential gradually decreases as shown in FIG.

The direction of the resonance current at this time is opposite to the direction of the rise of the potential described above, but D2 in the resonance circuit
If the circuit constants of the branch and the U2 branch are the same, the state of potential change shows the same tendency as at the rising. That is, the potential drop rate when the resonant current increases is large, and the potential drop rate when the resonant current decreases is saturated. In addition, V / 4 [V] which is a potential difference between C0 and C2 at the start of discharge of C0
Beyond that, the potential of C0, that is, the potential of the output terminal OUT drops.

At time t5 immediately before the potential of the output terminal OUT drops to + V / 2 [V], G2-SW is turned on, and this time, the output terminal OUT becomes G2-SW and G2-.
Connected to Vmid via Di. As a result, the potential of the output terminal OUT is + V / 2 which is the potential of Vmid.
It drops all the way to [V] and is clamped at + V / 2 [V].

At the subsequent time t6, this time D1-
SW is turned on, and the output terminal OUT is D1-L, D1.
-Di and D1-SW are connected to C1 via the series branch D1 of the first resonant circuit. As described above, the charging potential of C1 is + V / 4 [V], and the potential of the output terminal OUT at time t6, that is, the potential of C0 is + V / 2 [V].
Has become. Therefore, this time, the charge is collected from C0 to C1, and the resonance current due to D1-L and C1 of the first resonance circuit starts to flow. As a result, the potential of the output terminal OUT also starts to drop from + V / 2 [V].

The potential of the output terminal OUT further decreases,
At time t7 immediately before reaching 0 [V], G1-SW is turned on, and the output terminal OUT is directly connected to the ground potential 0 [V]. As a result, the potential of the output terminal OUT is clamped to the ground potential 0 [V]. The operation described above is repeated in the display panel drive circuit of FIG. 6 based on the control signals of the respective switches supplied from the drive control circuit 51 shown in FIG. As a result, the pulse waveform shown in FIG. 7 appears periodically at the output terminal OUT of the display panel drive circuit.

When the display panel drive circuit according to the present embodiment is used in the row electrode drive circuits 31 and 41 as, for example, a generation circuit (sustain driver) of sustain pulses IPy and IPx, pulse waveforms of the Y electrode and the X electrode are shown. The situation is shown in the time chart of FIG. In the circuit shown in FIG. 6, the power supply voltage is + V [V] and + V / 2.
As [V], a so-called positive polarity pulse generating circuit is used, but the present embodiment is not limited to this. For example,
It is also possible to configure a negative pulse generation circuit by using a negative power supply and reversing the polarity of the diode.

Further, in this embodiment, the second power supply terminal Vm
The shape of the pulse waveform can be adjusted by changing the potential of id. Therefore, it becomes possible to further optimize the shape of the pulse waveform in order to achieve the effect of reducing the electric power, depending on the situation of the load to be driven. Incidentally, in the present embodiment, the potential of the capacitor C3 in FIG. 6 automatically converges to + V / 2 [V] by the operation of the circuit. Therefore,
When the display panel drive circuit is operated with the potential of Vmid fixed at + V / 2 [V], the DC power supply applied to Vmid can be omitted.

Next, a second embodiment of the display panel drive circuit according to the present invention will be described. The configuration of the second embodiment is shown in the circuit diagram of FIG. In the figure, DC voltage + V
The ground terminal (0 [V]) of a DC power source (not shown) that generates / 2 [V] and -V / 2 [V] is connected to the ground potential G (0 [V]) which is the ground potential of the PDP 10. ing.
Then, the positive terminal (+ V / 2) of the DC power source (not shown)
[V]) is the first power supply terminal V1 of the circuit, and the negative side terminal (-V / 2 [V]) is the second power supply terminal V2 of the circuit.
, Respectively.

On the other hand, the switch B2-S is connected to the power supply terminal V1.
One end of W is connected, and the other end of the switch B2-SW is connected to the anode of the diode G2-Di, the series branch U2, the series branch D2, and the output terminal OUT. The output terminal OUT is an output terminal of a pulse signal reaching each row electrode or column electrode of the PDP 10, and the capacitance component C0 of the discharge cell C _{(i, j) in} the PDP 10 is connected to the output terminal OUT. Note that an output driver circuit may be inserted as necessary in the path from the output terminal OUT to the capacitance component C0.

The series branch U2 is an inductor U2-
A series circuit composed of L, a diode U2-Di, and a switch U2-SW. Similarly, the series branch D2 refers to a series circuit including an inductor D2-L, a diode D2-Di, and a switch D2-SW. Series branch U described above
2 and the other end of each of the series branches D2 are both connected to one end of the capacitor C2, and the portion formed of the series branch U2, the series branch D2, and the capacitor C2 is the second in the present embodiment.
Constitutes a resonance circuit of.

On the other hand, the cathode of the diode G2-Di is connected to one end of the switch G2-SW. The other end of the switch G2-SW is connected to the anode of the diode B1-Di, the other end of the capacitor C2, one end of the capacitor C1 described later, and the ground potential. Diode B
The cathode of 1-Di is connected to one end of the switch B1-SW, and the other end of the switch B1-SW is connected to the switch G1.
It is connected to one end of -SW, the output terminal OUT, the series branch U1, and the series branch D1. The series branch U1 includes an inductor U1-L, a diode U1-Di, and a switch U1-.
A series circuit composed of SW. Similarly, the series branch D1 refers to a series circuit including an inductor D1-L, a diode D1-Di, and a switch D1-SW.

The other ends of the series branch U1 and the series branch D1 are both connected to one end of the capacitor C1.
Similar to the second resonance circuit, the series branch U1 and the series branch D
1 and the capacitor C1 form a first resonance circuit in this embodiment. On the other hand, the other end of the switch G1-SW is V2 (-V / 2) which is the second power supply terminal of this circuit.
[V]).

Next, the operation of the display panel drive circuit according to the second embodiment of the present invention will be described with reference to the circuit diagram of FIG. 11 and the time chart shown in FIG. Incidentally, the switching element included in the circuit is, for example,
It may be configured by utilizing between the drain terminal and the source terminal of the FET, or other switching element may be used. When the FET is used, it is assumed that the switching element is turned on / off by a control signal applied to the gate terminal of the FET.

Further, all the switches shown in FIG. 6 are controlled in their on / off states by the logic level of the control signal supplied from the drive control circuit 51 shown in FIG. However, in the following description, in order to simplify the description, description of each control signal supplied from the drive control circuit 51 is omitted, and only changes in ON / OFF state of each switch are shown in time series. To do.

In the following description, all the names of the respective switches are indicated by only the symbols such as U1-SW. Similarly, other elements such as capacitors and inductors will be indicated only by the reference numerals such as C1 and U1-L. First, immediately before time t0 shown in the time chart of FIG. 12, U1-SW, B1
-SW, U2-SW, B2-SW switches are off, and D2-SW, G2-SW, D1-SW, G1-S
W is on. Therefore, the output terminal OUT is
It is connected to the power supply terminal V2 via 1-SW, and the potential thereof is -V / 2 [V]. Therefore, the output terminal O
The capacitance component C0 of the discharge cell C _{(i, j)} of the PDP 10 connected to the UT is charged to the potential of −V / 2 [V] by the time t0.

In the present embodiment, C1 and C2 are
When the power of this circuit is turned on,
It is assumed that the battery is charged to a potential of V / 4 [V], + V / 4 [V]. Next, at time t0, D2-SW, G2-SW, D1-SW, which have been on until now,
Each switch of G1-SW is turned off and U1-SW is turned on. As a result, the output terminal OUT is U1-L,
It is connected to C1 via the series branch U1 of the first resonant circuit composed of U1-Di and U1-SW.

As described above, C1 is charged to the potential of -V / 4 [V], and the potential of the output terminal OUT is -V / 2.
[V]. Therefore, due to the potential difference, the charging current starts to flow from C1 to C0 via the series branch U1 and the output terminal OUT. As a result, the potential of C0, that is, the potential of the output terminal OUT gradually rises from -V / 2 [V]. By the way, the increase in the potential is caused by U1-L and C0.
It is caused by the resonance phenomenon caused by. Therefore,
The rate of increase in potential during the period when the resonance current increases is large, and the rate of increase in potential during the period when the resonance current decreases tends to be saturated. Furthermore, the rise in the potential due to the resonance phenomenon occurs beyond the initial charging potential −V / 4 [V] at C1.

The potential of the output terminal OUT continues to rise again, but cannot rise to 0 [V] due to the loss due to the resistance component, and when the resonance current becomes 0, the diode U1-Di.
Turns off and is clamped to a potential lower than 0 [V]. At time t1 after this clamping, B1-SW is turned on and U1-SW is turned off. As a result, the output terminal OUT is connected to the ground potential via B1-SW and B1-Di, and the potential of the output terminal OUT is clamped at 0 [V].

At time t2 thereafter, U2-
SW is turned on and the output terminals OUT are U2-L and U2-
A series branch U of the second resonance circuit composed of Di and U2-SW
It is connected to C2 via 2. As mentioned above, C2 is + V
It is charged to / 4 [V], and its potential is output terminal O
The potential of the UT is higher than 0 [V]. Therefore, due to such a potential difference, from C2 to the serial branch U2 and the output terminal O
The charging current begins to flow again to C0 via UT.

As C0 is charged again, the output terminal O
The potential of UT starts to rise gradually from 0 [V]. Incidentally, such a rise in potential is caused by a resonance phenomenon due to U2-L and C0. Therefore, the output terminal OU
If the circuit constants of the inductors and the like in the first and second resonant circuits are set to be the same, the potential increase of T will occur at the previous time t0.
The same tendency as in the case of resonance by the first resonance circuit indicated by t1 is obtained.

The potential of the output terminal OUT continues to rise again, but cannot rise to + V / 2 [V] due to the loss due to the resistance component, and the diode U2 is reached when the resonance current becomes zero.
-Di turns off and is clamped at a potential lower than + V / 2 [V]. B2 at time t3 after this clamp
-SW is turned on. As a result, the output terminal OUT
Is directly connected to the power supply terminal V1 via B2-SW. Therefore, the potential of the output terminal OUT rises all the way to the potential of V1, + V / 2 [V], and is clamped at that potential.

Next, the fall of the pulse waveform from the output terminal OUT will be described. First, at time t4 in the time chart shown in FIG. 12, the switches B1-SW, U2-SW, and B2-SW that have been on until now are turned off, and D2-SW is turned on. As a result, the output terminal OUT has D2-L, D2-Di, and D-
C through the series branch D2 of the second resonance circuit composed of 2-SW
Connected to 2. That is, C0 connected to the output terminal OUT is connected to C2 via the series branch D2.

As described above, the charging potential of C2 is + V / 4.
[V], while C in the process from time t3 to time t4
0 is charged to + V / 2 [V]. Therefore, in this case, the electric charge accumulated in C0 is recovered by C2, and the resonance current due to D2-L and C2 of the second resonance circuit starts to flow in the form of discharging from C0 to C2. Then, the output terminal OUT is + V / when B2-SW is turned off.
Since the 2 [V] clamp is released, the potential thereof gradually decreases as C0 is discharged, as shown in FIG.

The direction of the resonance current at this time is opposite to that at the rise of the potential, but if the circuit constants of the branches in the resonance circuit are the same, the state of potential change is the same as at the rise. Shows the tendency of. That is, the potential drop rate when the resonant current increases is large, and the potential drop rate when the resonant current decreases is saturated. Further, the potential of C0, that is, the potential of the output terminal OUT drops, exceeding V / 4 [V], which is the potential difference between C0 and C2 at the start of discharge of C0.

At time t5 immediately before the potential of the output terminal OUT drops to 0 [V], G2-SW is turned on and D2-SW is turned on.
SW is turned off. As a result, the output terminal OUT is
It is connected to the ground potential via G2-SW and G2-Di, and the potential drops to the ground potential all at once.
It is clamped to [V]. At time t6 thereafter,
This time, D1-SW is turned on and the output terminal OUT is U
It is connected to C1 via the series branch D1 of the first resonant circuit consisting of 1-L, D1-Di, and D1-SW. As described above, the charging potential of C1 is −V / 4 [V], and the time t
6, the potential of the output terminal OUT, that is, the potential of C0 is 0
It is [V]. Therefore, this time, the charge is collected from C0 to C1, and U1 of the first resonant circuit is collected.
-Resonant current due to L and C1 begins to flow. As a result, the potential of the output terminal OUT also starts to drop from 0 [V] again.

The potential of the output terminal OUT further decreases,
At time t7 immediately before −V / 2 [V], G1-
SW is turned on, and the output terminal OUT is the power supply terminal V2.
It is directly connected to (-V / 2 [V]). As a result, the potential of the output terminal OUT is clamped at -V / 2 [V]. The above-described operation is repeated in the display panel drive circuit of FIG. 11 based on the control signal of each switch supplied from the drive control circuit 51 shown in FIG.
As a result, the pulse waveform shown in FIG. 12 periodically appears at the output terminal OUT of the display panel drive circuit.

When the display panel drive circuit according to the present embodiment is used in the row electrode drive circuits 31 and 41, for example, as a generation circuit (sustain driver) of sustain pulses IPy and IPx, the pulse waveforms of the Y electrodes and the X electrodes are shown. The situation is shown in the time chart of FIG. The pulse waveform produced by the display panel drive circuit of the present embodiment has an ambipolar amplitude of −V / 2 to + V / 2. Therefore, the pulse train supplied from each row electrode drive circuit to each electrode is
The phase is controlled by the drive control circuit 51 so that the potential difference Vdmax between the Y electrode and the X electrode becomes equal to or higher than the discharge start voltage.

As described above in detail, according to the present invention, the potential transition circuit in the conventional double resonance circuit shown in FIG. 4 can be omitted by using the resonance circuits connected in multiple stages. As a result, it is possible to prevent power loss due to the switching element of the potential transition circuit and generation of reactive power due to excitation of the parasitic capacitance, and to suppress power consumption when driving the display panel.

Although the first and second embodiments described above use only two resonant circuits, the present invention is not limited to these embodiments. That is, the display panel drive circuit according to the present invention may be configured by combining n stages (n ≧ 3) of resonance circuits having different amplitude ranges. However, in the case of the second embodiment, since it is necessary to target the pulse waveform with respect to the ground potential, n must be an even number of stages. By adopting such a configuration, it becomes possible to further reduce the breakdown voltage of the used element, and further it is possible to finely optimize the pulse waveform for the purpose of power reduction.

In the first and second embodiments, the constants of the inductors and the like in each resonance circuit are assumed to be the same for the sake of clear explanation, but the present invention is not limited to such cases. That is, according to the present invention, the constants of the inductors and the like in the resonant circuits of the respective stages can be adjusted independently, so that by adjusting these values, it becomes possible to subdivide and set the optimization of the pulse waveform.

Further, when the resonance time in the pulse waveform is extended due to the improvement of the drive sequence, the efficiency of power recovery can be improved by increasing the inductance of the resonance circuit. However, an increase in inductance leads to an increase in the number of turns in the inductor, resulting in an increase in its DC resistance. Even in such a case, since the present invention is a multi-stage resonant circuit, the inductors can be dispersed into a plurality of inductors, so that it is easy to eliminate disadvantages such as an increase in the resistance component due to an increase in the inductance.

[0067]

As described above in detail, according to the present invention,
It is possible to provide a display panel drive circuit that can easily optimize the pulse waveform and reduce power consumption when driving a load.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a conventional PDP display device.

FIG. 2 is a time chart showing application timings of various drive pulses in the apparatus of FIG.

FIG. 3 is a circuit diagram showing a configuration of a conventional display panel drive circuit (one-stage resonance circuit).

FIG. 4 is a circuit diagram showing a configuration of a conventional display panel drive circuit (double resonance circuit).

FIG. 5 is a block diagram showing a schematic configuration of a PDP display device including a display panel drive circuit according to the present invention.

FIG. 6 is a circuit diagram showing a first embodiment of a display panel drive circuit according to the present invention.

7 is a time chart showing the operation of the display panel drive circuit of FIG.

8 is a timing t0 of the display panel drive circuit of FIG.
It is a connection diagram showing a connection state immediately before.

9 is a timing t3 of the display panel drive circuit of FIG. 6;
It is a connection diagram which shows the connection state immediately after.

10 is a time chart showing an example of drive pulses output from the display panel drive circuit of FIG.

FIG. 11 is a circuit diagram showing a second embodiment of the display panel drive circuit according to the present invention.

12 is a time chart showing the operation of the display panel drive circuit of FIG.

13 is a time chart showing an example of drive pulses output from the display panel drive circuit of FIG. 11.

[Explanation of symbols]

10 ... PDP display panel 20, 21 ... Column electrode drive circuit 30, 31, 40, 41 ... Row electrode drive circuit 50, 51 ... Drive control circuit C0 ... Capacitance component C1 of discharge cell C _{(i, j)} in PDP electrode C2, C3 ... Capacitors D1-Di, U1-Di, D2-Di, U2-Di, B
1-Di, G2-Di ... Diodes D1-L, U1-L, D2-L, U2-L ... Inductors D1-SW, U1-SW, D2-SW, U2-SW, G
1-SW, B1-SW, G2-SW, B2-SW ...
switch

Continued front page    F-term (reference) 5C080 AA05 AA06 BB05 DD24 DD26                       JJ02 JJ03 JJ04

Claims (7)

[Claims] 1. A display having a row electrode group, a column electrode group arranged so as to intersect with the row electrode group, and a capacitive light emitting element disposed at each intersection of the row electrode group and the column electrode group. A display panel drive circuit that supplies a drive pulse to each of the capacitive light emitting elements via an output terminal when driving the panel, and a reference potential generation circuit that generates a plurality of reference potentials that are sequentially higher, and the output terminal. A resonance circuit that is connected to the capacitive light emitting element via a resonance circuit to form a resonance circuit, and generates a plurality of resonance voltages on the output terminal that rise and fall at different timings from each of the plurality of reference potentials. And each peak voltage of the resonance voltage is clamped to any of the plurality of reference potentials, and the rising edge gradually increases with the maximum value of the plurality of reference potentials as its amplitude and gradually. And a clamp circuit that generates a pulse having a falling edge that falls on the output terminal as the drive pulse. 2. The resonance circuit includes an inductor, a charge recovery capacitor, and a switch circuit that selectively forms a forward and reverse current path including a diode, and the switch circuit is switched to switch the switch circuit. 2. The display panel drive circuit according to claim 1, wherein a resonant circuit including the inductor and the capacitive light emitting element is formed when the potential of the output terminal rises and falls. 3. The clamp circuit includes a plurality of diodes and a switch circuit, and a potential of the output terminal is clamped to any one of the plurality of reference potentials by switching the switch circuit. The display panel drive circuit according to claim 1. 4. The display panel drive circuit according to claim 1, wherein the plurality of reference potentials have different polarities depending on the highest value and the lowest value. 5. A display having a row electrode group, a column electrode group arranged so as to intersect the row electrode group, and a capacitive light emitting element arranged at each intersection of the row electrode group and the column electrode group. A display panel drive circuit for supplying a drive pulse to each of the capacitive light emitting elements through an output terminal when driving a panel, comprising a series branch including a series connection of an inductor, a switch and a diode, an inductor and a switch. , And a first parallel circuit configured by parallel connection with a series branch configured by series connection of diodes having a polarity opposite to that of the diode; a second parallel circuit having the same configuration as the first parallel circuit; 1 switch, 1st diode, 2nd switch,
A series circuit including a second diode, a third switch, and a fourth switch connected in series, first, second, and third capacitors, an output terminal that outputs a pulse signal, and first and second And a DC power supply having a potential of 2, respectively, one end of the first switch is connected to the first potential, and the other end of the first switch is an anode of the first diode and the first diode. One end of the parallel circuit is connected to the output terminal, the other end of the first parallel circuit is connected to one end of the first capacitor, and the cathode of the first diode is connected to the second terminal. The other end of the second switch is connected to one end of a switch, and the other end of the second switch has an anode of the second diode, the other end of the first capacitor, one end of the third capacitor, and the second potential. Connected to the shadow of the second diode Is connected to one end of the third switch, the other end of the third switch is connected to one end of the fourth switch, one end of the second parallel circuit, and the output terminal, The other end of the second parallel circuit is connected to one end of the second capacitor, and the other end of the fourth switch is connected to the other end of the second capacitor and the other end of the third capacitor. A display pulse, which is connected to a ground potential, and is controlled to open and close based on a control signal generated by a predetermined sequence for each of the switches to generate the drive pulse on the output terminal. Panel drive circuit. 6. A display having a row electrode group, a column electrode group arranged so as to intersect with the row electrode group, and a capacitive light emitting element arranged at each intersection of the row electrode group and the column electrode group. A display panel drive circuit for supplying a drive pulse to each of the capacitive light emitting elements through an output terminal when driving a panel, comprising a series branch including a series connection of an inductor, a switch and a diode, an inductor and a switch. , And a first parallel circuit configured by parallel connection with a series branch configured by series connection of diodes having a polarity opposite to that of the diode; a second parallel circuit having the same configuration as the first parallel circuit; 1 switch, 1st diode, 2nd switch,
A series circuit including a series connection of a second diode, a third switch, and a fourth switch, first and second capacitors, an output terminal for outputting a pulse signal, and first and second polarities different from each other. A direct current power source having each of the potentials, one end of the first switch is connected to the first potential, and the other end of the first switch is the anode of the first diode and the first switch. Is connected to one end of the parallel circuit and the output terminal, the other end of the first parallel circuit is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the ground potential. The cathode of the first diode is connected to one end of the second switch, the other end of the second switch is connected to the anode of the second diode, and the ground potential, the second switch The cathode of the diode is Is connected to one end of a third switch, the other end of the third switch is connected to one end of the fourth switch, one end of the second parallel circuit, and the output terminal, The other end of the parallel circuit is connected to one end of the second capacitor, the other end of the second capacitor is connected to the ground potential, and the other end of the fourth switch is connected to the second potential. The display panel drive circuit is configured to generate the drive pulse on the output terminal by controlling the opening and closing of each of the switches based on a control signal generated by a predetermined sequence. 7. The display panel drive according to claim 5, wherein a drain terminal and a source terminal of an FET are used as the switch, and the control signal is supplied to each gate terminal of the FET. circuit.