JP2003140602A - Display panel driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display panel driver in which switching elements whose breakdown voltages are low can be used and in which power consumption for switching can be reduced. SOLUTION: This display panel driver is provided with a transition voltage generating circuit which changes the voltage of the DC voltage source of the driver and a resonance relay circuit which generates a pulse having a rising edge part which gradually builds up and a falling edge part which gradually decays on the basis of the transition voltage and outputs this pulse to a display panel as a driving pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for a display panel having a capacitive load such as an AC drive type plasma display panel (hereinafter referred to as PDP) or electroluminescence (hereinafter referred to as EL).

[0002]

2. Description of the Related Art Presently, as a wall-mounted TV, a display device using a self-luminous flat panel such as a PDP or EL has been commercialized. FIG. 1 is a diagram showing a schematic configuration of such a display device. In FIG. 1, a PDP 1 as a display panel
0 is a pair of X and Y for each line (1st line to nth line) of one screen.
Row electrodes Y _{1 to} Y _n and X ₁ forming a row electrode pair corresponding to
.About.X _n . Further, the PDP 10 has column electrodes Z _{1 to} Z that are orthogonal to the row electrode pairs and correspond to each column (first column to m-th column) of one screen with a dielectric layer and a discharge space (not shown) in between. _m is formed. In addition, a pair of row electrode pairs (X,
One discharge cell C _(i , _j) is formed at the intersection of Y) and one column electrode Z.

The row electrode driving circuit 30 first generates a positive voltage reset pulse RP _y as shown in FIG. 2 and applies it to each of the row electrodes Y _{1 to} Y _n at the same time. At the same time, the row electrode drive circuit 40 generates a negative voltage reset pulse RP _x and applies it to all the row electrodes X _{1 to} X _n at the same time. By simultaneously applying these reset pulses RP _x and RP _y , all discharge cells of the PDP 10 are excited by discharge to generate charged particles, and after this discharge is finished, a predetermined amount is uniformly applied to the dielectric layers of all the discharge cells. Wall charges are formed (reset stroke).

After the reset process is completed, the column electrode drive circuit 20 generates pixel data pulses DP _{1 to} DP _n according to the pixel data corresponding to each of the first row to the nth row of the screen, and these are generated. As shown in FIG. 2, the sequential column electrodes Z _{1 to} Z _m
Apply to. The row electrode drive circuit 30 generates a negative voltage scanning pulse SP in accordance with the application timing of each of the pixel data pulses DP _{1 to} DP _n , and sequentially outputs the scanning pulse SP as shown in FIG. 2 to the row electrodes Y _{1 to} Y _n. Apply to.

Among the discharge cells belonging to the row electrode to which the scan pulse SP is applied, discharge is generated in the discharge cells to which the positive voltage pixel data pulse is further applied at the same time, and most of the wall charges are lost. On the other hand, since discharge does not occur in the discharge cells to which the scan pulse SP is applied but the positive voltage pixel data pulse is not applied, the wall charges remain. At this time, the discharge cells in which the wall charges remain are the light emitting discharge cells, and the discharge cells in which the wall charges have disappeared are the non-light emitting discharge cells (addressing process).

When the address process is completed, the row electrode driving circuits 30 and 40 continuously apply a positive voltage sustaining pulse IP _Y to each of the row electrodes Y _{1 to} Y _n , as shown in FIG. , The positive voltage sustain pulse I is generated at a timing different from the application timing of the sustain pulse IP _Y.
P _X is continuously applied to each of the row electrodes X _{1 to} X _n . During the period in which the sustain pulses IP _X and IP _Y are alternately applied, the light emitting discharge cells in which the wall charge remains remain discharge and emit light and maintain the light emitting state (sustain discharge step).

The drive control circuit 50 shown in FIG. 1 generates various switching signals for generating various drive pulses as shown in FIG. 2 on the basis of the timing of the supplied video signal, and these are generated as described above. It is supplied to each of the column electrode drive circuit 20 and the row electrode drive circuits 30 and 40. That is,
Each of the column electrode drive circuit 20 and the row electrode drive circuits 30 and 40 generates various drive pulses shown in FIG. 2 according to the switching signal supplied from the drive control circuit 50.

FIG. 3 is a diagram showing a drive pulse generation circuit provided inside the row electrode drive circuit 30 for generating each of the reset pulse RP _Y and the sustain pulse IP _Y. In FIG. 3, the drive pulse generating circuit is provided with a capacitor C1 having one end grounded to the PDP ground potential Vs as the ground potential of the PDP 10.

The switching element S1 is in the cut-off state while the switching signal SW1 having the logic level "0" is supplied from the drive control circuit 50. On the other hand, when the logic level of the switching signal SW1 is "1", the connection state is established and the potential generated at the other end of the capacitor C1 is applied to the line 2 via the inductor L1 and the diode D1.
Apply on. As a result, the capacitor C1 starts discharging, and the potential generated by the discharging is applied to the line 2.

The switching element S2 is in the cutoff state while the switching signal SW2 having the logical level "0" is supplied from the drive control circuit 50, while the switching signal SW2 has the logical level "1". Is connected to the inductor L2.
And to the other end of the capacitor C1 via the diode D2. That is, the capacitor C1 is charged by the potential on the line 2.

The switching element S3 is in the cutoff state while the switching signal SW3 having the logical level "0" is supplied from the drive control circuit 50, while the switching signal SW3 has the logical level "1". Is connected to apply the positive-side terminal potential Vc of the DC power supply B1 to the line 2. The PDP ground potential Vs is applied to the negative terminal of the DC power supply B1.

The switching element S4 is in the cutoff state while the switching signal SW4 having the logic level "0" is supplied from the drive control circuit 50, while the switching signal SW4 has the logic level "1". Is connected and the PDP ground potential Vs is applied to the line 2. Line 2 is PDP1 with capacitive component C ₀
0 row electrode Y is connected. That is, inside the row electrode drive circuit 30, circuits as shown in FIG. 3 are provided for n systems corresponding to the respective row electrodes Y _{1 to} Y _n .

FIG. 4 shows a switching signal SW1 supplied from the drive control circuit 50 to the row electrode drive circuit 30 shown in FIG. 3 in order to generate the sustain pulse IP _y as shown in FIG. 2 on the line 2. 5 is a diagram showing the timing of each of SW4. FIG. As shown in FIG. 4, first, of the switching signals SW1 to SW4, the switching signal SW4
Since only the logic level is "1", the switching element S
4 is connected, and the PDP ground potential Vs is applied to the line 2. Therefore, during this period, the potential on the line 2 is the PDP ground potential Vs, that is, 0 [V].

Next, when the switching signal SW4 is switched to the logic level "0" and the switching signal SW1 is switched to the logic level "1", only the switching element S1 is brought into the connection state and the electric charge stored in the capacitor C1 is discharged. It Therefore, a current transiently flows in the inductor L1 in a form as shown in FIG. Such a current flows into the PDP 10 via the diode D1, the switching element S1, and the line 2 and the capacitance component C ₀ thereof is charged, so that the potential on the line 2 gradually rises as shown in FIG. go.

Next, when the switching signal SW1 is switched to the logic level "0" and the switching signal SW3 is switched to the logic level "1", only the switching element S3 is in the connection state, and the positive side terminal potential Vc of the DC power source B1 is on the line. 2 is applied on. Therefore, during this period, the potential on the line 2 is fixed to Vc as shown in FIG. Next, the switching signal SW2 is the logic level "1", and the switching signal S
When W3 switches to the logic level "0", respectively, only the switching element S2 enters the connection state, and a negative current transiently flows in the inductor L1 in the form as shown in FIG. That is, the capacitance component C _{0 of the} PDP 10 charged as described above is discharged, and the current thereof flows into the capacitor C1 through the line 2, the inductor L2, the diode D2 and the switching element S2 and is collected.
As a result, the potential on the line 2 gradually drops as shown in FIG.

By the above operation, the positive voltage sustain pulse IP _{y as} shown in FIG. 4 is applied to the line 2.

[0017]

By the way, as a voltage for driving a capacitive load such as a PDP, a relatively high voltage value of tens to hundreds of tens of volts is generally used. Therefore, in the configuration of the conventional drive circuit shown in FIG. 3, there is a problem that the resonance current flowing when charging and discharging the capacitive load also increases, resulting in a large power loss.

The breakdown voltage of each switching element included in the drive circuit for each of the row electrode and the column electrode is determined by the maximum value of the drive pulse voltage applied to each element. Therefore, in order to ensure a sufficient withstand voltage for the above-mentioned high voltage, it is necessary to use a high withstand voltage switching element, and the use of such a high withstand voltage switching element is also a cause of hindering cost reduction and downsizing of the drive circuit. Was there.

The present invention has been made to solve these problems, and it is an object of the present invention to provide a display panel driving device which can use a low breakdown voltage switching element and can reduce power consumption during switching. To aim.

[0020]

The present invention includes a row electrode group,
In driving a display panel having a column electrode group arranged to intersect the row electrode group and a capacitive light emitting element arranged at each intersection of the row electrode group and the column electrode group, the capacitive A display panel drive device for applying a drive pulse to each of the light emitting elements through its output terminal, wherein a direct current power supply for maintaining a predetermined voltage and rising and falling by charging and discharging electric charge from the direct current power supply. A transition voltage generating circuit for generating a transition voltage, and a pulse having a rising edge that gradually rises and a falling edge that gradually falls based on the transition voltage are output from the output terminal as the drive pulse. And a resonance relay circuit.

[0021]

FIG. 5 is a diagram showing a configuration of a display device including a display panel driving device according to the present invention. In FIG. 5, a PDP 10 as a display panel includes row electrodes Y _{1 to} Y _n and X ₁ that form a row electrode pair corresponding to each row (first row to nth row) of one screen with a pair of X and Y. .About.X _n . Further, the PDP 10 is orthogonal to the row electrode pair,
Further, column electrodes Z _{1 to} Z _m corresponding to each column (first column to m-th column) of one screen are formed with a dielectric layer and a discharge space (not shown) interposed therebetween. One discharge cell C _(i , _j) is formed at the intersection of one pair of row electrodes (X, Y) and one column electrode Z.

The row electrode drive circuit 31 generates a positive voltage reset pulse RP _y , a negative voltage scan pulse SP, and a sustain pulse IP _y , as shown in FIG. 2, which are shown in FIG. It is applied to each of the row electrodes Y _{1 to} Y _n at the timing. Row electrode drive circuit 41 generates a pulse IP _x each kept in the reset pulse RP _x of but such negative voltage, and a positive voltage shown in FIG. 2, these row electrodes X ₁ ~ at timing shown in FIG. 2 _Apply to each of X _n .

The column electrode drive circuit 21 is arranged in the first row to the n-th screen of the screen.
Pixel data pulses DP _{1 to} DP _n corresponding to the pixel data corresponding to each row are generated, and these are sequentially applied to the column electrodes Z _{1 to} Z _m as shown in FIG. Drive control circuit 51
Generates various switching signals for generating various drive pulses as shown in FIG. 2 based on the supplied video signal, and outputs these switching signals to the column electrode drive circuit 21 and the row electrode drive circuits 31 and 41, respectively. Supply to.

The inside of each of the row electrode drive circuit 31, the row electrode drive circuit 41, and the column electrode drive circuit 21 is as shown in FIG. 6, FIG. 8, or FIG. 10 described later. A pulse generation circuit is provided as a display panel driving device according to the present invention. FIG. 6 shows a first embodiment of the pulse generation circuit according to the present invention, and the configuration of the circuit will be described below.

In FIG. 6, the negative terminal of the DC power source B for generating a DC voltage (V / 2) is grounded to the PDP ground potential Vs which is the ground potential of the PDP 10. The positive terminal of the DC power supply B is connected to the line 1 via the diode D3. The line 1 is connected via the switching element S3 to the line 3 which is also an output terminal reaching each electrode (row electrode or column electrode) of the PDP 10, and the capacitance component C0 of the PDP 10 is connected to the line 3. In addition,
On the path from the line 3 to the capacitance component C0 of the PDP 10, an output driver circuit may be inserted as necessary.

On the other hand, the cathode of the diode D3 is connected to the line 2 via the capacitor C2, and the line 2 is further connected to the line 3 via the switching element S4. Also, line 2 is capacitor C
1, the diode parallel circuit 1, and the inductor L1 are connected to the line 3. Here, the diode parallel circuit 1 is a diode D1 and a switching element S.
It means a parallel circuit of a series branch of 5 and a series branch of the diode D2 and the switching element S6.

On the other hand, the positive terminal of the DC power source B is connected to the anode of the diode D3 and also to the line 2 via the switching element S1. The negative terminal of the DC power source B is also connected to the line 2 via the switching element S2, and at the same time the capacitor C is connected.
3, the diode parallel circuit 2, and the inductor L2 are connected to the line 2. Here, the diode parallel circuit 2 is a diode D4 and a switching element S.
It means a parallel circuit of a series branch of 7 and a series branch of the diode D5 and the switching element S8.

Incidentally, in the present embodiment, the circuit composed of the capacitor C1, the diode parallel circuit 1 and the inductor L1 forms a first resonance circuit, and is composed of the capacitor C3, the diode parallel circuit 2 and the inductor L2. The formed circuit forms a second resonance circuit. Next, the operation of the pulse generation circuit having such a configuration will be described with reference to FIG.
Will be described with reference to the circuit diagram of FIG. 7 and the operation time chart of the circuit shown in FIG.

The switching elements S1 to S8 included in the circuit are controlled in their on / off states by the logic levels of the switching signals SW1 to SW8 supplied from the drive control circuit 51 shown in FIG. It is a thing. However, in order to avoid a redundant description, the description about each switching signal supplied from the drive control circuit 51 is omitted in the following description, and only the change of the on / off state of the switching elements S1 to S8 is described. They should be listed in series.

Further, in the following description, the switching elements S1 to S8 will be simply referred to as S1 to S8, and similarly for other elements such as the capacitor C1 and the inductor L1, only the reference numerals thereof will be given like C1 and L1. It shall be stated. First, the time point t shown in the time chart of FIG.
Immediately before 0, S1, S3, S5, S7 and S8 are off, and S2, S4 and S6 are on. Therefore, the line 1 is connected to the positive terminal of the DC power supply B via the diode D3, and the potential thereof is (1/2) V. The line 2 and the line 3 are connected to the ground potential Vs via S2 and S4, and the potential is PDP.
Has a ground potential Vs, that is, 0 [V]. In addition,
It goes without saying that the C2 connected between the line 1 and the line 2 is charged to the potential of (1/2) V.

Further, in this embodiment, C1 and C3
Is set to (1 /
4) Assume that the battery is charged to the potential V. Figure 7
As shown in, at the time t0, S2 and S6 are turned off and S7 is
Is turned on, and C3 → S7 → D in the second resonance circuit.
A path of 4 → L2 is formed, and the charges charged in C3 flow into C0 via the lines 2 and 3. At this time, since the current flowing through L2 is the resonance current of the second resonance circuit, as shown in FIG.
To a positive peak value P1 and then gradually decreases.

On the other hand, the electric potential of the line 2 (line 3) gradually increases from the ground potential 0 [V] due to the accumulation of the charges in C0. Since the potential of line 2 is also the bias potential of C2, the potential of line 2 on the side of C2 gradually increases from (1/2) V which is the initial charging potential of C2 as the potential of line 2 rises. To rise. As shown in FIG.
The potential of line 2 (line 3) gradually rises from 0 [V] at time t0, and the resonance current flowing through L2 decreases and reaches 0.
At time t1, the potential becomes approximately (1/2) V. Incidentally, this potential is generated by the resonance phenomenon by the second resonance circuit, and has a value higher than the initial charging potential (1/4) V in C3.

At time t1 when the potential of line 1 is approximately V and the potentials of line 2 and line 3 are approximately (1/2) V, S1 is turned on and S4 is turned off, and line 2 is connected to the positive terminal side of DC power source B. Directly connected to, the potential of line 2 is DC power supply B
It is clamped to (1/2) V which is the electric potential of. Further, as a result, the bias potential of C2 becomes (1/2) V, so that the potential of the line 1 to which the other end of C2 is connected is the bias potential of (1/2) V of the conventional C2. (1/2) V is superposed and becomes the maximum potential V.

Further, with respect to C1, the bias potential (1/2) V of the line 2 is superimposed on the initial charging potential (1/4) V, and the potential of C1 in the first resonance circuit is (3 /
4) Increase to V. On the other hand, since S5 is turned on at time t1, C1 → S5 → D in the first resonance circuit
A path of 1 → L1 is formed. Then, the above-mentioned C1
Coupled with the potential increase in C, the capacitance component C0 of the PDP 10 from the first resonance circuit via line 3 is replaced with the electric charge stored in C1 instead of C3 of the second resonance circuit. Resonance current begins to flow.

In the circuit shown in FIG. 6, since the circuit constants of the first and second resonant circuits are set to be equal as one mode of the embodiment, as shown in FIG. 7, L1 flows at time points t1 to t2. The resonance current exhibits the same change as the resonance current flowing through L2 from time t0 to time t1. With the accumulation of charges in C0, the potential of line 3 starts to gradually increase from (1/2) V. At time t2 when the potential of the line 3 becomes approximately V, S3 is turned on, so that the potential of the line 3 is clamped to the potential of the line 1, that is, the maximum potential V.

Thereafter, at time t3, S3, S5, S
7 is turned off and S6 is turned on. by this,
In the first resonance circuit, instead of the previous path, L1 → D2 →
A new route, S6 → C1, has been created.
The electric charge stored in the capacitance component C0 of 10 is discharged to C1 through this path. Due to this discharge, a resonance current as shown in FIG. 7 flows through line 3 through line 3, and the potential of line 3 where the maximum potential V is unclamped by turning off S3 gradually decreases as shown in FIG.

The direction of the resonance current at this time is line 3
Since it is opposite to the potential rise time (time t1 to t2), L1
The peak P1 of the resonance current flowing through the node appears on the negative side as shown in FIG. 7 when the time points t1 to t2 are positive. Time point t4 when the potential of the line 3 becomes approximately (1/2) V
At, S1 is turned off and S4 and S8 are turned on. Therefore, this time, in the second resonance circuit, L2 → D5 → S8
The path of → C3 becomes effective, and as shown in FIG. 7, the resonance current starts to flow from C0 to the second resonance circuit via the line 3 and the line 2. It goes without saying that the direction of the resonance current in this case is opposite to the direction when the potential rises (time t0 to t1).

Along with this, the potentials of the lines 3 and 2 gradually decrease from (1/2) V, and at the same time, the potential V of the line 1 also gradually decreases. At time t5 when the potentials of the lines 2 and 3 are almost 0 [V], S2 is turned on and S8 is turned off, and the potentials of the lines 2 and 3 are clamped to the ground potential Vs of the PDP, that is, 0 [V]. . Also,
At time t5, the diode D3 becomes conductive, the electric charge of C2 is replenished by the DC power supply B, and the potential of the line 1 becomes (1/2).
It becomes V.

By the operation described above, the pulse waveform shown in FIG. 7 is generated on the line 3 of FIG. 6, and from the line 3 which is also the output terminal of the pulse circuit, the sustain pulse IP _x , the pixel data pulse DP, etc. It is supplied to the PDP 10 as each pulse. As is clear from the above description, the voltage range in which the switching elements S1 to S8 included in the circuit of this embodiment switch is [0
⇔ (1/2) V] or [(1/2) V ⇔ V]. Therefore, the withstand voltage of the switching elements in the circuit is all required to be (1/2) V, which is half the withstand voltage of the conventional circuit. As a result, the size and cost of the switching element used in the pulse generation circuit can be reduced.

Further, the maximum voltage of the DC power supply B to be provided as the pulse generation circuit is half the value of the conventional value (1 /
2) Needless to say, V is sufficient. Furthermore, if the power consumption in the conventional drive circuit shown in FIG. 3 is W0, then W0 = C0.V ² .f (1) can be expressed. Here, C0 is the capacitance component of the PDP 10, V is the voltage of the DC power supply, and f is the drive frequency.

On the other hand, in the drive circuit of the present embodiment shown in FIG. 6, the power supply voltage is 1/2 and the drive frequency is double that of the conventional circuit. Therefore, if the power consumption is W1, then W1 = C0 · (V / 2) ² · (2f) = (1/2) · C0 · V ² · f (2), which is almost half the power consumption W0 of the conventional circuit.

Next, the second pulse generation circuit according to the present invention will be described.
An example will be described. FIG. 8 shows the configuration of the circuit, and the configuration of the circuit according to the present embodiment will be described below with reference to the figure. In FIG. 8, DC voltage (V / 2)
The negative side terminal of the DC power supply B for generating the voltage is grounded to the PDP ground potential Vs which is the ground potential of the PDP 10, and the positive side terminal of the DC power supply B is connected to the line 1 via the diode D3.
It is connected to the.

The line 1 is connected to the line 3 which is an output terminal extending from this circuit to each electrode (row electrode or column electrode) of the PDP 10 via the switching element S3, and the line 3 is connected to the capacitance component C0 of the PDP 10. Will be done. Note that an output driver circuit may be inserted as necessary in the path from the line 3 to the capacitance component C0 of the PDP 10.

On the other hand, the cathode of the diode D3 is connected to the line 2 via the capacitor C2.
Is further connected to the above line 3 via the switching element S4.
It is connected to the. The line 2 is also connected to the line 3 via the capacitor C1, the diode parallel circuit, and the inductor L1. Here, the diode parallel circuit means a parallel circuit of a series branch of the diode D1 and the switching element S5 and a series branch of the diode D2 and the switching element S6.

A series branch of the switching element S1 and the switching element S2 is connected between the positive side terminal and the negative side terminal of the DC power source B, and the midpoint of this series branch is connected to the line 2 described above. There is. Next, the operation of the pulse generation circuit having such a configuration will be described with reference to the circuit diagram of FIG. 8 and the operation time chart of the circuit shown in FIG.

The on / off states of the switching elements S1 to S6 included in the same circuit are controlled by the logic levels of the switching signals SW1 to SW6 supplied from the drive control circuit 51 shown in FIG. However, in the following description, for simplification of the description, the description of the switching signal supplied from the drive control circuit 51 is omitted, and only the changes in the on / off states of the switching elements S1 to S6 are described in time series. I shall.

Further, in the following description, the switching elements S1 to S6 will be simply referred to as S1 to S6, and likewise for other elements such as the capacitor C1 and the inductor L1, only their reference numerals will be used, such as C1 and L1. It shall be stated. First, time t shown in the time chart of FIG.
Immediately before 0, S1, S3, S5 are off, S2,
S4 and S6 are on. Therefore, the line 1 is connected to the positive terminal of the DC power supply B via the diode D3, and the potential of the line 1 is (1/2) V.

Similarly, lines 2 and 3 are S2, S
It is connected to the ground potential Vs via 4, and the potential is the ground potential Vs of the PDP, that is, 0 [V].
By this, C2 connected between the line 1 and the line 2 is charged to the potential of (1/2) V. In addition, in the present embodiment, it is assumed that C1 is charged to a potential of (1/4) V by means (not shown) when the power of the apparatus is turned on.

When S4 is turned off and S5 is turned on at time t0, a path of C1 → S5 → D1 → L1 is formed, so that the charge charged in C1 is transferred to C via line 3.
It flows into 0. The current flowing through L1 is PD from the resonance circuit.
Since it is a resonance current to the capacitance component C0 of P10, it gradually increases from the on start time t0 of S5 as shown in FIG.
When the positive peak current value P1 is reached, it gradually decreases thereafter.

On the other hand, the potential of the line 3 gradually rises from 0 [V] at the time point t0, and becomes a potential of about (1/2) V at the time point t1 when the current flowing through the L1 decreases and becomes 0, The first resonance transition (change in potential on line 3 between times t0 and t1) ends. Incidentally, the potential due to the resonance transition is caused by the resonance phenomenon of the resonance circuit including L1, and has a value higher than the potential (1/4) V initially charged in C1.

At time t1 when the potential of line 3 becomes approximately (1/2) V, S1 is turned on, S2 is turned off, line 2 is switched from the ground potential to the positive terminal side of DC power supply B, and the potential of line 2 is changed. It is clamped to the potential (1/2) V of the DC power supply B. As a result, the potential of line 1 becomes C2
The bias potential (1/2) V of the line 2 is superimposed on the charging potential (1/2) V of 1 and rises to the maximum potential V.

Also in the resonance circuit, the conventional C
The bias potential (1/2) V of the line 2 is superimposed on the charging potential (1/4) V of 1 and the potential of C1 rises to (3/4) V. The discharge from C1 to C0 is restarted by the rise of the potential, the second resonance transition is generated following the first resonance transition, and the potential of the line 3 is continuously increased.

At time t2 when the potential of the line 3 becomes almost V, S3 is turned on and the line 3 is clamped to the maximum potential V which is the potential of the line 1. Then, at time t3, S3 and S5 are turned off and S6 is turned on. As a result, the clamp of the maximum potential V on the line 3 is released, and at the same time, the conventional resonance current path passing through S5 → D1 → L1 is also cut off.

On the other hand, by such switching operation,
A current path L1 → D2 → S6 → C1 is newly formed, and P
The electric charge charged in the capacitance component C0 of DP10 is discharged toward C1 this time. That is, the resonance current starts to flow again through the line 3, and the charge accumulated in C0 is recovered in C1. Incidentally, since the resonance current at this time is in the direction from C0 to C1,
Assuming that the direction of the current at the time points t0 to t2 is positive, the current direction of the resonance current can be expressed as the reverse direction, that is, the resonance current in the negative direction as shown in FIG. When the resonance current starts to flow, the electric charge stored in C0 gradually decreases, and the potential of the line 3 also gradually decreases accordingly.

At time t4 when the potential of the line 3 drops to about (1/2) V, S1 is turned off and S2 is turned on.
Turns on. As a result, the diode D3 becomes conductive and the electric charge of C2 is replenished by the DC power supply B, the potential of the line 1 becomes (1/2) V which is the potential of the DC power supply B, the potential of the line 2 becomes the ground potential Vs of the PDP, That is, it becomes 0 [V]. In addition, since the bias potential applied to C1 becomes 0 when the line 2 is grounded, the line 3
The potential of C1 with respect to is the initial charging potential of C1 (1/4) V
Fall to. The potential of line 3 is approximately (1/2) V
At the time t4 when the potential becomes, the third resonance transition (time t
The change in potential on line 3 between 3 and t4) ends.

As the potential of C1 is lowered, C0 to C
The discharge to 1 is restarted, the third resonance transition is followed by the fourth resonance transition, and the potential of the line 3 further decreases as shown in FIG. Then, at time t5 when the potential of the line 3 becomes almost 0 [V], S4 is turned on and the potential of the line 3 becomes the ground potential Vs of the PDP, that is, 0.
Clamped to [V].

By the operation described above, line 3 in FIG.
9, the pulse waveform shown in FIG. 9 is generated, and these pulses are supplied to the PDP 10 via the line 3 which is the output terminal of this circuit as respective pulses such as the sustain pulse IP _x and the pixel data pulse DP. . As is clear from the above description, the voltage range in which the switching elements S1 to S6 included in the circuit of this embodiment switch is:
[0 ⇔ (1/2) V] or [(1/2) V ⇔
V]. That is, the withstand voltage of the switching elements in the circuit is all required to be (1/2) V, which is half that of the conventional circuit. As a result, the size and cost of the switching element used in the pulse generation circuit can be reduced.

Also, the maximum voltage of the DC power supply B to be provided as the pulse generation circuit is half the value of the conventional value (1 /
2) Needless to say, V is sufficient. Further, if the power consumption in the conventional drive circuit shown in FIG. 3 is W0, it can be expressed as W0 = C0 · V ² · f (3) Here, C0 is the capacitance component of the PDP 10, V is the voltage of the DC power supply, and f is the drive frequency.

On the other hand, in the drive circuit of the present embodiment shown in FIG. 8, the power supply voltage is 1/2 and the drive frequency is twice that of the conventional circuit. Therefore, if the power consumption is W2, then W2 = C0 · (V / 2) ² · (2f) = (1/2) · C0 · V ² · f (4), which is almost half the power consumption W0 of the conventional circuit.

Further, in this embodiment, as compared with the above-described first embodiment, only one set of the resonance circuit is included in the pulse generation circuit, so that it is possible to reduce the cost by reducing the number of circuit elements. Next, a third embodiment of the pulse generating circuit as the driving device according to the present invention will be described.

First, the structure of the pulse generating circuit according to the third embodiment will be described with reference to the circuit diagram shown in FIG.
In FIG. 10, the negative terminal of the DC power supply B that generates a DC voltage (V / 3) is a PDP that is the ground potential of the PDP 10.
It is connected to the ground potential Vs, and the positive terminal of the DC power supply B is connected to the line 1 through the diodes D4 and D3.

The line 1 is connected to the line 3 which is an output terminal reaching each electrode (row electrode or column electrode) of the PDP 10 through the switching element S3.
The capacitance component C0 of P10 is connected. Note that an output driver circuit may be inserted as necessary in the path from the line 3 to the capacitance component C0 of the PDP 10.

The line 3 is connected to the line 2 through the inductor L1, the diode parallel circuit, and the capacitor C1.
It is connected to the. Here, the diode parallel circuit is
It means a parallel circuit of a series branch of the diode D1 and the switching element S5 and a series branch of the diode D2 and the switching element S6. In this embodiment, the inductor L1, the diode parallel circuit, and the capacitor C1 are used.
Further, the resonance circuit is configured by the capacitance component C0 of the PDP 10. The line 3 is further connected to the line 2 via the switching element S4.

On the other hand, one end of the capacitor C2 is connected to the cathode of the diode D3, and one end of the series branch of the switching elements S1 and S2 is connected to the anode of D3. Similarly, one end of the capacitor C3 is connected to the cathode of the diode D4, and one end of the series branch of the switching elements S7 and S8 is connected to the anode of D4. The other end of the capacitor C2 is connected to the line 2 and at the same time connected to the midpoint of the series branch of the switching elements S1 and S2, and the other end of the capacitor C3 is connected to the series of the switching elements S1 and S2. It is connected to the other end of the branch and to the midpoint of the series branch of the switching elements S7 and S8. The other end of the series branch of the switching elements S7 and S8 is connected to the negative terminal of the DC power supply B.

The pulse generating circuit according to this embodiment is not limited to the configuration shown in FIG. That is, in the figure, each diode connected in series to the line 1 is combined with a capacitor connected before and after it and a switching element series branch to form a one-stage transition voltage generation circuit. Then, the transition voltage generating circuit is cascaded in a plurality of stages between the DC power source B and the above-mentioned resonance circuit to form the pulse generating circuit according to the present embodiment.

That is, in the embodiment shown in FIG. 10, such a transition voltage generation circuit is inserted in two stages, and in the second embodiment shown in FIG. It may be considered that only the steps are inserted. continue,
FIG. 1 shows the operation of the pulse generation circuit according to this embodiment.
Description will be given with reference to the circuit diagram of No. 0 and the operation time chart of the circuit shown in FIG.

The on / off states of the switching elements S1 to S8 included in the same circuit are controlled by the logic levels of the switching signals SW1 to SW8 supplied from the drive control circuit 51 shown in FIG. Is. However, in the following description, in order to simplify the description, the description regarding the switching signal supplied from the drive control circuit 51 is omitted, and the switching elements S1 to S are simply included.
Only the changes in the on / off states of 8 shall be described in time series.

Further, in the following description, the switching elements S1 to S8 will be simply referred to as S1 to S8, and similarly, for other elements such as the capacitor C1 and the inductor L1, only their reference numerals will be used, such as C1 and L1. It shall be stated. First, immediately before time t0 shown in the time chart of FIG. 11, S1, S3, S5, and S7 are off, and S2, S4, S6, and S8 are on. Therefore, the line 1 is connected to the positive terminal of the DC power supply B via the diodes D3 and D4, and the potential of the line 1 is (1/3) V which is the potential of the DC power supply B.

Similarly, lines 2 and 3 are S4, S
Since it is connected to the ground potential Vs via S2 and S8, the potential is the ground potential Vs of the PDP, that is, 0 [V].
Has become. Note that this allows line 1 and line 2
Each of C2 and C3 connected between
3) Charged to V potential. Further, it is assumed that C1 included in the resonance circuit in the present embodiment is charged to a potential of (1/6) V by means (not shown) when the power of the device is turned on.

At time t0, S4 and S6 are off, S5
Is turned on, in the resonance circuit C1 → S5 → D1 →
Since the path L1 is formed, the charges charged in C1 flow into C0 via the line 3. At this time, the current flowing through L1 of the resonance circuit is equal to that of L1 of the resonance circuit and PDP1.
Since it is a resonance current with the capacitance component C0 of 0, as shown in FIG. 11, it gradually increases from the on start time t0 of S5 and reaches a positive peak current value P2, and then gradually decreases.

On the other hand, as shown in FIG. 11, the potential of the line 3 gradually rises from 0 [V] at the time point t0, and the resonance current flowing through the L1 decreases to almost zero at the time point t1 (1 /
3) The potential becomes V. By the way, since this value is caused by the resonance phenomenon of the resonance circuit including L1, C
The value is higher than the initial charging potential (1/6) V of 1. At time t1 when the potential of line 3 becomes approximately (1/3) V, S1 is turned on, S2 is turned off, and the line 2 side terminal of C2 is connected to the line 1 side terminal of C3 via S1.
As a result, the potential of line 1 becomes equal to the charging potential of C2 (1 /
3) The charging potential of C3 (1/3) V is superimposed on V and (2)
/ 3) Increase to V.

As for C1, the charging potential (1/6) V of C1 in the related art is changed to the bias potential (1
/ 3) V is superimposed, and the potential of C1 in the resonance circuit rises to (1/2) V. Due to the rise of the potential, the discharge from C1 to C0 is restarted and S5, D1, L
The resonance current through 1 again flows, that is, after the first resonance transition (time points t0 to t1), the second resonance transition (time points t1 to t2) occurs, and the potential of the line 3 continues to rise. Note that the resonance current in this case, as shown in FIG. 11, exhibits a change that gradually increases and then gradually decreases after reaching the peak value P2, as in the case of the previous times t0 to t1.

At the time t2 when the potential of the line 3 becomes approximately (2/3) V, S7 is turned on, S8 is turned off, and C3 is turned on.
The line 2 side terminal of is connected to the positive terminal side of the DC power supply B via S7. As a result, the potential of the line 1 is the charging potential of C2 (1/3) V and the charging potential of C3 (1/3) V.
And a bias potential (1/3) V from the DC power supply B
Are superposed, the voltage rises to the maximum potential V.

Similarly, for C1, the charging potential (1/3) V of C3 and the bias potential (1/3) V of the DC power source B are superimposed on the initial charging potential (1/6) V, and the resonance circuit The potential of C1 at rises to (5/6) V. As a result, the discharge from C1 to C0 is restarted and the resonance current flows through S5, D1 and L1 again, that is,
Following the second resonance transition (time points t1 to t2), the third resonance transition (time points t2 to t3) occurs and the line 3
Potential continues to rise. Note that the resonance current in this case is also the previous time points t0 to t1 and t1 as shown in FIG.
As in the case of up to t2, when the peak value P2 is gradually increased and then reaches the peak value P2, the change gradually decreases thereafter.

At time t3 when the potential of the line 3 becomes almost V, S3 is turned on and the line 3 is clamped to the maximum potential V which is the potential of the line 1. After that, at time t4, S3 and S5 are turned off and S6 is turned on. As a result, the clamp of the maximum potential V on the line 3 is released, and at the same time, the conventional resonance current path passing through S5 → D1 → L1 is also cut off.

On the other hand, by such switching operation,
A resonance current path of L1 → D2 → S6 → C1 is newly formed, and the electric charge charged in the capacitance component C0 of the PDP 10 is discharged toward C1 this time. That is, the resonance current starts to flow again through the line 3, and this time, the charge accumulated in C0 is collected in C1.
Incidentally, since the resonance current at this time is in the direction from C0 to C1, assuming that the direction of the current at the above-mentioned time points t0 to t3 is positive, the direction of the resonance current at this time is the opposite direction as shown in FIG. It can be expressed as a resonant current in the negative direction. When the resonance current starts to flow, the electric charge stored in C0 gradually decreases, and the potential of the line 3 also gradually decreases accordingly.

At time t5 when the potential of line 3 drops to about (2/3) V, S7 turns off and S8 this time.
Turns on. As a result, the potential of line 2 becomes only (1/3) V, which is the charging potential of C3, excluding the bias potential (1/3) V from DC power supply B. Further, the potential of C1 in the resonance circuit is also the potential of the line 2 (1 /
3) The initial charge potential of C1 (1/6) V is added to V to (1/2) V.

Therefore, the discharge from C0 to C1 is restarted, and the fifth resonance transition (time t5 to t6) follows the fourth resonance transition (time t4 to t5) to cause the potential of the line 3. Will continue to decline. At this time, the resonance current flowing through L1 is, as shown in FIG.
As at t5, the peak value P gradually increases in the negative direction.
When it reaches 2, the change gradually decreases thereafter.

After that, the potential of the line 3 is almost (1/3).
At time t6 when the voltage V drops to V, S1 turns off and S2 turns on. As a result, the potential of the line 2 becomes the ground potential Vs, that is, 0 [V], and the potential of C1 in the resonance circuit also drops to (1/6) V which is the initial charging potential. Therefore, the discharge from C0 to C1 is restarted, the sixth resonance transition (time points t6 to t7) follows the fifth resonance transition (time points t5 to t6), and the potential of the line 3 further decreases. To do. Note that the resonance current in this case is also the previous time points t4 to t5 and t5 as shown in FIG.
It goes without saying that the same change as at t6 is exhibited.

After that, at time t7 when the potential of the line 3 becomes almost 0 [V], S4 is turned on and the potential of the line 3 is clamped to the ground potential Vs of the PDP, that is, 0 [V]. Further, at time t7, the diodes D3 and D4 are turned on, and the DC power source B replenishes the charges of C2 and C3 so that the potential of the line 1 becomes (1/3) V. By the operation described above, the pulse waveform shown in FIG. 11 is generated on the line 3 of FIG. 10, and this pulse is the sustain pulse IP _x.
The respective pulses such as the pixel data pulse DP and the pixel data pulse DP are supplied to the PDP 10 through the line 3 which is an output terminal.

As is clear from the above description, the voltage range in which the switching elements S1 to S8 included in the circuit of the present embodiment switch is [0⇔ (1/3) V],
[(1/3) V ⇔ (2/3) V] or [(2 /
3) Limited to V ⇔ V]. In other words, the withstand voltage of the switching elements in the circuit is all required to be (1/3) V, which is 1/3 that of the conventional circuit. As a result, the size and cost of the switching element used in the pulse generation circuit can be reduced.

Further, the maximum voltage of the DC power supply B which should be provided as the pulse generation circuit is 1/3 of the conventional value (1/1).
3) Needless to say, V is sufficient. Furthermore, if the power consumption in the conventional drive circuit shown in FIG. 3 is W0, then W0 = C0.V ² .f (5) can be expressed. Here, C0 is the capacitance component of the PDP 10, V is the voltage of the DC power supply, and f is the drive frequency.

On the other hand, in the drive circuit of the present embodiment shown in FIG. 10, the power supply voltage is 1/3 and the drive frequency is 3 times that of the conventional circuit. Therefore, if the power consumption is W3, then W3 = C0 · (V / 3) ² · (3f) = (1/3) · C0 · V ² · f (6), which is almost one third of the power consumption W0 of the conventional circuit.

Further, as described above, the configuration of this embodiment is not limited to the circuit shown in FIG. That is,
By increasing the number of cascaded stages of so-called transition voltage generation circuits, which are inserted between the DC power supply and the resonance circuit, it is possible to use a switching element having a lower breakdown voltage, power consumption in the circuit, and the circuit. It is possible to further reduce the voltage value of the direct-current power supply that should be provided.

The first to third embodiments can be applied to both the sustain pulse generating circuit and the pixel data pulse generating circuit in the display device having the capacitive load. Although the first to third embodiments have been described with respect to the pulse generation circuit using the positive drive pulse, the present invention is not limited to this, and the pulse generation circuit using the negative drive pulse is used. May be adapted.

In the first to third embodiments, the inductors L1 and L2 in the resonance circuit are commonly used in the charge path and the discharge path for the capacitance component C0 of the PDP 10, but the present invention is not limited to this. Instead of this, an inductor may be independently provided in each of the charge path and the discharge path.

[0087]

As described above in detail, according to the display panel driving apparatus of the present invention, the power consumption of the apparatus can be reduced. Further, the voltage value of the DC power supply incorporated in the device can be lowered, and a low breakdown voltage switching element can be used.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a conventional PDP display device.

FIG. 2 is a diagram showing application timings of various drive pulses in the apparatus of FIG.

FIG. 3 is a diagram showing a drive pulse generation circuit provided in a row electrode drive circuit 30.

FIG. 4 is a diagram showing an operation time chart of the drive pulse generating circuit shown in FIG.

FIG. 5 is a diagram showing a schematic configuration of a PDP display device provided with the driving device of the present invention.

FIG. 6 is a diagram showing a first embodiment of a pulse generation circuit as a drive device according to the present invention.

7 is a diagram showing an operation time chart of the pulse generation circuit shown in FIG. 6;

FIG. 8 is a diagram showing a second embodiment of the pulse generation circuit as the driving device according to the present invention.

9 is a diagram showing an operation time chart of the pulse generation circuit shown in FIG. 8;

FIG. 10 is a diagram showing a third embodiment of the pulse generation circuit as the driving device according to the present invention.

11 is a diagram showing an operation time chart of the pulse generation circuit shown in FIG.

[Explanation of symbols]

10 ... PDP display panel 20, 21 ... Column electrode drive circuit 30, 31, 40, 41 ... Row electrode drive circuit 50, 51 ... Drive control circuit B, B1 ... DC power supply C0 ... Capacitance component of PDP electrode C1 to C3 ... Capacitor D1-D5 ... Diode L1, L2 ... Inductor S1 to S8 ... Switching element

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/66 G09G 3/28 JE F term (reference) 5C058 AA11 AA12 BA01 BA26 BB25 5C080 AA05 AA06 BB05 DD26 DD30 FF12 JJ02 JJ03 JJ04

Claims (8)

[Claims] 1. A row electrode group, a column electrode group arranged so as to intersect with the row electrode group, and a capacitive light emitting element arranged at each intersection of the row electrode group and the column electrode group. A display panel driving device that applies a driving pulse to each of the capacitive light emitting elements through its output terminal when driving the display panel, and a direct current power source for maintaining a predetermined voltage, and a charge from the direct current power source. A transition voltage generating circuit that generates a rising and falling transition voltage by charging and discharging a pulse, and a pulse having a rising edge that gradually rises and a falling edge that gradually falls based on the transition voltage. A resonance relay circuit that outputs the drive pulse from the output terminal, the display panel drive device. 2. The resonance relay circuit includes a first switch circuit that selectively forms a forward / reverse current path including a diode between the output terminal and a capacitor for power recovery via an inductor. The display panel drive device according to claim 1, further comprising: a second switch circuit that clamps the peak value of the drive pulse at the output terminal to a maximum level or a minimum level thereof. 3. The transition voltage generation circuit includes a capacitor charged by a predetermined voltage from the DC power supply, a diode connected to one end of the capacitor to prevent a reverse flow of charges charged in the capacitor, The display panel drive device according to claim 1, further comprising a switch circuit connected to the other end of the capacitor to switch a bias potential superimposed on the capacitor. 4. The display panel driving device according to claim 1, wherein the transition voltage generating circuits are cascaded in two or more stages between the DC power supply and the resonance relay circuit. 5. The display panel drive device according to claim 1, wherein the resonance relay circuit is provided between the DC power supply and the resonance relay circuit in place of the transition voltage generation circuit. 6. The display panel driving device according to claim 1, wherein the rising edge portion and the falling edge portion of the drive pulse include a plurality of resonance transition periods in which the resonance transition is stepwise performed. 7. The display panel drive device according to claim 1, wherein the transition voltage generation circuit generates a transition voltage that rises and falls between a maximum level of the drive pulse and an intermediate level thereof. . 8. When a bias voltage is not superimposed on a capacitor included in the transition voltage generation circuit, a high potential side terminal of the capacitor is at an intermediate level of the drive pulse and a low potential side terminal is at a minimum level of the drive pulse. When the bias voltage is superimposed on the capacitor, the high-potential side terminal of the capacitor is set to the maximum level of the drive pulse and the low-potential side terminal is set to the intermediate level of the drive pulse. The display panel drive device according to claim 3.