JP4542658B2 - Digital sine wave data generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention is used in, for example, a main device of a key telephone system, and for example, digital sine wave data generation for generating sine wave data for generating a tone signal used for providing an extension terminal or the like.In a vesselRelated.
[0002]
[Prior art]
The main part of the key telephone system having an exchange function has been digitized because of the recent demand for higher functionality and smaller size.
[0003]
By the way, in this type of apparatus, a function for generating a tone signal to be transmitted to an extension line or a local line is required, and a sine wave generator for generating a sine wave signal that is a source of the tone signal is provided.
[0004]
Further, it is necessary to detect various tone signals such as a busy tone and a DTMF signal that have arrived via an extension line or a local line, and a tone detection circuit that detects these tone signals is provided.
[0005]
Since these sine wave generators and tone detection circuits have been conventionally realized by analog circuits, there is a problem that the circuit scale is large and the integration is difficult. Also, since the other parts are digitized, a codec must be provided for interfacing with those parts, resulting in a further increase in circuit scale.
[0006]
According to the theory of traffic, these sine wave generators and tone detection circuits require eight for every 100 accommodated lines. However, the fact that all the plurality of tone detection circuits are composed of analog circuits It was a great hindrance to scale reduction.
[0007]
Although it is possible to perform sine wave generation and tone detection by digital processing using a DSP (Digital Signal Processor), it takes much time to create a program, and the circuit scale is still large, resulting in cost and power consumption. There is a problem that is too big.
[0008]
[Problems to be solved by the invention]
As described above, conventionally, the generation of the sine wave signal and the detection of the tone signal have been realized by an analog circuit, and thus there are problems such as an increase in size due to an increase in circuit scale, an increase in cost, and an increase in power consumption.
[0009]
  The present invention has been made in consideration of such circumstances, and an object of the present invention is to provide a digital sine capable of realizing downsizing, cost reduction, and low power consumption by integration with a simple digital circuit. Wave data generationVesselIt is to provide.
[0010]
[Problems to be solved by the invention]
In order to achieve the above object, a first invention is a digital sine wave that generates sine wave data by outputting a digital value indicating a level of a sine wave signal having a predetermined frequency as an output digital value at a predetermined cycle. In the data generator, a first reference value obtained by multiplying an output digital value in the previous cycle by a constant determined in accordance with the frequency of the sine wave signal, for example, a multiplication means including a latch circuit and a multiplier, and two cycles A second reference value generated by inverting the previous output digital value is generated, for example, generated by an inverting means including two latch circuits and a multiplier, and the first reference value generated by the multiplying means and the inverting means. Adding means such as an adder for generating an output digital value at the present time by adding the second reference value, and the first reference value to “0”, For example, reset means such as an initialization unit for resetting the second reference value to an initial value determined according to the frequency of the sine wave signal, and time elapsed after the reset by the reset means is performed. Time measuring means such as a timer, polarity change detecting means comprising, for example, a latch circuit and a comparison unit for detecting that the polarity of the output digital value generated by the adding means has changed from positive to negative, and the output digital value Detecting that the absolute value of the low level state is equal to or less than a predetermined reference value, for example, a level confirmation unit comprising a reference data register and a comparison unit, and an elapsed time measured by the time measuring unit exceeds a predetermined time When the polarity change is detected by the polarity change detection means, the low level state is detected by the level confirmation means. It has a reset control means such as a reset performed to example AND gate to the reset means if has been detected in.
[0011]
By taking such means, the first reference value obtained by multiplying the output digital value in the previous cycle by a constant determined according to the frequency of the desired sine wave signal and the output digital value in the previous two cycles are inverted. By adding the second reference value, a digital value indicating the level of the sine wave signal is obtained. Then, when the polarity of the output digital value changes from positive to negative in a state where the elapsed time since the last reset has exceeded a predetermined time, the absolute value of the output digital value is a predetermined reference value The first reference value and the second reference value are reset to “0” and an initial value determined according to the frequency of the sine wave signal, respectively, in response to the low level state that is described below. Accordingly, the sine wave data can be generated only by processing that can be realized by such digital processing, and the periodic reset is performed when the elapsed time from the previous reset exceeds a predetermined time. When the polarity of the output digital value changes from positive to negative, it is performed only when the absolute value of the output digital value is in a low level state that is equal to or less than a predetermined reference value. Strain is reduced.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, several embodiments of the present invention will be described with reference to the drawings.
[0025]
FIG. 1 is a block diagram showing a main configuration of a button telephone system including a sine wave data generator and a tone detection circuit according to the present invention.
[0026]
As shown in the figure, this key telephone system is configured by arbitrarily connecting a plurality (maximum i) of extension terminals 2 (2-1 to 2-i) to a main apparatus 1.
[0027]
The main device 1 further includes a time switch 11, a plurality (j) of local line interface circuits 12 (12-1 to 12-j), and a plurality (i) of extension interface circuits 13 (13-1 to 13-i). , CPU 14, ROM 15, RAM 16, data highway interface unit 17, sine wave data generator 18 and tone detection circuit 19, time switch 11, office line interface circuit 12, extension interface circuit 13, sine wave data generator 18. The tone detection circuit 19 is connected to each other via the PCM highway 20.
[0028]
The time switch 11, the office line interface circuit 12, the extension interface circuit 13, and the data highway interface unit 17 are connected to each other via the data highway 21. Further, the CPU 14, the ROM 15, the RAM 16 and the data highway interface unit 17 are connected to each other via a CPU local bus 22.
[0029]
The time switch 11 exchanges and connects the local line interface circuit 12 and the extension interface circuit 13 arbitrarily by exchanging the time slots on the PCM highway 20 based on the control of the CPU 14.
[0030]
A station line L (L-1 to L-j) such as a public line or a dedicated line is connected to the station line interface circuit 12 as necessary. The office line interface circuit 12 performs an office line interface operation for the connected office line L. The office line interface operation refers to conversion of an audio signal (analog) arriving via the office line L into a PCM signal, conversion of a PCM signal given via the time switch 11 into an audio signal (analog), and the office line L State monitoring, and transmission of various signals to the network connected via the office line L. The office line interface circuit 12 exchanges various control information related to the above-mentioned office line interface operation with the CPU 14 via the data highway 21, the data highway interface unit 17, and the CPU local bus 22.
[0031]
The extension terminal 2 is connected to the extension interface circuit 13 as necessary. The extension interface circuit 13 performs an extension interface operation related to the connected extension terminal. The extension interface operation includes the transmission of the PCM signal output from the extension terminal 2 to the PCM highway 20, the extraction of the PCM signal given via the time switch 11 from the PCM highway 20, the status monitoring of the extension terminal 2, and the extension terminal. 2 to send various signals. The extension interface circuit 13 exchanges various control information related to the extension interface operation with the CPU 14 via the data highway 21, the data highway interface unit 17, and the CPU local bus 22.
[0032]
The CPU 14 performs overall control of each of the time switch 11, the office line interface circuit 12, and the extension interface circuit 13 by performing processing based on the operation program stored in the ROM 15, and operates as a main device in the button telephone device. Is realized.
[0033]
The ROM 15 stores an operation program for the CPU 14 and other various data used permanently.
[0034]
The RAM 16 stores various information necessary for the CPU 14 to perform various processes.
[0035]
The data highway interface unit 17 exchanges data between the data highway 21 and the CPU local bus 22.
[0036]
(First embodiment)
This embodiment relates to the sine wave data generator 18 in FIG.
[0037]
FIG. 2 is a block diagram showing a specific configuration of the sine wave data generator 18 in the present embodiment.
[0038]
As shown in this figure, the sine wave data generator 18 in this embodiment includes an adder 31, latch circuits 32 and 33, multipliers 34 and 35, an output processing unit 36, a latch circuit 37, a comparison unit 38, and a reference data register. 39, a comparison unit 40, a timer 41, an AND gate 42, and an initialization unit 43.
[0039]
The adder 31 adds the output value of the multiplier 34 and the output value of the multiplier 35, and outputs the added value as the current value of the sine wave data. The output value of the adder 31 is composed of a data portion indicating the signal level and a code indicating the polarity.
[0040]
The output value of the adder 31 is input to the latch circuit 32. The latch circuit 32 captures and holds the output value of the adder 31 at a timing in accordance with a clock signal having the same frequency fs (for example, 8 KHz) in synchronization with the frame period on the PCM highway 20. The latch circuit 32 always outputs the held value.
[0041]
The output value of the latch circuit 32 is input to the latch circuit 33. The latch circuit 33 captures and holds the output value of the latch circuit 32 at a timing corresponding to the clock signal having the frequency fs. The latch circuit 33 always outputs the held value.
[0042]
Thus, the latch circuit 32 and the latch circuit 33 delay the output from the adder 31 by one frame period and output the output values one frame before and two frames before, respectively.
[0043]
The multiplier 34 multiplies the output value of the latch circuit 32 by a constant 2cos (w) determined according to the desired sine wave frequency and the frequency fs of the signal applied to the latch circuits 32 and 33, and obtains a value obtained as a result. This is given to the adder 31.
[0044]
The multiplier 35 inverts the data by multiplying the output value of the latch circuit 33 by “−1”, and gives the resulting value to the adder 31.
[0045]
The output value of the adder 31 is output by the output processing unit 36 to a time slot assigned on the PCM highway 20 as a current value in sine wave data indicating a sine wave signal having a predetermined frequency.
[0046]
The sign of the output value of the adder 31 is input to the latch circuit 37. The latch circuit 37 captures and holds the sign of the output value of the adder 31 at a timing according to the clock signal having the frequency fs. The latch circuit 37 outputs the retained code. That is, the latch circuit 37 delays the sign of the output from the adder 31 by one frame period, and outputs the sign of the output value from the adder 31 one frame before.
[0047]
The comparison unit 38 receives the sign output from the latch circuit 37 and the sign of the output value of the adder 31. The comparison unit 38 outputs the “H” level only when the sign output from the latch circuit 37 is “positive” and the sign of the output value of the adder 31 is “positive”.
[0048]
The reference data register 39 stores reference value data indicating a predetermined reference value ABS, and always outputs this reference value data.
[0049]
Reference value data output from the reference data register 39 and data out of the output values of the adder 31 are input to the comparison unit 40. The comparison unit 40 compares the values indicated by these two data, and outputs the “H” level only when the value indicated by the data among the output values of the adder 31 is equal to or less than the reference value.
[0050]
The timer 41 is cleared in response to the output of the AND gate 42 becoming “H” level. Then, the timer 41 counts the elapsed time from the time when it is cleared and, after completing a predetermined reset period, sets the output to “H” only until it is cleared next.
[0051]
The AND gate 42 is supplied with outputs of the comparator 38, the comparator 40, and the timer 41. The AND gate 42 outputs the “H” level only when the outputs of the comparison unit 38, the comparison unit 40, and the timer 41 are all “H”.
[0052]
An output from the AND gate 42 is given to the initialization unit 43. Then, in response to the output of the AND gate 42 becoming “H”, the initialization unit 43 initializes the holding values of the latch circuit 32 and the latch circuit 33 to a predetermined initial value.
[0053]
Next, the operation of the sine wave data generator 18 configured as described above will be described.
[0054]
First, the holding value of the latch circuit 32 is set to “0”, and the holding value of the latch circuit 33 is set to a constant Asin (w) determined according to a desired sine wave frequency and amplitude. Then, the output of the adder 31 is −Asin (w).
[0055]
Thereafter, the value held in the latch circuits 32 and 33 is updated at the timing of the clock signal, so that the output value of the adder 31 is also changed.
[0056]
At this time, the output value Y of the adder 31_(h)Represents the output value of the adder 31 one cycle before and two cycles before the clock signal, respectively._(h-1), Y_(h-2)If
Y_(h)= Y_(h-1)× 2cos (w) -Y_(h-2)
Thus, a level value when a sine wave signal having a desired sine wave frequency is sampled at a sampling frequency of fs appears as an output value Y.
[0057]
That is, the output of the adder 31 is shown in FIG. 3 having a frequency determined by the constant 2cos (w) and the constant Asin (w) with −Asin (w) as an initial value and an amplitude determined by the constant Asin (w). The sine wave data is obtained by sampling such a sine wave signal at a sampling frequency of fs. The sine wave data is sent to the PCM highway 20 by the output processing unit 36 at an appropriate timing. This sine wave data is used, for example, to generate an arbitrary tone signal by intermittent control of output by the time switch 11.
[0058]
The output value Y is a digital value, but the number of bits is finite. For this reason, the output of the multiplier 34 is a rounded result, and an error from the normal value occurs. Such errors are accumulated by repeated calculations.
[0059]
Therefore, the holding values of the latch circuits 32 and 33 are reset by a reset circuit including the latch circuit 37, the comparison unit 38, the reference data register 39, the comparison unit 40, the timer 41, the AND gate 42, and the initialization unit 43. I am going to do that.
[0060]
That is, first, the timer 41 counts a reset period appropriately set in consideration of the time during which the error of the output value Y is within an allowable range. H ”. Therefore, the output of the AND gate 42 does not become “H” until the timer 41 finishes counting the reset period.
[0061]
On the other hand, in the comparison unit 38, the current output value Y_(h)And the output value Y one frame before held in the latch circuit 37_(h-1)The sign of the output value Y is monitored to see if it changes from positive to negative. And the output value Y_(h-1)Is positive and the output value Y_(h)Since the sign of the output value Y has changed from positive to negative, the comparison unit 38 sets the output to “H”.
[0062]
Further, the comparison unit 40 compares the data excluding the sign of the output value Y, that is, the absolute value of the output value Y, with the reference value ABS indicated by the reference value data held in the reference data register 39. When the absolute value of the output value Y is equal to or less than the reference value ABS, the comparison unit 40 sets the output to “H”. The reference value ABS is set to an appropriate value smaller than -Asin (w) that is the initial value of the output value Y after reset.
[0063]
Thus, after the timer 41 finishes counting the reset period, all of the AND gates 42 only when the absolute value of the output value Y immediately after the sign of the output value Y changes from positive to negative is equal to or less than the reference value ABS. Becomes “H”, and the output of the AND gate 42 becomes “H”.
[0064]
Then, in response to the output of the AND gate 42 becoming “H”, the initialization unit 43 sets the holding value of the latch circuit 32 to “0” and the holding value of the latch circuit 33 to the constant Asin (w). initialize.
[0065]
Further, in response to the output of the AND gate 42 becoming “H”, the timer 41 is also reset, and timing of a new reset period is started.
[0066]
In this way, the output value Y is periodically reset to -Asin (w), and the error is suppressed within a certain range.
[0067]
In this embodiment, since the output value Y is reset immediately after the change from positive to negative, the output value Y changes from a positive level to -Asin (w), which is a steep change that cannot normally occur. Is prevented. As a result, the distortion of the waveform can be reduced and the noise generated in the tone generated using the sine wave data can be reduced.
[0068]
By the way, the output value Y immediately after the sign of the output value Y changes from positive to negative always falls within the range of 0 to −Asin (w). The closer this value is to −Asin (w), the more the output after resetting. The value Y becomes almost the same level, and for example, the waveform is distorted as shown in FIG.
[0069]
However, in this embodiment, reset execution is limited to the case where the absolute value of the output value Y is equal to or less than the reference value ABS set smaller than Asin (w). And the noise generated in the tone generated using this sine wave data can be reduced.
[0070]
Although it is possible to reduce the distortion of the waveform as the reference value ABS is decreased, the probability that the reset execution condition is satisfied may be reduced and the reset cycle may be too long. It is desirable to set the reference value ABS appropriately in consideration.
[0071]
(Second Embodiment)
This embodiment relates to the tone detection circuit 19 in FIG.
[0072]
FIG. 5 is a block diagram showing a specific configuration of the tone detection circuit 19 in the present embodiment.
[0073]
As shown in this figure, the tone detection circuit 19 in this embodiment includes a speed conversion unit 51, a compression / linear conversion unit 52, an arithmetic processing unit 53, an absolute value conversion unit 54, a peak detection unit 55, an addition unit 56, and a determination unit. 57, a register 58, a CPU interface 59, a counter 60, and a reset signal generator 61.
[0074]
The speed converter 51 is connected to the PCM highway 20. The speed conversion unit 51 extracts a predetermined one of a number of channels multiplexed on the PCM highway 20 with a 1 / fs frame period (for example, 125 μs), reduces the speed, To do. That is, the speed converter 51 reproduces a PCM signal whose value changes with a period of 1 / fs.
[0075]
The compression / linear conversion unit 52 is provided with the PCM signal output from the speed conversion unit 51. This PCM signal is compressed by a predetermined compression method. Therefore, the compression / linear conversion unit 52 expands the PCM signal output from the speed conversion unit 51 and returns it to a linear PCM signal.
[0076]
The arithmetic processing unit 53 performs a product-sum operation, which will be described in detail later, on each of a plurality of frequencies of interest using the PCM signal provided from the compression / linear conversion unit, and sends the result of the product-sum operation to the absolute value conversion unit 54. And give.
[0077]
The absolute value conversion unit 54 calculates the absolute value of the output value of the arithmetic processing unit 53.
[0078]
The peak detector 55 detects the peak value of the output value from the absolute value converter 54 for each frequency of interest.
[0079]
The adder 56 calculates the sum of peak values for each frequency of interest detected by the peak detector 55.
[0080]
The determination unit 57 determines the presence / absence of a tone signal to be detected based on the output value from the addition unit 56 when the counter 60 finishes counting the predetermined number of repetitions N. The determination unit 57 outputs determination data indicating the determination result.
[0081]
The register 58 stores and holds determination data output from the determination unit 57.
[0082]
The CPU interface 59 sends the determination data stored and held in the register 58 to the CPU local bus 22 at a predetermined timing.
[0083]
The counter 60 is given a clock signal having a frequency fs. The counter 60 cyclically counts the clock signal having the frequency fs repeatedly up to the number of times N. When the counter 60 finishes counting the predetermined number of repetitions N, it gives a count-up signal to each of the determination unit 57 and the reset signal generation unit 61.
[0084]
The reset signal generation unit 61 outputs a reset signal for resetting the operation states of the arithmetic processing unit 53 and the peak detection unit 55 to a predetermined initial state in response to the count up signal from the counter 60.
[0085]
FIG. 6 is a block diagram showing a specific configuration of the arithmetic processing unit 53 in FIG.
[0086]
As shown in this figure, the arithmetic processing unit 53 includes a subtracter 71, an adder 72, p flip-flops (FF) 73 (73-1, 73-2... 73-j) connected in series, and serial connection. P flip-flops (FF) 74 (74-1, 74-2... 74-j), a coefficient generator 75, and a multiplier 76.
[0087]
An output value of the compression / linear conversion unit 52 is input to the subtracter 71. Further, the output value of the flip-flop 74-j at the final stage is input to the subtracter 71. The subtractor 71 subtracts the output value of the flip-flop 74-j from the output value of the compression / linear conversion unit 52, and outputs the subtraction value.
[0088]
The output value of the subtracter 71 is input to the adder 72. Further, the output value of the multiplier 76 is input to the adder 72. The adder 72 adds these two values and outputs the added value. The output value of the adder 72 is output to the absolute value conversion unit 54 as a result of product-sum operation.
[0089]
The output value of the adder 72 is input to the uppermost flip-flop 73-1 of the flip-flops 73. Each flip-flop 73 is supplied with a clock signal having a frequency p times the frame frequency fs. Thus, the flip-flop 73 sequentially transfers the output value of the adder 72 at a period of 1 / p of the frame period. The held value of each flip-flop 73 is reset by a reset signal output from the reset signal generation unit 61.
[0090]
The output value of the last flip-flop 73-j of the flip-flops 73 is input to the uppermost flip-flop 74-1 of the flip-flops 74-1. Each flip-flop 74 is supplied with a clock signal having a frequency p times the frame frequency fs. Thus, the flip-flop 74 sequentially transfers the output value of the flip-flop 73-j at a period of 1 / p of the frame period. The held value of each flip-flop 74 is reset by a reset signal output from the reset signal generation unit 61.
[0091]
The coefficient generator 75 sequentially outputs a coefficient corresponding to each of the p target frequencies while changing the coefficient in synchronization with a clock signal having a frequency p times the frame frequency fs. That is, the coefficient generator 75 outputs a coefficient corresponding to a different frequency of interest in each period obtained by equally dividing one frame period by p.
[0092]
The multiplier 76 multiplies the output value of the flip-flop 73-j by the coefficient output from the coefficient generator 75.
[0093]
FIG. 7 is a block diagram showing a specific configuration of the peak detector 55 in FIG.
[0094]
As shown in this figure, the peak detector 55 includes a comparator 81, a selector 82, and p flip-flops (FF) 83 (83-1, 83-2,..., 83-j) connected in series. Become.
[0095]
The comparator 81 is given the output value of the absolute value converter 54 and the output value of the flip-flop 83-j at the final stage of the flip-flop 83. The comparator 81 compares these two values, and gives an “H” level to the selector 82 when the output value of the absolute value converter 54 is larger than the output value of the flip-flop 83-j.
[0096]
The selector 82 is given the output value of the absolute value converter 54 and the output value of the flip-flop 83-j. The selector 82 outputs the output value of the absolute value converter 54 when the "H" level is given from the comparator 81, and the flip-flop 83-j when the "L" level is given from the comparator 81. Select and output each output value.
[0097]
The output value of the selector 82 is input to the uppermost flip-flop 83-1 of the flip-flops 83. Each flip-flop 83 is supplied with a clock signal having a frequency p times the frame frequency fs. Thus, the flip-flop 83 sequentially transfers the output value of the selector 82 at a period of 1 / p of the frame period. Each output of each flip-flop 83 is individually supplied to the adder 56 as a peak value related to each frequency of interest. Note that the held value of each flip-flop 83 is reset by the reset signal output from the reset signal generation unit 61.
[0098]
Next, the operation of the tone detection circuit 19 configured as described above will be described.
[0099]
Here, the operation will be described as detecting a BT (Busy Tone) signal having any frequency within the frequency band of 305 Hz to 640 Hz.
[0100]
When such a BT signal is detected, the frequency of interest is set to four frequencies f1, f2, f3, and f4 within a band of 305 Hz to 640 Hz.
[0101]
Therefore, the number of flip-flops 73, 74, 81, 83 is four each. The frequency of the clock signal applied to these flip-flops 73, 74, 81, 83 is four times fs. If fs is 8 KHz, the frequency is 32 KHz.
[0102]
A speed conversion unit 51 extracts a channel as a detection target of the BT signal from a large number of channels multiplexed on transmission data of the PCM highway 20. Since the serial data of each channel is time-division multiplexed on the PCM highway 20, the data extracted by the speed conversion unit 51 exists in bursts. Therefore, the extracted data is subjected to parallel conversion and speed reduction by the speed conversion unit 51, and converted into continuous data in which data corresponding to one sampling value (but compressed here) exists for each frame period. Is done.
[0103]
The data converted into continuous data in this way is then decompressed by the compression / linear conversion unit 52 and returned to data directly indicating the signal level, and then provided to the arithmetic processing unit 53.
[0104]
Thus, in the arithmetic processing unit 53, one sampling value is given to the subtracter 71 over one frame period.
[0105]
On the other hand, a value to be output from the arithmetic processing unit 53 to the absolute value conversion unit 54, that is, an output value of the adder 72 that is a product-sum operation result in the arithmetic processing unit 53 (hereinafter referred to as a product-sum operation value) is The flip-flops 73-1 to 73-k and the flip-flops 74-1 to 74-k are sequentially transferred every quarter of the frame period.
[0106]
Thus, the output values of the flip-flop 73-k at the final stage (here, the fourth stage) of the flip-flop 73 and the flip-flop 74-k at the final stage (here, the fourth stage) of the flip-flop 74 are one frame. It becomes the output value of the adder 72 before the cycle and two frames before.
[0107]
Thus, the subtracter 71 subtracts the product-sum operation value two frames before from the sampling value given from the compression / linear conversion unit 52. However, while the sampling value given from the compression / linear converter 52 is the same value during one frame period, the output value of the flip-flop 74-k is obtained by dividing one frame period into four as will be described later. It becomes a different value in the period. Therefore, the output value of the subtracter 71 also becomes a different value in each period obtained by dividing one frame period into four equal parts.
[0108]
On the other hand, the multiplier 76 multiplies the product-sum operation value before one frame period by the coefficient output from the coefficient generator 75. Here, the coefficient generator 75 sequentially outputs coefficients corresponding to the four frequencies of interest in synchronization with a clock signal having a frequency four times the frame frequency. That is, one frame period is divided into four equal parts, and coefficients corresponding to each of the frequencies of interest f1, f2, f3, and f4 are sequentially output. Since the flip-flop 73 has a four-stage configuration and uses the same clock signal as that supplied to the coefficient generator 75 as a transfer clock, the output value of the flip-flop 73-k divides one frame period into four equal parts. It becomes a different value in each period.
[0109]
Thus, the multiplier 76 performs different multiplication in each period obtained by dividing one frame period into four, and the output value also differs in each period obtained by dividing one frame period into four equal parts.
[0110]
Since different values are given to the adder 72 from each of the subtractor 71 and the multiplier 76 in respective periods obtained by dividing one frame period into four equal parts, the adder 72 adds two values at each timing.
[0111]
In this way, as shown in FIG. 8, four product-sum operation processes are performed in a time division manner within one frame period. In each period obtained by dividing one frame period into four equal parts, the first period is a coefficient K corresponding to the first frequency of interest f1._(f1)Is used for the second period, the coefficient K corresponding to the second frequency of interest f2_(f2)Is used for the third period, the coefficient K corresponding to the third frequency of interest f3_(f3)And the period is a coefficient K corresponding to the fourth frequency of interest f4._(f4)The product-sum operation process is performed using the values related to. That is, the product-sum calculation process for each frequency of interest is performed in a time division manner. In FIG. 8, the notations “_f1”, “_f2”, “_f3”, and “_f4” attached to the end of each value indicate whether the value relates to the frequency of interest f1, f2, f3, or f4. Show.
[0112]
And the output value V by the product-sum operation for each frequency of interest_(h)Represents the sampling value given from the compression / linear conversion unit 52 as X_(h), The output value of flip-flop 73-k is V_(h-1), The output value of flip-flop 74-k is V_(h-2)And the coefficient generated by the coefficient generator 75 is denoted as K, respectively.
V_(h)= X_(h)-V_(h-2)+ V_(h-1)× K_(f)
It becomes.
[0113]
K_(f)Is determined according to the frequency of interest,
K_(f)= 2cos (2 × π × k_(f)/ N_(f))
It becomes.
[0114]
Here, k is a constant determined according to the frequency of interest. N_(f)Is the number of repetitions of product-sum operation (number of sample points) determined according to the frequency of interest. These constant k and number of repetitions N_(f)Indicates the frequency of interest as ftone and the repetition frequency of the product-sum operation as fs.
ftone / fs ≒ k_(f)/ N_(f)
Are set so that each satisfies an integer.
[0115]
The output value V thus obtained is repeatedly increased and decreased as the product-sum operation is repeated. However, the peak value of the output value V increases only when the component of the frequency of interest exists in the input signal. Go.
[0116]
FIG. 9 is a diagram illustrating a change in the output value V when the product-sum operation is performed with the frequency fx as the frequency of interest and the input signal frequency is changed to fx, fy, and fz.
[0117]
As is clear from this figure, when the same frequency fx as the frequency of interest is input, the peak value of the output value V increases, but when other frequencies fy and fz are input, the peak value of the output value V is obtained. Does not increase.
[0118]
Therefore, it is possible to determine whether or not the frequency of interest exists in the input signal based on the peak value of the output value V after repeating the product-sum operation over a certain period.
[0119]
However, the peak value of the output value V can occur both positively and negatively as can be seen from FIG. Therefore, the output value V is converted into an absolute value by the absolute value conversion unit 54, and the peak value is detected by the peak detection unit 55.
[0120]
The peak detector 55 detects this peak value as follows.
[0121]
That is, the output value of the absolute value converter 54 is given to the comparator 81 and compared with the output value of the flip-flop 83-k.
[0122]
Here, in the flip-flops 83-1 to 83-k, the output value of the selector 82 is sequentially transferred every 1/4 period of the frame period, so that the output value of the flip-flop 83-k at the final stage is one frame. This is the output value of the selector 82 before the cycle.
[0123]
Thus, the output value of the absolute value converter 54 is compared with the value selected by the selector 82 in the previous frame period by the comparator 81. As a result of the comparison by the comparator 81, the selector 82 selects the larger value of the output value of the absolute value converter 54 and the output value of the flip-flop 83-k. Here, the value selected by the selector 82 is input to the flip-flop 83-1, and sequentially transferred through the flip-flops 83-1 to 83-k.
[0124]
In this way, the flip-flops 83-1 to 83-k hold the peak value of the output value of the absolute value converter 54 for each frequency of interest. Therefore, the output values of the flip-flops 83-1 to 83-k are individually given to the adding unit 56 as the peak value of the product-sum operation result for each frequency of interest.
[0125]
The p peak values given from the peak detection unit 55 in this way are added to each other by the addition unit 56, and the total value of the peak values obtained thereby is given to the determination unit 57.
[0126]
Now, while the product-sum operation is repeatedly performed by the arithmetic processing unit 53 as described above, the counter 60 counts the number of times the product-sum operation is executed, so that the frequency is the frame frequency fs. The signal is counted. When the counter 60 finishes counting the predetermined number of repetitions N, a count-up signal is given from the counter 60 to the determination unit 57 and the reset signal generation unit 61.
[0127]
When the count-up signal is given from the counter 60 in this way, the determination unit 57 makes a detection target by confirming whether or not the output value of the addition unit 56 at that time exceeds a predetermined threshold value. It is determined whether or not the BT signal is included in the input signal.
[0128]
That is, if the BT signal has arrived, all of the frequencies of interest are included, so the peak value of the product-sum calculation value for each of the frequencies of interest is a large value. That is, this is equivalent to the detection of the frequency spectrum as shown in FIG.
[0129]
Now, the result of the product-sum operation for each frequency of interest is a frequency spectrum having a certain bandwidth as shown in FIG. The bandwidth is determined by the number of product-sum operations repeated.
[0130]
Therefore, the number of repetitions of the product-sum operation for each frequency of interest is set so that the frequency spectra obtained for the adjacent frequencies of interest overlap appropriately as shown in FIG.
[0131]
By doing so, the sum of the product sum calculation values for each frequency of interest is added by the adder 56, whereby the sum of the spectrum of each frequency of interest as shown in FIG. 10 is obtained. The signal of each frequency is detected with the sensitivity distribution as shown.
[0132]
That is, not only when a signal having the same frequency as the target frequency has arrived, but also when a signal having an intermediate frequency between the target frequencies has arrived, the output value of the adder 56 becomes a sufficiently large value. Thus, the same result as that obtained by passing the band-pass filter having the frequency characteristics as shown in FIG. 11 can be obtained.
[0133]
Therefore, if the output value of the adder 56 is equal to or greater than a certain value, it can be determined that a signal in the band as shown in FIG. 11, that is, a BT signal has arrived.
[0134]
Then, the determination data indicating the determination result in the determination unit 57 is stored and held in the register 58, and then sent to the CPU local bus 22 at a predetermined timing by the CPU interface 59 and notified to the CPU 14.
[0135]
In parallel with the determination processing by the determination unit 57, a reset signal is supplied from the reset signal generation unit 61 to the arithmetic processing unit 53 and the peak detection unit 55 in response to the count-up signal being supplied from the counter 60. As a result, the flip-flops 73-1 to 73-k and 74-1 to 74-k of the arithmetic processing unit 53 and the flip-flops 83-1 to 83-k of the peak detecting unit 55 are reset, and a new product-sum operation process is performed. And the peak value detection of the product-sum operation value is started.
[0136]
By the way, the number of times the product-sum operation is repeated is different for each frequency of interest, and theoretically, the determination unit 57 uses the value obtained by the product-sum operation of the number of repetitions corresponding to each frequency of interest. become.
[0137]
However, the number of repetitions N corresponding to each frequency of interest_(f)Is set to a value closest to the reference number, and the number of repetitions N counted by the counter 60 is set to the reference number. As a result, the determination unit 57 can make a determination based on the peak value of the product-sum operation value for each frequency of interest at the time when the counter 60 has counted the number of repetitions N as described above.
[0138]
This is because, as can be seen from FIG. 9, even if the number of iterations changes slightly, the peak value of the product-sum operation result does not change greatly._(f)This is because even the peak value at the time of the number of repetitions N with a small difference from the above has little influence on the determination accuracy of the presence or absence of the BT signal.
[0139]
The number of repetitions N is appropriately set so that N product-sum operations can be completed at least once during the duration of the detection target tone (here, the BT signal).
[0140]
As described above, according to the present embodiment, the value obtained by subtracting the product-sum operation value two frames before from the level of the input signal in each frame and the product-sum operation value one frame before are used as the frequency of interest. The sum-of-products operation process performed by adding the values obtained by multiplying the corresponding coefficients is performed over a predetermined number of iterations, and the peak value is detected, and the frequency of interest is determined using the Goertzel algorithm. A plurality of frequency spectra as the center frequency are calculated. The bandwidth of the frequency spectrum is determined by the number of repetitions of the product-sum operation and the coefficient used for the product-sum operation. Therefore, one frequency band can be synthesized by combining each frequency spectrum after setting adjacent frequency spectra. A pass filter is configured to detect the BT signal.
[0141]
Therefore, the BT signal can be detected only by processing that can be easily performed by digital processing by a basic digital circuit, and downsizing can be achieved by integration.
[0142]
Further, in this embodiment, since each frequency spectrum is synthesized by adding the peak values of the respective frequencies of interest, it is possible to obtain sufficient sensitivity with respect to intermediate frequencies between the frequencies of interest. The interval of the frequency of interest can be increased compared to the case of the third embodiment described later. As a result, the number of frequencies of interest required to cover a certain frequency band can be reduced, and the number of product-sum calculation processes can be reduced, thereby simplifying the configuration and reducing the processing speed. Thus, it can be easily realized.
[0143]
Further, according to the present embodiment, one frame period is equally divided into p, and the product-sum operation processing for each of the p number of frequencies of interest is processed in a time-sharing manner. The adder 72 and multiplier 76 can be shared by each frequency of interest, and the circuit scale can be further reduced as compared with the case where they are provided individually.
[0144]
Further, according to the present embodiment, the number of repetitions N of product-sum operations for each frequency of interest is N._(f)Is set to a value closest to a certain reference number, and the product-sum operation value used for determining the presence or absence of the BT signal is set to a value obtained by the product-sum operation of the reference number. It is sufficient to simply add the latest values of the peak values regarding the number of individual repetitions N_(f)Therefore, the configuration can be further simplified.
[0145]
(Third embodiment)
This embodiment relates to the tone detection circuit 19 in FIG.
[0146]
FIG. 12 is a block diagram showing a specific configuration of the tone detection circuit 19 in the present embodiment. 1 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0147]
As shown in this figure, the tone detection circuit 19 in this embodiment includes a speed conversion unit 51, a compression / linear conversion unit 52, an arithmetic processing unit 53, an absolute value conversion unit 54, a peak detection unit 55, a register 58, and a CPU interface 59. , A counter 60, a reset signal generation unit 61, a threshold value comparison unit 91, and a determination unit 92.
[0148]
That is, in the present embodiment, the tone detection circuit 19 includes a threshold value comparison unit 91 and a determination unit 92 in place of the addition unit 56 and the determination unit 57 in the second embodiment.
[0149]
The threshold comparison unit 91 compares the peak value of each frequency of interest detected by the peak detection unit 55 with a predetermined threshold value, and notifies the determination unit 92 of the comparison result.
[0150]
The determination unit 92 determines the presence / absence of a tone signal to be detected based on the notification content from the threshold value comparison unit 91 when the counter 60 finishes counting the predetermined number of repetitions N. The determination unit 92 outputs determination data indicating the determination result.
[0151]
FIG. 13 is a block diagram showing a specific configuration of the threshold comparison unit 91.
[0152]
As shown in this figure, the threshold value comparison unit 91 is composed of p number of comparison circuits 101 (101-1, 101-2... 101-k) and a threshold value register 102.
[0153]
Each comparison circuit 101 receives a peak value of each frequency of interest detected by the peak detector 55. Each comparison circuit 101 is commonly given a threshold value stored and held in the threshold value register 102. Each comparison circuit 101 compares the peak value with a threshold value and notifies the determination unit 92 whether or not the peak value is larger than the threshold value.
[0154]
The threshold register 102 stores and holds a predetermined threshold value set in advance, and always outputs this threshold value.
[0155]
Thus, the tone detection circuit 19 of this embodiment does not add the peak values for each frequency of interest, but compares them individually with the threshold value. The determination unit 92 determines that the BT signal has arrived if the threshold value comparison unit 91 determines that any one of the peak values related to each frequency of interest exceeds the threshold value.
[0156]
In the case of the second embodiment described above, since the spectrum of each frequency of interest is synthesized, it is likely to be affected by harmonics and the detection accuracy may be lowered.
[0157]
However, according to the present embodiment, since the spectrum of each frequency of interest is individually compared with the threshold without being synthesized, it is possible to accurately detect the BT signal without being affected by the harmonics. .
[0158]
However, in the case of the present embodiment, since the sensitivity is low for the intermediate frequency between the frequencies of interest, in order to suppress such a decrease in sensitivity for the intermediate frequency, for example, as shown in FIG. It is necessary to increase the density of the frequency of interest compared to the case of the second embodiment described above. Accordingly, the number of frequencies of interest necessary to cover a certain frequency band increases, and the number of multiplexed product-sum calculation processes increases, which requires an increase in processing speed.
[0159]
(Fourth embodiment)
This embodiment relates to the tone detection circuit 19 in FIG.
[0160]
FIG. 15 is a block diagram showing a specific configuration of the tone detection circuit 19 in the present embodiment. The same parts as those in FIGS. 1, 5, and 12 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0161]
As shown in this figure, the tone detection circuit 19 in this embodiment includes a speed conversion unit 51, a compression / linear conversion unit 52, an arithmetic processing unit 53, an absolute value conversion unit 54, a peak detection unit 55, a register 58, a counter 60, A reset signal generation unit 61, a threshold comparison unit 91, a determination unit 92, a threshold comparison unit 111, a matrix unit 112, a register 113, and a CPU interface 114 are provided.
[0162]
That is, in the present embodiment, the tone detection circuit 19 includes a threshold value comparison unit 111, a matrix unit 112, and a register 113 in addition to the configuration of the tone detection circuit 19 in the third embodiment, and the CPU in the third embodiment. Instead of the interface 59, a CPU interface 114 is provided.
[0163]
In the present embodiment, in addition to a plurality of frequencies of interest set in the frequency band of 305 Hz to 640 Hz for BT signal detection, frequencies that can be elements of a DTMF (Dual Tone Multi Frequency) signal (for example, 697 Hz, 770 Hz, 852 Hz). , 941 Hz, 1209 Hz, 1336 Hz, 1477 Hz, and 1633 Hz). Accordingly, if the target frequency for detecting the BT signal is 8 frequencies as shown in the third embodiment, the number p of the target frequencies is “16”.
[0164]
Accordingly, the peak detector 55 has 16 outputs. Of the 16 outputs, 8 related to the target frequency for detecting the BT signal are stored in the threshold value comparison unit 91, and the remaining 8 outputs, that is, 8 related to the target frequency for detecting the DTMF signal are compared with the threshold value. Each is input to the unit 111.
[0165]
The threshold comparison unit 111 has the same configuration as the threshold comparison unit 91. Then, the threshold value comparing unit 111 compares each output value from the peak detecting unit 55 related to the target frequency for detecting the DTMF signal with a predetermined threshold value, and each output value from the peak detecting unit 55 is greater than the threshold value. The matrix unit 112 is notified of whether it is larger.
[0166]
The matrix unit 112 determines whether or not a DTMF signal has arrived and the type of the DTMF signal that has arrived, based on the notification content from the threshold value comparison unit 91 when the counter 60 has finished counting the number of times of repetition N. Identify. The matrix unit 112 outputs determination data indicating the determination result.
[0167]
The register 113 stores and holds determination data output from the matrix unit 112.
[0168]
The CPU interface 114 sends the determination data stored and held in the register 58 and the register 113 to the CPU local bus 22 at a predetermined timing.
[0169]
Thus, in the tone detection circuit 19, the BT signal is detected in exactly the same manner as in the third embodiment. In parallel with the detection of the BT signal, a frequency spectrum for each element frequency of the DTMF signal is obtained as shown in FIG. The DTMF signal is composed of a combination of two element frequencies, and there is no need to detect an intermediate frequency. Therefore, if the bandwidth of the frequency spectrum to be obtained is sufficient to cover the frequency tolerance. Good.
[0170]
Then, each of the output values related to the target frequency for detecting the DTMF signal from the peak detecting unit 55 is compared with the threshold value by the threshold value comparing unit 111, and as a result, any two output values are equal to or more than the threshold value. If this is the case, it is known that the DTMF signal has arrived, and the DTMF that has arrived is determined by determining which element frequency corresponds to the two output values that are equal to or greater than the threshold value. Since the signal type can be determined, such a determination is performed by the matrix unit 112.
[0171]
As described above, according to the present embodiment, it is possible to detect both the BT signal and the DTMF signal by the tone detection circuit 19 with only a slight configuration.
[0172]
The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the digital sine wave data generator and the tone detection circuit of the present invention are illustrated and described as being used in a button telephone system. It can also be realized as applied.
[0173]
In the first embodiment, only sine wave data of one frequency is generated, but sine wave data of a plurality of frequencies may be generated in a time division manner. That is, the latch circuit 32 and the latch circuit 33 have a multi-stage configuration similar to the flip-flop 73 and the flip-flop 74 shown in FIG. What is necessary is just to make it generate | occur | produce in a time division using a thing. The initialization unit 43 sets different values for the constant Asin (w) set in each of the plurality of stages of latch circuits 33 in accordance with each sine wave frequency and amplitude.
[0174]
In the second to fourth embodiments, the number of repetitions N of product-sum operations is N._(f)The tone signal is detected by using the peak value of the product-sum operation value by the same number of product-sum operations even though the frequency varies depending on the frequency of interest._(f)The peak value of the product-sum operation value by the product-sum operation is obtained and stored in sequence, and after waiting for the product-sum operation values for all the frequencies of interest to be obtained, the tone signal is detected using them. You may make it do. If this is done, the number of repetitions of product-sum operations N_(f)The degree of freedom of setting is increased, and it is possible to take measures such as setting it so as to further improve the detection accuracy.
[0175]
In the second to fourth embodiments, the arithmetic processing unit 53, the absolute value conversion unit 54, and the peak detection unit 55 perform processing on each target frequency in a time-sharing manner, but each processing system is provided with a separate processing system. It is also possible to perform processing in parallel. In this case, the configuration is slightly complicated as compared with the second to fourth embodiments, but the processing speed is low.
[0176]
In the second to fourth embodiments, only the tone detection for one channel is illustrated, but tone detection for a plurality of channels may be performed in a time-sharing manner. In this case, the variable p may be the product of the number of frequencies of interest and the number of channels to be time-division processed. In this case, the addition unit 56, the determination unit 57, the threshold value comparison unit 91, the determination unit 92, the threshold value comparison unit 111, and the matrix unit 112 also perform time division processing. If the accommodated lines are 100 lines and a tone detection circuit for 8 channels is required, it is only necessary to provide a single tone detection circuit 19 by time-sharing the 8 channels. This greatly contributes to the reduction of scale, the associated cost reduction and miniaturization promotion, and reduction of power consumption.
[0177]
In the second to fourth embodiments, the arithmetic processing unit 53 and the peak detection unit 55 use flip-flops 73, 74, and 83 connected in multiple stages in order to hold values related to the respective frequencies of interest. However, a RAM, a FIFO memory or the like may be used. If the number of frequencies of interest p and the number of channels to be multiplexed are large and the number of flip-flop stages becomes very large, the circuit scale may be reduced by using these memories.
[0178]
In the second to fourth embodiments, the variable n is set to “1”, the multiplier 76 multiplies the product-sum operation value one frame period before by the coefficient, and the subtractor 71 multiplies the product two frames period before. Although the sum operation value is subtracted from the input value, the variable n may be arbitrary. For example, “2” is set to the multiplier 76 and the product-sum operation value two frames before is supplied to the multiplier 76. You may make it give the product-sum operation value 4 periods before, respectively. In such a case, for example, it is possible to take measures such as performing processing related to different frequencies of interest in odd-numbered frames and even-numbered frames.
[0179]
In the fourth embodiment, the same configuration as that of the third embodiment is used for the detection of the BT signal. However, the same configuration as that of the second embodiment can also be used. .
[0180]
In addition, various modifications can be made without departing from the scope of the present invention.
[0181]
【The invention's effect】
According to the first invention, in the digital sine wave data generator for generating sine wave data by outputting a digital value indicating the level of a sine wave signal having a predetermined frequency as an output digital value at predetermined intervals, Multiplying means for generating a first reference value obtained by multiplying an output digital value before a cycle by a constant determined according to the frequency of the sine wave signal, and a second reference value by inverting the output digital value two cycles before. Inversion means, addition means for adding the first reference value generated by the multiplication means and the second reference value generated by the inversion means to generate an output digital value at the present time, and the first reference A reset means for resetting the value to “0” and the second reference value to an initial value determined in accordance with the frequency of the sine wave signal; Timing means for measuring the elapsed time since the reset by the resetting means, polarity change detecting means for detecting that the polarity of the output digital value generated by the adding means has changed from positive to negative, and the output digital Level confirmation means for detecting that the absolute value of the value is a low level state that is equal to or less than a predetermined reference value, and the polarity change detection means in a state in which the elapsed time counted by the time measuring means exceeds a predetermined time And a reset control means for resetting the reset means if the low-level state is detected by the level confirmation means when the polarity change is detected by the digital confirmation processing. The sine wave data can be generated only by a process that can be realized with the simple digital circuit. It can provide and power consumption is a feasible, yet the strain less sinusoidal digital sine wave data generator capable of generating data.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main configuration of a button telephone system including a sine wave data generator and a tone detection circuit according to the present invention.
FIG. 2 is a block diagram showing a specific configuration of a sine wave data generator 18 according to the first embodiment of the present invention.
3 is a diagram showing a sine wave indicated by sine wave data generated by the sine wave data generator 18 shown in FIG. 2; FIG.
FIG. 4 is a diagram showing how a maximum strain is generated at the time of resetting.
FIG. 5 is a block diagram showing a specific configuration of a tone detection circuit 19 according to the second embodiment of the present invention.
6 is a block diagram showing a specific configuration of an arithmetic processing unit 53 in FIG.
7 is a block diagram showing a specific configuration of a peak detection unit 55 in FIG.
FIG. 8 is a diagram showing a state of product-sum operation performed by the arithmetic processing unit 53 in FIG. 5;
FIG. 9 is a diagram illustrating a change in an output value V when a product-sum operation is performed with the frequency fx as a frequency of interest and the input signal frequency is changed to fx, fy, and fz.
10 is a diagram showing frequency spectra detected for each frequency of interest by the tone detection circuit 19 shown in FIG.
FIG. 11 is a diagram showing a state in which the frequency spectra shown in FIG. 10 are synthesized.
FIG. 12 is a block diagram showing a specific configuration of a tone detection circuit 19 in the third embodiment of the present invention.
13 is a block diagram showing a specific configuration of a threshold value comparison unit 91 in FIG.
14 is a diagram showing the arrangement of frequency spectra of each frequency of interest detected by the tone detection circuit 19 shown in FIG.
FIG. 15 is a block diagram showing a specific configuration of a tone detection circuit 19 according to a fourth embodiment of the present invention.
16 is a diagram showing the arrangement of the frequency spectrum of each frequency of interest detected by the tone detection circuit 19 shown in FIG.
[Explanation of symbols]
1 ... Main unit
2 (2-1 to 2-i): Extension terminal
11 ... Time switch
12 (12-1 to 12-j): Station line interface circuit
13 (13-1 to 13-i): Extension interface circuit
14 ... CPU
15 ... ROM
16 ... RAM
17 ... Data highway interface
18 ... Sine wave data generator
19: Tone detection circuit
20 ... PCM Highway
21 ... Data Highway
22 ... CPU local bus
31 ... Adder
32, 33 ... Latch circuit
34, 35 ... Multiplier
36 ... Output processing section
37 ... Latch circuit
38 ... Comparison part
39: Reference data register
40 ... Comparison part
41 ... Timer
42 ... AND gate
43. Initialization unit
51. Speed converter
52. Compression / linear conversion unit
53. Arithmetic processing part
54. Absolute value conversion unit
55. Peak detector
56: Adder
57. Determination unit
58 ... Register
59 ... CPU interface
60 ... Counter
61 ... Reset signal generator
71: Subtractor
72. Adder
73 (73-1 to 73-p) ... Flip-flop
74 (74-1 to 74-p) ... Flip-flop
75 ... coefficient generator
76 ... Multiplier
81 ... Comparator
82 ... Selector
83 (83-1 to 83-p) ... Flip-flop
91: Threshold comparison unit
92: Determination unit
101: Comparison circuit
102: Threshold register
111... Threshold value comparison unit
112 ... Matrix part
113 ... Register
114 ... CPU interface

Claims (1)

In a digital sine wave data generator that generates sine wave data by outputting a digital value indicating a level of a sine wave signal of a predetermined frequency as an output digital value at a predetermined cycle,
Multiplying means for generating a first reference value obtained by multiplying an output digital value one cycle before by a constant determined according to the frequency of the sine wave signal;
Inverting means for generating a second reference value obtained by inverting the output digital value two cycles before;
Adding means for adding the first reference value generated by the multiplying means and the second reference value generated by the inverting means to generate a current output digital value;
Resetting means for resetting the first reference value to “0” and the second reference value to an initial value determined according to the frequency of the sine wave signal;
A time measuring means for measuring the elapsed time since the reset by the reset means,
Polarity change detecting means for detecting that the polarity of the output digital value generated by the adding means has changed from positive to negative;
Level confirmation means for detecting a low level state in which the absolute value of the output digital value is equal to or less than a predetermined reference value;
In a state in which the elapsed time measured by the time measuring means exceeds a predetermined time, the low level state is detected by the level confirmation means when the polarity change is detected by the polarity change detecting means. If so, a digital sine wave data generator comprising reset control means for causing the reset means to reset.

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