JP4516961B2 - 半導体試験システム、試験プログラムを生成するための方法、及びプリヘッダ - Google Patents

半導体試験システム、試験プログラムを生成するための方法、及びプリヘッダ Download PDF

Info

Publication number
JP4516961B2
JP4516961B2 JP2006519571A JP2006519571A JP4516961B2 JP 4516961 B2 JP4516961 B2 JP 4516961B2 JP 2006519571 A JP2006519571 A JP 2006519571A JP 2006519571 A JP2006519571 A JP 2006519571A JP 4516961 B2 JP4516961 B2 JP 4516961B2
Authority
JP
Japan
Prior art keywords
test
file
header
program
class
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006519571A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007528993A (ja
JP2007528993A5 (enExample
Inventor
プラマニック、アンカン
エルストン、マーク
クリッシュナスワミィ、ラマチャンドラン
敏明 足立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of JP2007528993A publication Critical patent/JP2007528993A/ja
Publication of JP2007528993A5 publication Critical patent/JP2007528993A5/ja
Application granted granted Critical
Publication of JP4516961B2 publication Critical patent/JP4516961B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/263Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2006519571A 2004-05-22 2005-05-23 半導体試験システム、試験プログラムを生成するための方法、及びプリヘッダ Expired - Fee Related JP4516961B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US57357704P 2004-05-22 2004-05-22
US10/918,714 US7197417B2 (en) 2003-02-14 2004-08-13 Method and structure to develop a test program for semiconductor integrated circuits
PCT/JP2005/009813 WO2005114235A2 (en) 2004-05-22 2005-05-23 Method and structure to develop a test program for semiconductor integrated circuits

Publications (3)

Publication Number Publication Date
JP2007528993A JP2007528993A (ja) 2007-10-18
JP2007528993A5 JP2007528993A5 (enExample) 2010-02-12
JP4516961B2 true JP4516961B2 (ja) 2010-08-04

Family

ID=34975206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006519571A Expired - Fee Related JP4516961B2 (ja) 2004-05-22 2005-05-23 半導体試験システム、試験プログラムを生成するための方法、及びプリヘッダ

Country Status (6)

Country Link
US (1) US7197417B2 (enExample)
EP (1) EP1756601B1 (enExample)
JP (1) JP4516961B2 (enExample)
KR (1) KR20070014206A (enExample)
TW (1) TWI365387B (enExample)
WO (1) WO2005114235A2 (enExample)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7197417B2 (en) * 2003-02-14 2007-03-27 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
US7437261B2 (en) * 2003-02-14 2008-10-14 Advantest Corporation Method and apparatus for testing integrated circuits
US7184917B2 (en) 2003-02-14 2007-02-27 Advantest America R&D Center, Inc. Method and system for controlling interchangeable components in a modular test system
US7340364B1 (en) * 2003-02-26 2008-03-04 Advantest Corporation Test apparatus, and control method
CN1567223A (zh) * 2003-07-09 2005-01-19 松下电器产业株式会社 程序生成装置、方法及程序
US7430486B2 (en) * 2004-05-22 2008-09-30 Advantest America R&D Center, Inc. Datalog support in a modular test system
US7210087B2 (en) * 2004-05-22 2007-04-24 Advantest America R&D Center, Inc. Method and system for simulating a modular test system
US7197416B2 (en) * 2004-05-22 2007-03-27 Advantest America R&D Center, Inc. Supporting calibration and diagnostics in an open architecture test system
KR100548199B1 (ko) * 2004-07-15 2006-02-02 삼성전자주식회사 아날로그/디지털 혼합 신호 반도체 디바이스 테스트 장치
US8725748B1 (en) * 2004-08-27 2014-05-13 Advanced Micro Devices, Inc. Method and system for storing and retrieving semiconductor tester information
US7865880B2 (en) * 2004-11-16 2011-01-04 Lsi Corporation System and/or method for implementing efficient techniques for testing common information model providers
US7624379B2 (en) * 2005-01-12 2009-11-24 Advanced Testing Technologies, Inc. Test program set obsolescence mitigation through software and automatic test equipment system processes
US8484618B2 (en) 2005-01-12 2013-07-09 Advanced Testing Technologies, Inc. Test program set obsolescence mitigation through software and automatic test equipment processes
US8214800B2 (en) * 2005-03-02 2012-07-03 Advantest Corporation Compact representation of vendor hardware module revisions in an open architecture test system
US7253607B2 (en) * 2005-04-29 2007-08-07 Teradyne, Inc. Site-aware objects
US7254508B2 (en) * 2005-04-29 2007-08-07 Teradyne, Inc. Site loops
US7487422B2 (en) * 2005-04-29 2009-02-03 Teradyne, Inc. Delayed processing of site-aware objects
JP4427002B2 (ja) * 2005-05-20 2010-03-03 株式会社アドバンテスト 半導体試験用プログラムデバッグ装置
US7528622B2 (en) 2005-07-06 2009-05-05 Optimal Test Ltd. Methods for slow test time detection of an integrated circuit during parallel testing
US7458043B1 (en) * 2005-09-15 2008-11-25 Unisys Corporation Generation of tests used in simulating an electronic circuit design
US7567947B2 (en) 2006-04-04 2009-07-28 Optimaltest Ltd. Methods and systems for semiconductor testing using a testing scenario language
US10838714B2 (en) * 2006-04-24 2020-11-17 Servicenow, Inc. Applying packages to configure software stacks
US7590903B2 (en) * 2006-05-15 2009-09-15 Verigy (Singapore) Pte. Ltd. Re-configurable architecture for automated test equipment
US7532024B2 (en) * 2006-07-05 2009-05-12 Optimaltest Ltd. Methods and systems for semiconductor testing using reference dice
US7558770B2 (en) * 2006-08-23 2009-07-07 International Business Machines Corporation Method and system to detect application non-conformance
US8359585B1 (en) 2007-01-18 2013-01-22 Advanced Testing Technologies, Inc. Instrumentation ATS/TPS mitigation utilizing I/O data stream
US7761471B1 (en) * 2007-10-16 2010-07-20 Jpmorgan Chase Bank, N.A. Document management techniques to account for user-specific patterns in document metadata
US7809520B2 (en) * 2007-11-05 2010-10-05 Advantest Corporation Test equipment, method for loading test plan and program product
US20090319997A1 (en) * 2008-06-20 2009-12-24 Microsoft Corporation Precondition rules for static verification of code
WO2010055964A1 (en) * 2008-11-17 2010-05-20 Industry-University Cooperation Foundation Hanyang University Method of testing semiconductor device
US8149721B2 (en) * 2008-12-08 2012-04-03 Advantest Corporation Test apparatus and test method
US20110012902A1 (en) * 2009-07-16 2011-01-20 Jaganathan Rajagopalan Method and system for visualizing the performance of applications
KR101028359B1 (ko) * 2009-12-10 2011-04-11 주식회사 이노와이어리스 스크립트를 이용한 dut 자동화 테스트 장치
US10089119B2 (en) 2009-12-18 2018-10-02 Microsoft Technology Licensing, Llc API namespace virtualization
EP2534580A4 (en) * 2010-05-05 2017-11-29 Teradyne, Inc. System for concurrent test of semiconductor devices
US8776014B2 (en) 2010-09-23 2014-07-08 Microsoft Corporation Software build analysis
JP5626786B2 (ja) * 2010-11-09 2014-11-19 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation ソフトウエア開発支援方法とソフトウエア開発支援装置とソフトウエア開発支援プログラム
TW201301135A (zh) * 2011-06-16 2013-01-01 Hon Hai Prec Ind Co Ltd 零件資料轉檔系統及方法
US8776094B2 (en) 2011-08-11 2014-07-08 Microsoft Corporation Runtime system
EP2557501B1 (en) * 2011-08-11 2016-03-16 Intel Deutschland GmbH Circuit arrangement and method for testing same
US8695021B2 (en) 2011-08-31 2014-04-08 Microsoft Corporation Projecting native application programming interfaces of an operating system into other programming languages
US9217772B2 (en) * 2012-07-31 2015-12-22 Infineon Technologies Ag Systems and methods for characterizing devices
US8789006B2 (en) * 2012-11-01 2014-07-22 Nvidia Corporation System, method, and computer program product for testing an integrated circuit from a command line
CN103092156B (zh) * 2012-12-26 2016-02-10 莱诺斯科技(北京)有限公司 设备可替换型自动化测试系统及方法
US9785542B2 (en) * 2013-04-16 2017-10-10 Advantest Corporation Implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing
US9785526B2 (en) * 2013-04-30 2017-10-10 Advantest Corporation Automated generation of a test class pre-header from an interactive graphical user interface
US10635504B2 (en) 2014-10-16 2020-04-28 Microsoft Technology Licensing, Llc API versioning independent of product releases
EP3213214B1 (fr) * 2014-10-30 2021-03-03 SPHEREA Test & Services Banc et logiciel pour tester un appareillage electrique, notamment un calculateur
EP3032270A1 (en) * 2014-12-12 2016-06-15 Airbus Defence and Space, S.A. Method and system for performing electrical tests to complex devices
KR101688632B1 (ko) * 2015-07-31 2016-12-22 한국전자통신연구원 라이브러리 적재 탐지를 위한 방법 및 장치
US10095596B1 (en) * 2015-12-18 2018-10-09 Amazon Technologies, Inc. Executing integration tests in a distributed load and performance evaluation framework
US9733930B2 (en) * 2015-12-21 2017-08-15 Successfactors, Inc. Logical level difference detection between software revisions
US10191736B2 (en) * 2017-04-28 2019-01-29 Servicenow, Inc. Systems and methods for tracking configuration file changes
TWI676906B (zh) * 2018-04-13 2019-11-11 和碩聯合科技股份有限公司 提示方法及其電腦系統
KR102583174B1 (ko) 2018-06-12 2023-09-26 삼성전자주식회사 테스트 인터페이스 보드, 이를 포함하는 테스트 시스템 및 이의 동작 방법
US11159303B1 (en) 2018-11-20 2021-10-26 Mitsubishi Electric Corporation Communication system, list distribution station, communication method, and computer readable medium
JP7122236B2 (ja) * 2018-11-28 2022-08-19 東京エレクトロン株式会社 検査装置、メンテナンス方法、及びプログラム
US11182265B2 (en) * 2019-01-09 2021-11-23 International Business Machines Corporation Method and apparatus for test generation
CN110082666B (zh) * 2019-04-10 2022-02-22 杭州微纳核芯电子科技有限公司 芯片测试分析方法、装置、设备及存储介质
US11656270B2 (en) * 2019-05-09 2023-05-23 Ase Test, Inc. Apparatus and method of testing electronic components
CN111880079B (zh) * 2020-07-24 2022-12-13 安测半导体技术(江苏)有限公司 一种芯片测试监控方法及服务器
CN112100954B (zh) * 2020-08-31 2024-07-09 北京百度网讯科技有限公司 验证芯片的方法、装置和计算机存储介质
CN113051114A (zh) * 2021-03-19 2021-06-29 无锡市软测认证有限公司 一种用于提高芯片测试效率的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK557884A (da) * 1983-11-25 1985-05-26 Mars Inc Automatisk testudstyr
US5488573A (en) 1993-09-02 1996-01-30 Matsushita Electric Industrial Co., Ltd. Method for generating test programs
US5892949A (en) 1996-08-30 1999-04-06 Schlumberger Technologies, Inc. ATE test programming architecture
US6182258B1 (en) 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US6028439A (en) 1997-10-31 2000-02-22 Credence Systems Corporation Modular integrated circuit tester with distributed synchronization and control
US6195774B1 (en) 1998-08-13 2001-02-27 Xilinx, Inc. Boundary-scan method using object-oriented programming language
US6601018B1 (en) 1999-02-04 2003-07-29 International Business Machines Corporation Automatic test framework system and method in software component testing
US6427223B1 (en) 1999-04-30 2002-07-30 Synopsys, Inc. Method and apparatus for adaptive verification of circuit designs
US6678643B1 (en) 1999-06-28 2004-01-13 Advantest Corp. Event based semiconductor test system
US6405364B1 (en) 1999-08-31 2002-06-11 Accenture Llp Building techniques in a development architecture framework
US6779140B2 (en) 2001-06-29 2004-08-17 Agilent Technologies, Inc. Algorithmically programmable memory tester with test sites operating in a slave mode
JP2003173266A (ja) * 2001-12-05 2003-06-20 Mitsubishi Electric Corp プログラム生成システム、プログラム変換システム、プログラム変換方法、半導体装置開発システム、記録媒体及びプログラム
KR100936855B1 (ko) * 2002-04-11 2010-01-14 가부시키가이샤 어드밴티스트 Asic/soc 제조시에 프로토타입-홀드를 방지하기위한 제조 방법 및 장치
US7197417B2 (en) * 2003-02-14 2007-03-27 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
TWI344595B (en) 2003-02-14 2011-07-01 Advantest Corp Method and structure to develop a test program for semiconductor integrated circuits
US7437261B2 (en) 2003-02-14 2008-10-14 Advantest Corporation Method and apparatus for testing integrated circuits
US7184917B2 (en) 2003-02-14 2007-02-27 Advantest America R&D Center, Inc. Method and system for controlling interchangeable components in a modular test system

Also Published As

Publication number Publication date
KR20070014206A (ko) 2007-01-31
WO2005114235A2 (en) 2005-12-01
EP1756601A2 (en) 2007-02-28
US20050154551A1 (en) 2005-07-14
JP2007528993A (ja) 2007-10-18
TWI365387B (en) 2012-06-01
EP1756601B1 (en) 2009-12-09
WO2005114235A3 (en) 2006-04-20
TW200617704A (en) 2006-06-01
US7197417B2 (en) 2007-03-27

Similar Documents

Publication Publication Date Title
JP4516961B2 (ja) 半導体試験システム、試験プログラムを生成するための方法、及びプリヘッダ
JP3890079B1 (ja) モジュール式試験システムにおける交換可能コンポーネントを制御するための方法及びシステム
JP4332179B2 (ja) パターンコンパイラ
JP4332200B2 (ja) モジュール式試験システム内のパターンオブジェクトファイルを管理するための方法およびモジュール式試験システム
JP3939336B2 (ja) 半導体集積回路用のテストプログラムを開発する方法および構造
US8255198B2 (en) Method and structure to develop a test program for semiconductor integrated circuits
JP2007528993A5 (enExample)
US7809520B2 (en) Test equipment, method for loading test plan and program product
KR20070023762A (ko) 반도체 집적 회로를 위한 테스트 프로그램을 개발하는 방법및 구조
KR20070035507A (ko) 모듈식 테스트 시스템에서 호환성있는 컴포넌트를 제어하는방법 및 시스템
Dollas et al. A KNOWLEDGE BASED ENVIRONMENT FOR INTEGRATED CIRCUIT TESTING

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080707

RD13 Notification of appointment of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7433

Effective date: 20090925

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20090925

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091211

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100112

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100305

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100511

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100517

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130521

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130521

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130521

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140521

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees