JP4513532B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4513532B2
JP4513532B2 JP2004348280A JP2004348280A JP4513532B2 JP 4513532 B2 JP4513532 B2 JP 4513532B2 JP 2004348280 A JP2004348280 A JP 2004348280A JP 2004348280 A JP2004348280 A JP 2004348280A JP 4513532 B2 JP4513532 B2 JP 4513532B2
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resin film
film
pad
polyimide resin
opening
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JP2006156869A (en
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康一 和田
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

本発明は、半導体装置の製造方法及び半導体装置に関する。特に本発明は、半導体チップを配線基板に固定する際に用いられる異方性導電性樹脂と、半導体チップのパッシベーション膜上の樹脂膜との剥離を抑制した半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device in which peeling between an anisotropic conductive resin used for fixing a semiconductor chip to a wiring substrate and a resin film on a passivation film of the semiconductor chip is suppressed.

図５は、従来の半導体装置の構成を説明する為の断面図である。本図に示す半導体装置は、半導体チップと配線基板とを異方性導電性樹脂を用いて固定したものであり、半導体チップのバンプと配線基板上の配線とは、異方性導電性樹脂のフィラーを介して接続している。   FIG. 5 is a cross-sectional view for explaining the configuration of a conventional semiconductor device. The semiconductor device shown in this figure is obtained by fixing a semiconductor chip and a wiring board using an anisotropic conductive resin. The bumps of the semiconductor chip and the wiring on the wiring board are made of an anisotropic conductive resin. Connected via filler.

半導体チップのシリコン基板（図示せず）には、トランジスタ等の半導体素子（図示せず）が形成されている。半導体素子上には、層間絶縁膜及び配線層が、この順に繰り返し積層されている。最上層の層間絶縁膜１００上には、Ａｌ合金パッド１０１が形成されている。層間絶縁膜１００上及びＡｌ合金パッド１０１上にはパッシベーション膜１０２が形成されており、パッシベーション膜１０２上にはポリイミド樹脂膜１０３が形成されている。パッシベーション膜１０２にはＡｌ合金パッド１０１上に位置する第１の開口部１０２ａが形成されており、ポリイミド樹脂膜１０３には、第１の開口部１０２ａ上に位置する第２の開口部１０３ａが形成されている。ポリイミド樹脂膜１０３上にはＡｕバンプ１０４が形成されている。Ａｕバンプ１０４は、一部が第１の開口部１０２ａ及び第２の開口部１０３ａ内に埋め込まれることにより、底部がＡｌ合金パッド１０１に接続している。   A semiconductor element (not shown) such as a transistor is formed on a silicon substrate (not shown) of the semiconductor chip. On the semiconductor element, an interlayer insulating film and a wiring layer are repeatedly laminated in this order. An Al alloy pad 101 is formed on the uppermost interlayer insulating film 100. A passivation film 102 is formed on the interlayer insulating film 100 and the Al alloy pad 101, and a polyimide resin film 103 is formed on the passivation film 102. A first opening 102 a located on the Al alloy pad 101 is formed in the passivation film 102, and a second opening 103 a located on the first opening 102 a is formed in the polyimide resin film 103. Has been. Au bumps 104 are formed on the polyimide resin film 103. A part of the Au bump 104 is embedded in the first opening 102 a and the second opening 103 a, so that the bottom is connected to the Al alloy pad 101.

半導体チップは、異方性導電性樹脂フィルム１２２によって配線基板１２０上に固定されている。異方性導電性樹脂フィルム１２２には、導電性のフィラー１２２ａが多数混ぜられており、これらのフィラー１２２ａの一部を間に挟むことにより、半導体チップのＡｕバンプ１０４は配線基板１２０表面の配線１２０ａに接続している。   The semiconductor chip is fixed on the wiring substrate 120 by an anisotropic conductive resin film 122. A large number of conductive fillers 122a are mixed in the anisotropic conductive resin film 122. By sandwiching a part of these fillers 122a, the Au bumps 104 of the semiconductor chip are connected to the wiring on the surface of the wiring board 120. 120a is connected.

配線１２０ａは、配線基板１２０内を上下に走っている配線を介して、配線基板１２０の裏面に設けられた配線１２０ｂに接続している。配線１２０ｂには、配線基板１２０を実装基板（図示せず）に接続するためのソルダーボール１２４が取り付けられている（例えば特許文献１参照）。
特開平１１−２６０９５４号公報（図１６） The wiring 120a is connected to the wiring 120b provided on the back surface of the wiring board 120 through the wiring running up and down in the wiring board 120. Solder balls 124 for connecting the wiring board 120 to a mounting board (not shown) are attached to the wiring 120b (see, for example, Patent Document 1).
Japanese Patent Application Laid-Open No. 11-260954 (FIG. 16)

ポリイミド樹脂膜にパッド上に位置する開口部を形成するとき、パッド上にポリイミド樹脂膜が残留することがある。また、バンプを形成する前に、一時的にパッドが露出するため、パッドの表面が酸化されている場合がある。これらの場合、バンプとパッドの接続不良が生じうる。このため、ポリイミド樹脂膜に開口部を形成した後、パッドの表面をクリーニングするために、全体を酸素等のプラズマに晒すことがある。この場合、ポリイミド樹脂膜の表面粗さが大きくなるため、ポリイミド樹脂膜と異方性導電性樹脂とが剥離しやすくなり、隙間（例えば図５の符号１３０で示す部分）が形成されることがある。   When the opening located on the pad is formed in the polyimide resin film, the polyimide resin film may remain on the pad. In addition, since the pad is temporarily exposed before the bump is formed, the surface of the pad may be oxidized. In these cases, connection failure between the bump and the pad may occur. For this reason, after forming the opening in the polyimide resin film, the entire surface may be exposed to plasma such as oxygen in order to clean the surface of the pad. In this case, since the surface roughness of the polyimide resin film is increased, the polyimide resin film and the anisotropic conductive resin are easily separated, and a gap (for example, a portion indicated by reference numeral 130 in FIG. 5) is formed. is there.

本発明は上記のような事情を考慮してなされたものであり、その目的は、パッシベーション膜上の樹脂膜と、異方性導電性樹脂との剥離を抑制した半導体装置の製造方法及び半導体装置を提供することにある。   The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device in which peeling between the resin film on the passivation film and the anisotropic conductive resin is suppressed. Is to provide.

上記課題を解決するため、本発明に係る半導体装置の製造方法は、絶縁膜上にパッドを形成する工程と、
前記絶縁膜上及び前記パッド上に、パッシベーション膜を形成する工程と、
前記パッシベーション膜に、前記パッド上に位置する第１の開口部を形成する工程と、
前記パッシベーション膜上及び前記第１の開口部内に、樹脂膜を形成する工程と、
前記樹脂膜に、前記パッド上に位置する第２の開口部を形成する工程と、
前記樹脂膜及び前記第２の開口部をプラズマ処理することにより、前記パッドの表面をクリーニングする工程と、
前記樹脂膜を熱処理する工程とを具備する。 In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a pad on an insulating film,
Forming a passivation film on the insulating film and the pad;
Forming a first opening located on the pad in the passivation film;
Forming a resin film on the passivation film and in the first opening;
Forming a second opening located on the pad in the resin film;
Cleaning the surface of the pad by plasma processing the resin film and the second opening;
Heat treating the resin film.

この半導体装置の製造方法によれば、プラズマ処理でパッドの表面をクリーニングした後、プラズマ処理で樹脂膜の表面粗さが大きくなっても、その後の熱処理によって樹脂膜の表面粗さを小さくすることができる。従って、従来と比べて異方性導電性樹脂と樹脂膜の密着性を向上させることができる。樹脂膜は、例えば感光性のポリイミド樹脂膜である。   According to this method of manufacturing a semiconductor device, after the surface of the pad is cleaned by plasma processing, even if the surface roughness of the resin film is increased by plasma processing, the surface roughness of the resin film is reduced by subsequent heat treatment. Can do. Accordingly, the adhesion between the anisotropic conductive resin and the resin film can be improved as compared with the conventional case. The resin film is, for example, a photosensitive polyimide resin film.

前記熱処理する工程の後に、前記第２の開口部に、前記パッドに接続するバンプを形成する工程と、異方性導電性樹脂を用いて、前記バンプを配線基板上の配線に接続する工程と、
を更に具備してもよい。パッドの表面をクリーニングする工程において、酸素プラズマ又はＡｒプラズマを用いてもよい。 After the heat treatment step, a step of forming a bump connected to the pad in the second opening, and a step of connecting the bump to a wiring on a wiring board using an anisotropic conductive resin; ,
May further be provided. In the step of cleaning the surface of the pad, oxygen plasma or Ar plasma may be used.

本発明に係る他の半導体装置の製造方法は、異方性導電性樹脂を用いて半導体チップを配線基板に固定することにより、前記半導体チップが有するバンプと、前記配線基板が有する配線とを接続する工程を具備し、
前記半導体チップは、実装面に樹脂膜を具備し、該樹脂膜の表面は、プラズマ処理が行われた後、熱処理が行われている。 In another method of manufacturing a semiconductor device according to the present invention, a semiconductor chip is fixed to a wiring board using an anisotropic conductive resin, thereby connecting bumps of the semiconductor chip and wirings of the wiring board. Comprising the steps of:
The semiconductor chip includes a resin film on a mounting surface, and the surface of the resin film is subjected to a heat treatment after being subjected to a plasma treatment.

本発明に係る半導体装置は、絶縁膜と、
前記絶縁膜上に形成されたパッドと、
前記絶縁膜上に形成され、前記パッド上に位置する第１の開口部を有するパッシベーション膜と、
前記パッシベーション膜上に形成され、前記第１の開口部上に位置する第２の開口部を有する樹脂膜と、
を具備し、前記樹脂膜は、表面にプラズマ処理が行われた後、熱処理が行われている。 A semiconductor device according to the present invention includes an insulating film,
A pad formed on the insulating film;
A passivation film formed on the insulating film and having a first opening located on the pad;
A resin film formed on the passivation film and having a second opening located on the first opening;
The resin film is subjected to a heat treatment after the surface is subjected to a plasma treatment.

本発明に係る他の半導体装置は、絶縁膜と、
前記絶縁膜上に形成されたパッドと、
前記絶縁膜上に形成され、前記パッド上に位置する第１の開口部を有するパッシベーション膜と、
前記パッシベーション膜上に形成され、前記第１の開口部上に位置する第２の開口部を有するエステル結合型のポリイミド樹脂膜と、
を具備し、前記ポリイミド樹脂膜の表面粗さは５ｎｍ以上３０ｎｍ以下である。 Another semiconductor device according to the present invention includes an insulating film,
A pad formed on the insulating film;
A passivation film formed on the insulating film and having a first opening located on the pad;
An ester bond-type polyimide resin film formed on the passivation film and having a second opening located on the first opening;
The surface roughness of the polyimide resin film is 5 nm or more and 30 nm or less.

本発明に係る他の半導体装置は、絶縁膜と、
前記絶縁膜上に形成されたパッドと、
前記絶縁膜上に形成され、前記パッド上に位置する第１の開口部を有するパッシベーション膜と、
前記パッシベーション膜上に形成され、前記第１の開口部上に位置する第２の開口部を有するイオン結合型のポリイミド樹脂膜と、
を具備し、前記ポリイミド樹脂膜の表面粗さは１０ｎｍ以下である。 Another semiconductor device according to the present invention includes an insulating film,
A pad formed on the insulating film;
A passivation film formed on the insulating film and having a first opening located on the pad;
An ion-bonded polyimide resin film formed on the passivation film and having a second opening located on the first opening;
The polyimide resin film has a surface roughness of 10 nm or less.

本発明に係る他の半導体装置は、半導体チップのバンプと配線基板の配線とを、異方性導電性樹脂で接続した半導体装置であって、
前記半導体チップは、
絶縁膜と、
前記絶縁膜上に形成されたパッドと、
前記絶縁膜上に形成され、前記パッド上に位置する第１の開口部を有するパッシベーション膜と、
前記パッシベーション膜上に形成され、前記第１の開口部上に位置する第２の開口部を有する樹脂膜と、
前記第１及び前記第２の開口部に一部が埋め込まれることにより前記パッドに接続するバンプと、
を具備し、前記樹脂膜は、表面にプラズマ処理が行われた後、熱処理が行われている。 Another semiconductor device according to the present invention is a semiconductor device in which bumps of a semiconductor chip and wiring of a wiring board are connected by an anisotropic conductive resin,
The semiconductor chip is
An insulating film;
A pad formed on the insulating film;
A passivation film formed on the insulating film and having a first opening located on the pad;
A resin film formed on the passivation film and having a second opening located on the first opening;
A bump connected to the pad by being partially embedded in the first and second openings;
The resin film is subjected to a heat treatment after the surface is subjected to a plasma treatment.

発明を実施するための形態BEST MODE FOR CARRYING OUT THE INVENTION

以下、図面を参照して本発明の実施形態について説明する。図１は、本発明の実施形態に係る半導体チップの製造方法を説明するフローチャートである。図２の各図は、図１に示した半導体チップの製造方法を説明する為の断面図である。本実施形態は、半導体チップ表面上のポリイミド樹脂膜に、パッド上に位置する開口部を形成し、パッド表面をプラズマ処理してクリーニングした後、ポリイミド樹脂膜にアニール処理を行うことにより、ポリイミド樹脂膜の表面粗さを調整するものである。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart for explaining a semiconductor chip manufacturing method according to an embodiment of the present invention. Each drawing in FIG. 2 is a cross-sectional view for explaining a method of manufacturing the semiconductor chip shown in FIG. In this embodiment, the polyimide resin film on the semiconductor chip surface is formed with an opening located on the pad, the pad surface is cleaned by plasma treatment, and then the polyimide resin film is annealed to obtain a polyimide resin. The surface roughness of the film is adjusted.

まず、ウェハ状のシリコン基板（図示せず）上にトランジスタ等の半導体素子を複数形成し、これら半導体素子上に層間絶縁膜（図示せず）及びＡｌ合金配線層（図示せず）を、交互にそれぞれ複数回積層する。   First, a plurality of semiconductor elements such as transistors are formed on a wafer-like silicon substrate (not shown), and an interlayer insulating film (not shown) and an Al alloy wiring layer (not shown) are alternately formed on these semiconductor elements. Each is laminated several times.

そして、図１のＳ２及び図２（Ａ）それぞれに示すように、最上層の層間絶縁膜１０上に、Ａｌ合金膜をスパッタリング法により形成する。次いで、このＡｌ合金膜上にフォトレジスト膜を塗布し、このフォトレジスト膜を露光及び現像する。これにより、Ａｌ合金膜上にはレジストパターンが形成される。次いで、このレジストパターンをマスクとしてＡｌ合金膜をエッチングする。これにより、Ａｌ合金膜はパターニングされ、最上層のＡｌ合金配線（図示せず）及びＡｌ合金パッド１１が形成される。その後、レジストパターンを除去する。   Then, as shown in S2 of FIG. 1 and FIG. 2A, an Al alloy film is formed on the uppermost interlayer insulating film 10 by a sputtering method. Next, a photoresist film is applied on the Al alloy film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. Thereby, the Al alloy film is patterned, and the uppermost Al alloy wiring (not shown) and the Al alloy pad 11 are formed. Thereafter, the resist pattern is removed.

次いで、層間絶縁膜１０上及びＡｌ合金パッド１１上に、酸化シリコン膜及び窒化シリコン膜をこの順に積層したパッシベーション膜１２を、ＣＶＤ法を用いて形成する。次いで、パッシベーション膜１２上にフォトレジスト膜（図示せず）を塗布し、このフォトレジスト膜を露光及び現像する。これにより、パッシベーション膜１２上にはレジストパターンが形成される。次いで、このレジストパターンをマスクとしてパッシベーション膜１２をエッチングする。これにより、パッシベーション膜１２には、Ａｌ合金パッド１１上に位置する第１の開口部１２ａが形成される。その後、レジストパターンを除去する。   Next, a passivation film 12 in which a silicon oxide film and a silicon nitride film are stacked in this order on the interlayer insulating film 10 and the Al alloy pad 11 is formed using the CVD method. Next, a photoresist film (not shown) is applied on the passivation film 12, and the photoresist film is exposed and developed. As a result, a resist pattern is formed on the passivation film 12. Next, the passivation film 12 is etched using this resist pattern as a mask. As a result, the first opening 12 a located on the Al alloy pad 11 is formed in the passivation film 12. Thereafter, the resist pattern is removed.

次いで、図１のＳ４及び図２（Ｂ）それぞれに示すように、パッシベーション膜１２上及び第１の開口部１２ａ内にポリイミド樹脂膜１３を塗布する。ここで用いるポリイミド樹脂は、例えば感光性のポリイミド樹脂であるが、エステル結合型及びイオン結合型のいずれであってもよい。次いで、ポリイミド樹脂膜１３を露光及び現像する。これにより、ポリイミド樹脂膜１３には、第１の開口部１２ａ上に位置する第２の開口部１３ａが形成される。なお、この処理において、Ａｌ合金パッド１１上にポリイミド樹脂膜１３の残渣が生じる場合がある。   Next, as shown in S4 of FIG. 1 and FIG. 2B, respectively, a polyimide resin film 13 is applied on the passivation film 12 and in the first opening 12a. The polyimide resin used here is, for example, a photosensitive polyimide resin, but may be either an ester bond type or an ion bond type. Next, the polyimide resin film 13 is exposed and developed. As a result, a second opening 13 a located on the first opening 12 a is formed in the polyimide resin film 13. In this process, a residue of the polyimide resin film 13 may occur on the Al alloy pad 11 in some cases.

次いで、図１のＳ６に示すように、窒素雰囲気下でポリイミド樹脂膜１３に熱処理を行う。ここでの熱処理の条件は、例えば熱処理温度が３５０℃、熱処理時間が１時間である。これにより、ポリイミド樹脂膜１３は硬化する。   Next, as shown in S6 of FIG. 1, the polyimide resin film 13 is heat-treated in a nitrogen atmosphere. The heat treatment conditions here are, for example, a heat treatment temperature of 350 ° C. and a heat treatment time of 1 hour. Thereby, the polyimide resin film 13 is cured.

上記したＳ２〜Ｓ６までの処理において、Ａｌ合金パッド１１は大気に晒される場合がある。このため、Ａｌ合金パッド１１の表面に薄い酸化膜が形成される。   In the processing from S2 to S6 described above, the Al alloy pad 11 may be exposed to the atmosphere. For this reason, a thin oxide film is formed on the surface of the Al alloy pad 11.

次いで、図１のＳ８及び図２（Ｃ）それぞれに示すように、ポリイミド樹脂膜１３をプラズマに晒す。ここで用いるプラズマは、酸素プラズマ又はＡｒプラズマである。これにより、Ａｌ合金パッド１１の表面に位置する酸化膜及びポリイミド樹脂膜１３の残渣はクリーニングされる。なお、この処理において、ポリイミド樹脂膜１３の表面粗さは大きくなる。   Next, as shown in S8 of FIG. 1 and FIG. 2C, the polyimide resin film 13 is exposed to plasma. The plasma used here is oxygen plasma or Ar plasma. Thereby, the residue of the oxide film and the polyimide resin film 13 located on the surface of the Al alloy pad 11 is cleaned. In this process, the surface roughness of the polyimide resin film 13 is increased.

次いで、図１のＳ１０に示すように、ポリイミド樹脂膜１３に熱処理を行う。ここでの熱処理の条件は、例えば窒素雰囲気下で、熱処理温度が２５０℃以上３００℃以下、熱処理時間が６時間である。これにより、ポリイミド樹脂膜１３の表面粗さは制御され、配線基板に実装するときに用いられる異方性導電性樹脂とポリイミド樹脂膜１３の剥離が抑制される。   Next, as shown in S10 of FIG. 1, the polyimide resin film 13 is heat treated. The heat treatment conditions here are, for example, a heat treatment temperature of 250 ° C. to 300 ° C. and a heat treatment time of 6 hours in a nitrogen atmosphere. Thereby, the surface roughness of the polyimide resin film 13 is controlled, and peeling of the anisotropic conductive resin and the polyimide resin film 13 used when mounting on the wiring board is suppressed.

なお、ポリイミド樹脂膜１３がエステル結合型のポリイミド樹脂である場合、熱処理の条件を調整することにより、ポリイミド樹脂膜１３の表面粗さを５ｎｍ以上３０ｎｍ以下にするのが好ましい。また、ポリイミド樹脂膜１３がイオン結合型のポリイミド樹脂である場合、熱処理の条件を調整することにより、ポリイミド樹脂膜１３の表面粗さを１０ｎｍ以下にするのが好ましい。これらのようにすると、特にポリイミド樹脂膜１３は、異方性導電性樹脂とポリイミド樹脂膜１３の剥離が特に抑制される。   In addition, when the polyimide resin film 13 is an ester bond type polyimide resin, it is preferable that the surface roughness of the polyimide resin film 13 is 5 nm or more and 30 nm or less by adjusting the conditions of heat treatment. When the polyimide resin film 13 is an ion-bonded polyimide resin, it is preferable to adjust the heat treatment conditions so that the surface roughness of the polyimide resin film 13 is 10 nm or less. If it does in these ways, especially the polyimide resin film 13 will suppress especially peeling of anisotropic conductive resin and the polyimide resin film 13. FIG.

次いで、図１のＳ１２に示すように、シリコン基板の裏面を研削し、薄くする。次いで、図１のＳ１４に示すように、シリコン基板をダイシングし、複数のチップに分割する。   Next, as shown in S12 of FIG. 1, the back surface of the silicon substrate is ground and thinned. Next, as shown in S14 of FIG. 1, the silicon substrate is diced and divided into a plurality of chips.

図３は、図１及び図２を用いて説明した方法により製造された半導体チップを、配線基板に実装する方法を説明するフローチャートである。図４の各図は、図１に示した半導体チップの製造方法を説明する為の断面図である。本方法はＦＣＢＧＡ実装方法であり、半導体チップにバンプを形成し、その後、異方性導電性樹脂を用いて半導体チップを配線基板に実装する方法である。   FIG. 3 is a flowchart for explaining a method of mounting a semiconductor chip manufactured by the method described with reference to FIGS. 1 and 2 on a wiring board. Each drawing in FIG. 4 is a cross-sectional view for explaining a method of manufacturing the semiconductor chip shown in FIG. This method is an FCBGA mounting method in which bumps are formed on a semiconductor chip, and then the semiconductor chip is mounted on a wiring board using an anisotropic conductive resin.

まず、図３のＳ２２及び図４（Ａ）に示すように、ボンディングツ−ル（図示せず）を用いることにより、半導体チップの第１の開口部１２ａ及び第２の開口部１３ａに、Ａｕバンプ１４を形成する。Ａｕバンプ１４は、底部がＡｌ合金パッド１１に接続しており、上部が半導体チップのポリイミド樹脂膜１３より上方に位置している。   First, as shown in S22 of FIG. 3 and FIG. 4A, by using a bonding tool (not shown), the first opening 12a and the second opening 13a of the semiconductor chip are made Au. Bumps 14 are formed. The Au bump 14 has a bottom connected to the Al alloy pad 11 and an upper portion located above the polyimide resin film 13 of the semiconductor chip.

次いで、図３のＳ２４及び図４（Ｂ）に示すように、配線基板２０上に異方性導電性樹脂フィルム２２を貼り付けておき、この異方性導電性樹脂フィルム２２を介して半導体チップを配線基板２０に熱圧着する。これにより、半導体チップは配線基板２０の表面上に固定される。また、異方性導電性樹脂フィルム２２の導電性のフィラー２２ａが、配線基板２０の表面上に形成された配線２０ａと、半導体チップのＡｕバンプ１４との間に挟まれる。これにより、Ａｕバンプ１４と配線２０ａとが接続される。なお、ポリイミド樹脂膜１３が形成されているため、熱圧着時に半導体チップの配線層やトランジスタに加わる力が緩和される。   Next, as shown in S24 of FIG. 3 and FIG. 4B, an anisotropic conductive resin film 22 is pasted on the wiring board 20, and the semiconductor chip is interposed via the anisotropic conductive resin film 22. Is thermocompression bonded to the wiring board 20. Thereby, the semiconductor chip is fixed on the surface of the wiring substrate 20. Moreover, the conductive filler 22a of the anisotropic conductive resin film 22 is sandwiched between the wiring 20a formed on the surface of the wiring substrate 20 and the Au bump 14 of the semiconductor chip. Thereby, the Au bump 14 and the wiring 20a are connected. Since the polyimide resin film 13 is formed, the force applied to the wiring layer of the semiconductor chip and the transistor during the thermocompression bonding is alleviated.

また、図１及び図２を用いて説明したように、ポリイミド樹脂膜１３の表面粗さは、熱処理によって調整されている。このため、異方性導電性樹脂フィルム２２とポリイミド樹脂膜１３が剥離することが、従来と比べて抑制される。   Further, as described with reference to FIGS. 1 and 2, the surface roughness of the polyimide resin film 13 is adjusted by heat treatment. For this reason, it is suppressed compared with the past that the anisotropic conductive resin film 22 and the polyimide resin film 13 peel.

次いで、図３のＳ２６及び図４（Ｃ）に示すように、配線基板２０の裏面に位置する配線２０ｃに、ソルダーボール２４を付着する。ソルダーボール２４は、配線２０ｃを実装基板（図示せず）上の配線に接続する端子である。なお、配線２０ｃは、配線基板２０を上下に貫通する配線２０ｂを介して、配線２０ａに接続している。このため、実装基板と半導体チップは、ソルダーボール２４、配線２０ｃ，２０ｂ，２０ａ、及びＡｕバンプ１４を介して互いに接続する。   Next, as shown in S26 of FIG. 3 and FIG. 4C, the solder balls 24 are attached to the wiring 20c located on the back surface of the wiring board 20. The solder ball 24 is a terminal for connecting the wiring 20c to a wiring on a mounting substrate (not shown). In addition, the wiring 20c is connected to the wiring 20a through the wiring 20b which penetrates the wiring board 20 up and down. For this reason, the mounting substrate and the semiconductor chip are connected to each other via the solder balls 24, the wirings 20c, 20b, 20a, and the Au bumps 14.

以上、本発明の実施形態によれば、Ａｌ合金パッド１１の表面をクリーニングするためにプラズマ処理を行い、ポリイミド樹脂膜１３の表面粗さが不適切な状態になっても、プラズマ処理後にポリイミド樹脂膜１３を熱処理しているため、ポリイミド樹脂膜１３の表面粗さを適切な状態にすることができる。従って、異方性導電性樹脂フィルム２２を用いて半導体チップを配線基板２０に実装した場合、ポリイミド樹脂膜１３と異方性導電性樹脂フィルム２２の剥離を、従来と比べて抑制できる。   As described above, according to the embodiment of the present invention, the plasma treatment is performed to clean the surface of the Al alloy pad 11, and the polyimide resin is used after the plasma treatment even if the surface roughness of the polyimide resin film 13 becomes inappropriate. Since the film 13 is heat-treated, the surface roughness of the polyimide resin film 13 can be set to an appropriate state. Therefore, when the semiconductor chip is mounted on the wiring substrate 20 using the anisotropic conductive resin film 22, the peeling between the polyimide resin film 13 and the anisotropic conductive resin film 22 can be suppressed as compared with the conventional case.

このため、半導体チップが製造後に吸湿材等と共に封止されていなくても、配線基板に実装された後のポリイミド樹脂膜１３と異方性導電性樹脂フィルム２２の密着性は高くなり、耐熱及び耐湿に関する所定の規格（例えばＪＥＣＥＣ規格のレベル１）をクリアすることができる。従って、半導体チップが実装基板に実装されるまでのコストを低くすることができる。   For this reason, even if the semiconductor chip is not sealed with a hygroscopic material or the like after manufacture, the adhesion between the polyimide resin film 13 and the anisotropic conductive resin film 22 after being mounted on the wiring board is increased, A predetermined standard regarding moisture resistance (for example, level 1 of the JECEC standard) can be cleared. Therefore, the cost until the semiconductor chip is mounted on the mounting substrate can be reduced.

尚、本発明は上述した実施形態に限定されるものではなく、本発明の主旨を逸脱しない範囲内で種々変更して実施することが可能である。例えば、上記した実施形態では、ポリイミド樹脂膜１３として感光性のポリイミド樹脂を用いたが、非感光性ポリイミド樹脂を用いてもよい。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, a photosensitive polyimide resin is used as the polyimide resin film 13, but a non-photosensitive polyimide resin may be used.

この場合、パッシベーション膜１２の第１の開口部１２ａと、ポリイミド樹脂膜１３の第２の開口部１３ａを同一工程で形成することができる。すなわち、第１の開口部１２ａを形成する前に、パッシベーション膜１２上にポリイミド樹脂膜１３を形成し、ポリイミド樹脂膜１３上にレジストパターンを形成する。次いで、このレジストパターンをマスクとして、ポリイミド樹脂膜１３及びパッシベーション膜１２をエッチングすることにより、第２の開口部１３ａ及び第１の開口部１２ａを連続して形成する。このようにすると、工程数を少なくすることができる。   In this case, the first opening 12a of the passivation film 12 and the second opening 13a of the polyimide resin film 13 can be formed in the same process. That is, before forming the first opening 12 a, the polyimide resin film 13 is formed on the passivation film 12 and a resist pattern is formed on the polyimide resin film 13. Next, by using the resist pattern as a mask, the polyimide resin film 13 and the passivation film 12 are etched to continuously form the second opening 13a and the first opening 12a. In this way, the number of steps can be reduced.

実施形態に係る半導体チップの製造方法を説明するフローチャート。6 is a flowchart for explaining a method for manufacturing a semiconductor chip according to the embodiment. （Ａ）は図１に示した半導体チップの製造方法を説明する為の断面図、（Ｂ）は（Ａ）の次の工程を説明する為の断面図、（Ｃ）は（Ｂ）の次の工程を説明する為の断面図。(A) is sectional drawing for demonstrating the manufacturing method of the semiconductor chip shown in FIG. 1, (B) is sectional drawing for demonstrating the next process of (A), (C) is following (B). Sectional drawing for demonstrating the process of. 半導体チップを配線基板に実装する方法を説明するフローチャート。The flowchart explaining the method of mounting a semiconductor chip on a wiring board. （Ａ）は図１に示した実装方法を説明する為の断面図、（Ｂ）は（Ａ）の次の工程を説明する為の断面図、（Ｃ）は（Ｂ）の次の工程を説明する為の断面図。(A) is a cross-sectional view for explaining the mounting method shown in FIG. 1, (B) is a cross-sectional view for explaining the next step of (A), and (C) is a next step of (B). Sectional drawing for demonstrating. 従来の半導体装置の構造を説明する為の断面図。Sectional drawing for demonstrating the structure of the conventional semiconductor device.

符号の説明Explanation of symbols

１０，１００…層間絶縁膜、１１，１０１…Ａｌ合金パッド、１２，１０２…パッシベーション膜、１２ａ，１０２ａ…第１の開口部、１３，１０３…ポリイミド樹脂膜、１３ａ，１０３ａ…第２の開口部、１４，１０４…Ａｕバンプ、２０，１２０…配線基板、２０ａ，２０ｂ，２０ｃ，１２０ａ，１２０ｂ…配線、２２，１２２…異方性導電性樹脂フィルム、２２ａ，１２２ａ…フィラー、２４，１２４…ソルダーボール DESCRIPTION OF SYMBOLS 10,100 ... Interlayer insulation film, 11, 101 ... Al alloy pad, 12, 102 ... Passivation film, 12a, 102a ... 1st opening part, 13, 103 ... Polyimide resin film, 13a, 103a ... 2nd opening part , 14, 104 ... Au bumps, 20, 120 ... wiring board, 20a, 20b, 20c, 120a, 120b ... wiring, 22, 122 ... anisotropic conductive resin film, 22a, 122a ... filler, 24, 124 ... solder ball

Claims (4)

絶縁膜上にパッドを形成する工程と、
前記絶縁膜上及び前記パッド上に、パッシベーション膜を形成する工程と、
前記パッシベーション膜に、前記パッド上に位置する第１の開口部を形成する工程と、
前記パッシベーション膜上及び前記第１の開口部内に、樹脂膜を形成する工程と、
前記樹脂膜に、前記パッド上に位置する第２の開口部を形成する工程と、
前記樹脂膜及び前記第２の開口部をプラズマ処理することにより、前記パッドの表面をクリーニングする工程と、
前記樹脂膜を窒素雰囲気下で２５０℃以上３００℃以下の温度で６時間以上熱処理する工程と、
を具備し、
前記樹脂膜は感光性のポリイミド樹脂膜である半導体装置の製造方法。 Forming a pad on the insulating film;
Forming a passivation film on the insulating film and the pad;
Forming a first opening located on the pad in the passivation film;
Forming a resin film on the passivation film and in the first opening;
Forming a second opening located on the pad in the resin film;
Cleaning the surface of the pad by plasma processing the resin film and the second opening;
Heat-treating the resin film at a temperature of 250 ° C. or higher and 300 ° C. or lower for 6 hours or more in a nitrogen atmosphere;
Comprising
The method of manufacturing a semiconductor device, wherein the resin film is a photosensitive polyimide resin film. 前記熱処理する工程の後に、前記第２の開口部に、前記パッドに接続するバンプを形成する工程と、
異方性導電性樹脂を用いて、前記バンプを配線基板上の配線に接続する工程と、
を更に具備する請求項１に記載の半導体装置の製造方法。 Forming a bump connected to the pad in the second opening after the heat treatment step;
Connecting the bump to the wiring on the wiring board using an anisotropic conductive resin;
The method for manufacturing a semiconductor device according to claim 1, further comprising: 前記パッドの表面をクリーニングする工程において、酸素プラズマ又はＡｒプラズマを用いる請求項１又は２に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein oxygen plasma or Ar plasma is used in the step of cleaning the surface of the pad. 異方性導電性樹脂を用いて半導体チップを配線基板に固定することにより、前記半導体チップが有するバンプと、前記配線基板が有する配線とを接続する工程を具備し、
前記半導体チップは、実装面に樹脂膜と前記バンプ下に位置するパッドを具備し、該樹脂膜の表面は、プラズマ処理が行われることにより前記パッドの表面がクリーニングされた後、窒素雰囲気下で２５０℃以上３００℃以下の温度で６時間以上熱処理が行われており、前記樹脂膜は感光性のポリイミド樹脂膜である半導体装置の製造方法。 A step of connecting the bumps of the semiconductor chip and the wiring of the wiring substrate by fixing the semiconductor chip to the wiring substrate using an anisotropic conductive resin;
The semiconductor chip is provided with a pad located below the resin layer bump on the mounting surface, the surface of the resin film, after the surface of the pad by Rukoto plasma processing is performed has been cleaned, under a nitrogen atmosphere In the method of manufacturing a semiconductor device, the heat treatment is performed at a temperature of 250 ° C. or more and 300 ° C. or less for 6 hours or more, and the resin film is a photosensitive polyimide resin film.
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