JP4497493B2 - Ferroelectric memory element and method for manufacturing ferroelectric memory element - Google Patents

Ferroelectric memory element and method for manufacturing ferroelectric memory element Download PDF

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JP4497493B2
JP4497493B2 JP2000119078A JP2000119078A JP4497493B2 JP 4497493 B2 JP4497493 B2 JP 4497493B2 JP 2000119078 A JP2000119078 A JP 2000119078A JP 2000119078 A JP2000119078 A JP 2000119078A JP 4497493 B2 JP4497493 B2 JP 4497493B2
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ferroelectric
film
memory element
thin film
ferroelectric memory
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JP2001308284A (en
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和男 坂巻
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Seiko NPC Corp
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Seiko NPC Corp
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【０００１】
【発明の属する技術分野】
本発明は、強誘電体不揮発性記憶素子およびその製造方法に関し、特に製造プロセス中における強誘電体薄膜の劣化を抑える技術に関する。
【０００２】
【従来の技術】
強誘電体不揮発性記憶素子としては、少なくとも一つのトランジスタと一つの強誘電体キャパシタを接続したタイプと、電界効果型トランジスタのゲートに強誘電体を用いてソース〜ドレイン間の電流を制御するタイプとがある。前者のタイプは、例えば特開平２−１１３４９６号公報に記載されている。後者のタイプは、例えば特開平９−６４２０６号公報に記載されている。
前者のタイプは、従来のＤＲＡＭのキャパシタを強誘電体に置き換えた構造で、ＦＲＡＭ（Ferroelectric Random Access Memory）とも呼ばれる。ＦＲＡＭは低電圧動作であり、かつ、書き換え回数が従来のＥＥＰＲＯＭ（Electrically Erasable and Programmable Read Only Memory）、Ｆｌａｓｈ Ｍｅｍｏｒｙなどの不揮発性メモリより優れており、次世代の不揮発性メモリとして期待されている。後者のタイプは、電界効果型トランジスタのゲート絶縁膜部分に強誘電体を用いた構造で、そのゲート部分の積層構造から、ＭＦ（Ｉ）Ｓ−ＦＥＴ（金属−強誘電体−（絶縁体−）半導体−電界効果型トランジスタ）またはＭＦＭＩＳ−ＦＥＴ（金属−強誘電体−金属−絶縁体−半導体−電界効果型トランジスタ）とも呼ばれる。このタイプは、前者のＦＲＡＭより高速かつ面積縮小化に有利な強誘電体メモリとして提案されている。上記のＦＲＡＭやＭＦ（Ｉ）Ｓ−ＦＥＴ構造やＭＦＭＩＳ−ＦＥＴ構造は、強誘電体薄膜の分極を用いた記憶素子である。
【０００３】
【発明が解決しようとする課題】
しかし、強誘電体として、ＡＢＯ3型構造を持つ強誘電体（但し、Ａ、Ｂは金属元素、以下同じ）、Ａ2Ｂ2Ｏ7型構造を持つ強誘電体、あるいは層状ペロブスカイト構造を持つ強誘電体で、例えば、ＰｂＴｉＯ3、またはＰｂＺｒＴｉＯ3、またはＰｂＬａＺｒＴｉＯ3、またはＢｉ4Ｔｉ3Ｏ12、またはＳｒ2Ｎｂ2Ｏ7、またはＳｒ2（ＴａＮｂ）2Ｏ7、あるいはＳｒＢｉ2Ｔａ2Ｏ9などの酸化化合物であり、通常、半導体製造装置でよく使用されるシラン系ガスを用いた成膜プロセスや水素を用いたシンタリング工程での還元雰囲気中の熱処理により、この強誘電体薄膜の酸化物が金属に還元されてしまい、このため強誘電体薄膜が劣化するという問題点がある。本発明は、上記従来の未解決の問題に着目してなされたものであり、半導体装置製造プロセスの際の還元雰囲気中においても、強誘電体薄膜を劣化させない構造を持った強誘電体記憶素子を提供することを目的とする。
【０００４】
【課題を解決するための手段】
上記目的を達成するために、本発明は強誘電体薄膜を有する強誘電体記憶素子において、水素を吸蔵するＴｉ（チタン）と酸化膜の積層で強誘電体薄膜の少なくとも一部を覆う構造を有する強誘電体記憶素子を提供する。
【０００５】
さらに、本発明では、強誘電体薄膜を有する強誘電体記憶素子において、水素を吸蔵するＴｉ（チタン）と酸化膜の積層で強誘電体薄膜の少なくとも一部を覆い、これら強誘電体薄膜とＴｉ（チタン）と酸化膜の積層を、水素の拡散係数が小さいＢＰＳＧ（boron phosphorus silicate glass）の覆層間絶縁膜でさらに覆う構造を有する強誘電体記憶素子を提供する。以下、本発明の実施の形態について図面を参照して説明する。
【０００６】
【発明の実施の形態】
図１ａから図１ｈは、本発明の一実施の形態によるＭＦＩＳ−ＦＥＴの製造工程を示す図である。図１ａにおいて、Ｐ型半導体基板１の素子間分離用の酸化領域２が形成された主面上に、ＣｅＯ2の相互拡散防止絶縁膜３が電子線ビーム蒸着により形成される。その上に、ＳＢＴ（ＳｒＢｉ2Ｔａ2Ｏ9）の強誘電体薄膜４がスピンコート法により形成された。さらに、ゲート電極としてのＰｔ（白金）電極５がＰｔスパッター装置により積層された。
【０００７】
図１ｂにおいて、ゲート構造部分だけを残すようにマスクして、Ｐｔ（白金）電極層５、ＳＢＴ強誘電体層４、ＣｅＯ2相互拡散防止絶縁膜３がＲＩＥ（リアクティブ・イオン・エッチング）で除去された。図１ｃにおいて、低濃度ソース領域６および低濃度ドレイン領域７の形成のためのＮ-イオン・インプランテーションがゲート構造体をマスクとして行なわれた。そして、活性化および回復のアニール処理が７００℃の酸素雰囲気中で６０分間なされた。
【０００８】
図１ｄにおいて、２００Åないし４００Å厚の薄い二酸化シリコンの第１の酸化膜８の堆積がゲート構造の上に、ＴＥＯＳ（tetraethylorthosilicate）装置で行なわれる。その上に、スパッター装置で２００Åないし４００Å厚のＴｉ（チタン）薄膜９が堆積される。さらに、３０００Å厚の二酸化シリコンの第２の酸化膜８’の堆積が、ＴＥＯＳ（tetraethylorthosilicate）装置で行なわれる。次に図１ｅにおいて、上の厚い第２の酸化膜８’およびＴｉ薄膜９および下の薄い第１の酸化膜８がエッチバックされて、ゲート構造体の両側部分のみにサイドスペースとして残された。
【０００９】
次に、図１ｆにおいて、上の第２の酸化膜８’、Ｔｉ薄膜９および薄い第１の酸化膜８からなるサイドスペースを有するゲート構造体をマスクとして、高濃度ソース領域１０および高濃度ドレイン領域１１を形成するために、Ｎ+のイオン・インプランテーションが行なわれ、活性化および回復のための９００℃のアニール処理が行なわれた。図１ｇに示すように、ＴＥＯＳ（tetraethylorthosilicate）装置により、ＢＰＳＧ（boron phosphorus silicate glass）の層間絶縁膜１２が堆積される。そしてコンタクトホールがＲＩＥ（リアクテイブ・イオン・エッチング）装置でＢＰＳＧ層間絶縁膜１２に形成される。そしてコンタクトホールにアルミニウム電極１３が形成される。そして、図１ｈに示されように、最終保護ＳｉＮ膜１４の堆積がプラズマＣＶＤにより行なわれる。そして、界面準位を下げるためのシンターリングか行なわれる。
【００１０】
図１ａから図１ｈの工程で製作された強誘電体ゲート構造は、ゲートの強誘電体薄膜４の側部を、水素を吸蔵するＴｉ膜９と酸化膜８および８’で覆って保護し、さらに層間絶縁膜として水素の拡散係数が小さいＢＰＳＧ膜１２を設けていることによって、シラン系ガスを用いた最終保護膜の成膜や水素を用いたシンタリングなどの還元雰囲気での熱処理を施しても、強誘電体薄膜４が還元されず、強誘電体薄膜４の劣化を抑えた強誘電体記憶素子ができる。
【００１１】
図２ａから図２ｆは、本発明の第２実施の形態によるＦＲＡＭ用の強誘電体キャパシタを形成する工程を示す図である。図２ａにおいて、ＢＰＳＧ膜１２上に、白金のＰｔ下部電極１５がスパッターにより付着される。そして、３０００Å厚のＳＢＴ（ＳｒＢｉ2Ｔａ2Ｏ9）強誘電体薄膜４がスピンコート法により付着される。そして、白金のＰｔ上部電極１６がスパッターにより付着される。図２ｂにおいて、上部電極１６にマスクが付けられて、ＲＩＥ装置によりエッチングが行なわれる。次に、強誘電体薄膜４にマスクが付けられて、ＲＩＥ装置によりエッチングが行なわれる。そして、下部電極１５にマスクが付けられて、ＲＩＥ装置によりエッチングが行なわれる。
【００１２】
図２ｃにおいて、２００Åないし４００Å厚の薄い二酸化シリコンの第１の酸化膜８の堆積がキャパシタ構造の上にＴＥＯＳ（tetraethylorthosilicate）装置で行なわれる。その上に、スパッター装置で２００Åないし４００Å厚のＴｉ（チタン）薄膜９が堆積される。さらに、２００Åないし４００Å厚の二酸化シリコンの第２の酸化膜８’の堆積がＴＥＯＳ（tetraethylorthosilicate）装置で行なわれる。次に、図２ｄにおいて、上の第２の酸化膜８’のエッチングのためのレジストが付着されて、上の第２の酸化膜８’のウエットまたはドライ・エッチングが行なわれる。そして、レジストが剥離除去される。次に、Ｔｉ層９のエッチングが、硫酸と過酸化水素水の混合液またはアンモニア溶液と過酸化水素水の混合液を用いて行なわれる。
【００１３】
図２ｅにおいて、ＴＥＯＳ（tetraethylorthosilicate）装置により、ＢＰＳＧ（boron phosphorus silicate glass）の層間絶縁膜１２が堆積される。そしてコンタクトホールがＲＩＥ（リアクテイブ・イオン・エッチング）装置で、ＢＰＳＧの層間絶縁膜１２に形成される。そしてコンタクトホールにアルミニウム電極１３が形成される。そして、図２ｆに示されように、最終保護ＳｉＮ膜１４の堆積がプラズマＣＶＤにより行なわれる。そして、界面準位を下げるためのシンターリングか行なわれる。
【００１４】
図２ａから図２ｆの工程で製作された強誘電体キャパシタ構造は、強誘電体キャパシタの強誘電体薄膜４の少なくとも一部を、水素を吸蔵するＴｉ膜９と酸化膜８および８’で覆って保護し、さらに層間絶縁膜として水素の拡散係数が小さいＢＰＳＧ膜１２を設けることによって、シラン系ガスを用いた成膜や水素を用いたシンタリングなどの還元雰囲気中で熱処理を施しても、強誘電体薄膜が還元されず、強誘電体薄膜の劣化を抑えた強誘電体記憶素子ができる。
【００１５】
【発明の効果】
本発明による強誘電体記憶素子およびその製造方法では、強誘電体薄膜の少なくとも一部を、水素を吸蔵するＴｉ膜と酸化膜で覆って保護することにより、シラン系ガスを用いた成膜や水素を用いたシンタリングなどの還元雰囲気中で熱処理を施しても、強誘電体薄膜が還元されず、強誘電体薄膜の劣化を抑えた強誘電体記憶素子ができる。さらに層間絶縁膜として水素の拡散係数が小さいＢＰＳＧ膜を設ければ、その効果は、一層高まる。
【図面の簡単な説明】
【図１ａ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｂ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｃ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｄ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｅ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｆ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｇ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図１ｈ】 本発明の一実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図２ａ】 本発明の他の実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図２ｂ】 本発明の他の実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図２ｃ】 本発明の他の実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図２ｄ】 本発明の他の実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図２ｅ】 本発明の他の実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【図２ｆ】 本発明の他の実施の形態による強誘電体不揮発性記憶素子の製造工程の一部を示す工程図である。
【符号の説明】
１ シリコン半導体基板
２ 素子間分離酸化領域
３ 相互拡散防止絶縁膜
４ 強誘電体薄膜
５ Ｐｔ電極
６ Ｎ-ソース領域
７ Ｎ-ドレイン領域
８、８’ 酸化膜
９ Ｔｉ膜
１０ Ｎ+ソース領域
１１ Ｎ+ドレイン領域
１２ ＢＰＳＧ膜
１３ Ａｌ配線
１４ 最終保護膜
１５ Ｐｔ下部電極
１６ Ｐｔ上部電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric nonvolatile memory element and a manufacturing method thereof, and more particularly to a technique for suppressing deterioration of a ferroelectric thin film during a manufacturing process.
[0002]
[Prior art]
Ferroelectric nonvolatile memory elements include a type in which at least one transistor and one ferroelectric capacitor are connected, and a type in which a ferroelectric is used for the gate of a field effect transistor to control a source-drain current. There is. The former type is described, for example, in JP-A-2-113696. The latter type is described, for example, in JP-A-9-64206.
The former type is a structure in which a conventional DRAM capacitor is replaced with a ferroelectric, and is also called FRAM (Ferroelectric Random Access Memory). FRAM operates at a low voltage, and the number of rewrites is superior to conventional nonvolatile memories such as EEPROM (Electrically Erasable and Programmable Read Only Memory) and Flash Memory, and is expected as a next generation nonvolatile memory. The latter type is a structure in which a ferroelectric is used for a gate insulating film portion of a field effect transistor. From the laminated structure of the gate portion, an MF (I) S-FET (metal-ferroelectric material- (insulator- ) Semiconductor-Field Effect Transistor) or MFMIS-FET (Metal-Ferroelectric-Metal-Insulator-Semiconductor-Field Effect Transistor). This type has been proposed as a ferroelectric memory that is faster than the former FRAM and is advantageous for area reduction. The FRAM, MF (I) S-FET structure, and MFMIS-FET structure described above are memory elements using polarization of a ferroelectric thin film.
[0003]
[Problems to be solved by the invention]
However, as a ferroelectric, a ferroelectric having an ABO 3 type structure (A and B are metal elements, the same shall apply hereinafter), a ferroelectric having an A 2 B 2 O 7 type structure, or a layered perovskite structure. For example, PbTiO 3 , PbZrTiO 3 , PbLaZrTiO 3 , Bi 4 Ti 3 O 12 , Sr 2 Nb 2 O 7 , or Sr 2 (TaNb) 2 O 7 , or SrBi 2 Ta 2 O 9 is an oxidation compound, such as, usually, by heat treatment in a reducing atmosphere in the sintering process using a deposition process or hydrogen using a silane gas commonly used in semiconductor manufacturing device, the ferroelectric thin film There is a problem that the oxide is reduced to a metal, and thus the ferroelectric thin film deteriorates. The present invention has been made paying attention to the above-mentioned conventional unsolved problems, and has a structure in which a ferroelectric thin film is not deteriorated even in a reducing atmosphere in a semiconductor device manufacturing process. The purpose is to provide.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a ferroelectric memory element having a ferroelectric thin film has a structure in which at least a part of the ferroelectric thin film is covered with a stack of Ti (titanium) that stores hydrogen and an oxide film. A ferroelectric memory element having the same is provided.
[0005]
Furthermore, according to the present invention, in a ferroelectric memory element having a ferroelectric thin film, at least a part of the ferroelectric thin film is covered with a laminate of Ti (titanium) that stores hydrogen and an oxide film, Provided is a ferroelectric memory element having a structure in which a laminate of Ti (titanium) and an oxide film is further covered with an interlayer insulating film of BPSG (boron phosphorus silicate glass) having a small hydrogen diffusion coefficient. Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1a to 1h are diagrams showing manufacturing steps of an MFIS-FET according to an embodiment of the present invention. In FIG. 1a, an interdiffusion-preventing insulating film 3 of CeO 2 is formed by electron beam evaporation on the main surface of the P-type semiconductor substrate 1 where the isolation region 2 for element isolation is formed. On top of this, a ferroelectric thin film 4 of SBT (SrBi 2 Ta 2 O 9 ) was formed by spin coating. Further, a Pt (platinum) electrode 5 as a gate electrode was laminated by a Pt sputtering apparatus.
[0007]
In FIG. 1 b, the Pt (platinum) electrode layer 5, the SBT ferroelectric layer 4, and the CeO 2 interdiffusion prevention insulating film 3 are masked so as to leave only the gate structure portion by RIE (reactive ion etching). Removed. In FIG. 1c, N − ion implantation for forming the lightly doped source region 6 and the lightly doped drain region 7 was performed using the gate structure as a mask. An annealing process for activation and recovery was performed in an oxygen atmosphere at 700 ° C. for 60 minutes.
[0008]
In FIG. 1d, a thin silicon dioxide first oxide film 8 having a thickness of 200 to 400 mm is deposited on the gate structure with a TEOS (tetraethylorthosilicate) device. A Ti (titanium) thin film 9 having a thickness of 200 to 400 mm is deposited thereon by a sputtering apparatus. Further, the second oxide film 8 'of silicon dioxide having a thickness of 3000 mm is deposited by a TEOS (tetraethylorthosilicate) apparatus. Next, in FIG. 1e, the upper thick second oxide film 8 ′ and the Ti thin film 9 and the lower thin first oxide film 8 are etched back, leaving only side portions of the gate structure as side spaces. .
[0009]
Next, in FIG. 1f, the high-concentration source region 10 and the high-concentration drain are formed using a gate structure having a side space made of the second oxide film 8 ′, the Ti thin film 9 and the thin first oxide film 8 as a mask. In order to form the region 11, N + ion implantation was performed, and an annealing process at 900 ° C. for activation and recovery was performed. As shown in FIG. 1g, an interlayer insulating film 12 of BPSG (boron phosphorus silicate glass) is deposited by a TEOS (tetraethylorthosilicate) apparatus. A contact hole is formed in the BPSG interlayer insulating film 12 by an RIE (reactive ion etching) apparatus. An aluminum electrode 13 is formed in the contact hole. Then, as shown in FIG. 1h, the final protective SiN film 14 is deposited by plasma CVD. Then, sintering is performed to lower the interface state.
[0010]
In the ferroelectric gate structure manufactured in the steps of FIGS. 1a to 1h, the sides of the ferroelectric thin film 4 of the gate are covered with a Ti film 9 that absorbs hydrogen and oxide films 8 and 8 ′, and protected. Furthermore, by providing a BPSG film 12 with a small diffusion coefficient of hydrogen as an interlayer insulating film, a heat treatment is performed in a reducing atmosphere such as the formation of a final protective film using a silane-based gas or sintering using hydrogen. However, the ferroelectric thin film 4 is not reduced, and a ferroelectric memory element in which deterioration of the ferroelectric thin film 4 is suppressed can be obtained.
[0011]
2a to 2f are views showing a process of forming a ferroelectric capacitor for FRAM according to a second embodiment of the present invention. In FIG. 2a, a platinum Pt lower electrode 15 is deposited on the BPSG film 12 by sputtering. A 3000-thick SBT (SrBi 2 Ta 2 O 9 ) ferroelectric thin film 4 is deposited by spin coating. Then, a platinum Pt upper electrode 16 is deposited by sputtering. In FIG. 2b, the upper electrode 16 is masked and etched by an RIE apparatus. Next, a mask is attached to the ferroelectric thin film 4 and etching is performed by an RIE apparatus. Then, a mask is attached to the lower electrode 15 and etching is performed by an RIE apparatus.
[0012]
In FIG. 2c, a thin silicon dioxide first oxide film 8 having a thickness of 200 to 400 mm is deposited on the capacitor structure with a TEOS (tetraethylorthosilicate) device. A Ti (titanium) thin film 9 having a thickness of 200 to 400 mm is deposited thereon by a sputtering apparatus. Further, a second oxide film 8 'of silicon dioxide having a thickness of 200 to 400 mm is deposited by a TEOS (tetraethylorthosilicate) apparatus. Next, in FIG. 2d, a resist for etching the upper second oxide film 8 'is deposited, and wet or dry etching of the upper second oxide film 8' is performed. Then, the resist is peeled and removed. Next, etching of the Ti layer 9 is performed using a mixed solution of sulfuric acid and hydrogen peroxide solution or a mixed solution of ammonia solution and hydrogen peroxide solution.
[0013]
In FIG. 2e, an interlayer insulating film 12 of BPSG (boron phosphorus silicate glass) is deposited by a TEOS (tetraethylorthosilicate) apparatus. Then, contact holes are formed in the interlayer insulating film 12 of BPSG by an RIE (reactive ion etching) apparatus. An aluminum electrode 13 is formed in the contact hole. Then, as shown in FIG. 2f, the final protective SiN film 14 is deposited by plasma CVD. Then, sintering is performed to lower the interface state.
[0014]
In the ferroelectric capacitor structure manufactured by the steps of FIGS. 2a to 2f, at least a part of the ferroelectric thin film 4 of the ferroelectric capacitor is covered with a Ti film 9 for absorbing hydrogen and oxide films 8 and 8 ′. By providing the BPSG film 12 with a small diffusion coefficient of hydrogen as an interlayer insulating film, even if heat treatment is performed in a reducing atmosphere such as film formation using a silane-based gas or sintering using hydrogen, A ferroelectric memory element in which deterioration of the ferroelectric thin film is suppressed can be obtained without reducing the ferroelectric thin film.
[0015]
【The invention's effect】
In the ferroelectric memory element and the method of manufacturing the same according to the present invention, at least a part of the ferroelectric thin film is covered with a Ti film and an oxide film that occludes hydrogen to protect the film. Even if heat treatment is performed in a reducing atmosphere such as sintering using hydrogen, the ferroelectric thin film is not reduced, and a ferroelectric memory element in which deterioration of the ferroelectric thin film is suppressed can be obtained. Further, if a BPSG film having a small hydrogen diffusion coefficient is provided as an interlayer insulating film, the effect is further enhanced.
[Brief description of the drawings]
FIG. 1a is a process diagram showing a part of a manufacturing process of a ferroelectric nonvolatile memory element according to an embodiment of the present invention;
FIG. 1B is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to an embodiment of the present invention.
FIG. 1c is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to an embodiment of the present invention.
FIG. 1D is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to an embodiment of the present invention.
FIG. 1e is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to an embodiment of the present invention.
FIG. 1f is a process diagram showing a part of a process for manufacturing a ferroelectric nonvolatile memory element according to an embodiment of the present invention;
FIG. 1g is a process diagram showing a part of a manufacturing process of a ferroelectric nonvolatile memory element according to an embodiment of the present invention.
FIG. 1h is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to an embodiment of the present invention.
FIG. 2a is a process diagram showing a part of a manufacturing process of a ferroelectric nonvolatile memory element according to another embodiment of the present invention.
FIG. 2B is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to another embodiment of the present invention.
FIG. 2C is a process diagram showing a part of a process for manufacturing a ferroelectric nonvolatile memory element according to another embodiment of the present invention.
FIG. 2D is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to another embodiment of the present invention.
FIG. 2E is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to another embodiment of the present invention.
FIG. 2f is a process diagram showing a part of a process of manufacturing a ferroelectric nonvolatile memory element according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Interelement isolation oxidation region 3 Interdiffusion prevention insulating film 4 Ferroelectric thin film 5 Pt electrode 6 N − source region 7 N − drain region 8, 8 ′ oxide film 9 Ti film 10 N + source region 11 N + Drain region 12 BPSG film 13 Al wiring 14 final protective film 15 Pt lower electrode 16 Pt upper electrode

Claims (6)

半導体基板と強誘電体薄膜を有する強誘電体記憶素子であって、水素を吸蔵するＴｉ膜を第１の酸化膜と第２の酸化膜で挟んだ積層構造で前記強誘電体薄膜の少なくとも側部を直接覆うことを特徴とする強誘電体記憶素子。A ferroelectric memory element having a semiconductor substrate and a ferroelectric thin film, wherein the Ti film storing hydrogen is sandwiched between a first oxide film and a second oxide film, and is at least on the ferroelectric thin film A ferroelectric memory element characterized by directly covering a portion . ゲート電極を有し、このゲート電極が前記強誘電体薄膜上に積層された強誘電体ゲート構成を有する前記強誘電体記憶素子であって、前記第１の酸化膜と前記Ｔｉ膜と前記第２の酸化膜とからなる積層構造で前記強誘電体薄膜の側部を直接覆うことを特徴とする請求項１記載の強誘電体記憶素子。A ferroelectric memory element having a ferroelectric gate structure in which the gate electrode is stacked on the ferroelectric thin film, the first oxide film, the Ti film, and the first electrode ; 2. The ferroelectric memory element according to claim 1, wherein the ferroelectric thin film is directly covered with a laminated structure comprising two oxide films. 上部電極と下部電極とを有し、前記強誘電体薄膜を前記上部電極と前記下部電極で挟んだ強誘電体キャパシタを有する前記強誘電体記憶素子であって、前記第１の酸化膜と前記Ｔｉ膜と前記第２の酸化膜からなる積層構造で前記強誘電体薄膜の側部を直接覆うことを特徴とする請求項１記載の強誘電体記憶素子。The ferroelectric memory element having an upper electrode and a lower electrode, and having a ferroelectric capacitor sandwiching the ferroelectric thin film between the upper electrode and the lower electrode, wherein the first oxide film and the 2. The ferroelectric memory element according to claim 1, wherein a side surface of the ferroelectric thin film is directly covered with a laminated structure including a Ti film and the second oxide film. ＢＰＳＧの層間絶縁膜を有することを特徴とする請求項１ないし３項記載の強誘電体記憶素子。A ferroelectric memory device of claims 1 to 3 Claims characterized by having a BPSG interlayer insulating film. 半導体基板上に強誘電体薄膜を形成する工程と、
前記強誘電体薄膜上に上部電極となる導電体層を形成する工程と、
前記強誘電体薄膜及び前記導電体層を所定の電極パターンにパターニングする工程と、
前記電極パターンを直接覆う第１の酸化膜、Ｔｉ膜および第２の酸化膜をこの順序で積層形成する工程と、
前記第１および第２の酸化膜及びＴｉ膜の形成の後、シラン系ガスを用いた成膜を行う行程、または水素を用いたシンタリングの還元雰囲気を用いた熱処理を行う工程と
を備えることを特徴とする強誘電体記憶素子の製造方法。Forming a ferroelectric thin film on a semiconductor substrate;
Forming a conductor layer to be an upper electrode on the ferroelectric thin film;
Patterning the ferroelectric thin film and the conductor layer into a predetermined electrode pattern;
Laminating a first oxide film, a Ti film and a second oxide film directly covering the electrode pattern in this order;
After the first and second oxide films and the Ti film are formed, a step of forming a film using a silane-based gas or a step of performing a heat treatment using a reducing atmosphere of sintering using hydrogen is provided. A method for manufacturing a ferroelectric memory element. 前記半導体基板上にＢＰＳＧ膜を形成する工程を備えることを特徴とする請求項５記載の強誘電体記憶素子の製造方法。6. The method of manufacturing a ferroelectric memory element according to claim 5, further comprising a step of forming a BPSG film on the semiconductor substrate.
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JPH0997883A (en) * 1995-09-29 1997-04-08 Sony Corp Capacitor structure of semiconductor memory element and manufacture thereof
JPH1197635A (en) * 1997-09-16 1999-04-09 Matsushita Electron Corp Capacity element and its manufacturing method
JPH1197632A (en) * 1997-07-24 1999-04-09 Matsushita Electron Corp Semiconductor device and manufacture thereof
JP2001196551A (en) * 1999-12-30 2001-07-19 Hyundai Electronics Ind Co Ltd Semiconductor element with capacitor and manufacturing method therefor

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JPH0997883A (en) * 1995-09-29 1997-04-08 Sony Corp Capacitor structure of semiconductor memory element and manufacture thereof
JPH1197632A (en) * 1997-07-24 1999-04-09 Matsushita Electron Corp Semiconductor device and manufacture thereof
JPH1197635A (en) * 1997-09-16 1999-04-09 Matsushita Electron Corp Capacity element and its manufacturing method
JP2001196551A (en) * 1999-12-30 2001-07-19 Hyundai Electronics Ind Co Ltd Semiconductor element with capacitor and manufacturing method therefor

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