JP4484899B2 - Magnetic memory device and data reading method in magnetic memory device - Google Patents

Description

  In the present invention, a plurality of magnetic memory cells having a structure in which a plurality of magnetic layers separated by a nonmagnetic layer are stacked are arranged in a matrix, and data (information) is stored using the magnetoresistive effect of these magnetic memory cells. The present invention relates to a magnetic memory device that performs writing or reading, and a data reading method in the magnetic memory.

  In recent years, magnetic memory devices such as those described above have attracted attention as nonvolatile high-density memory elements. Each of the plurality of magnetic memory cells constituting the main part of the magnetic memory device generally includes a plurality of magnetic layers, for example, two ferromagnetic layers made of a ferromagnetic thin film separated by a nonmagnetic layer. It is formed by laminating in a state where This magnetic memory device writes data to a memory cell at an arbitrary position (address) and reads data from the memory cell, similarly to a DRAM (dynamic random access memory) having a plurality of memory cells. It has a function and is also called MRAM (magnetic random access memory).

  More specifically, depending on whether the magnetic moment directions of the two ferromagnetic layers included in the magnetic memory cell are parallel or antiparallel, the resistance value of the magnetic memory cell varies depending on the magnetoresistive effect. come. Corresponding to the magnitude of the resistance value, data of “0” or “1” is stored in the magnetic memory cell.

  Data is written to the magnetic memory cell by passing a current through a current line (for example, a word line and a bit line) provided near the ferromagnetic layer, and the two ferromagnetic layers by the magnetic field (magnetic field) generated by the current. This is performed by controlling the reversal or non-reversal of the direction of one of the magnetic moments. On the other hand, when reading data from the magnetic memory cell, the resistance value of the magnetic memory cell when the directions of the magnetic moments of the two ferromagnetic layers are parallel to each other is more than the resistance value when the magnetic memory cells are antiparallel to each other. Take advantage of getting smaller. In other words, data is read by detecting the relative resistance value of the magnetic memory cell by passing a weak current in the horizontal direction or a weak current in the vertical direction to the two ferromagnetic layers. The detection result is amplified by a sense amplifier, and data “0” or “1” is determined.

  Here, with reference to FIG. 19 to FIG. 21, an operation principle of a magnetic memory cell generally used and a conventional example of a magnetic memory device in which a plurality of magnetic memory cells are arranged will be described.

  FIG. 19 is a schematic diagram showing the operation principle of a magnetic memory cell using a general magnetoresistive effect, FIG. 20 is a perspective view showing the configuration of a conventional magnetic memory device of the first example, and FIG. It is a perspective view which shows the structure of the magnetic memory device of the 2nd example. However, FIGS. 20 and 21 illustrate the configuration of the main part of the magnetic memory device.

19A to 19C, a data write operation is performed on a magnetic memory cell 200 having a configuration in which two ferromagnetic layers made of a ferromagnetic thin film are separated by a nonmagnetic layer. The sequence for doing is shown. In general, a thin film of ferromagnetic material, cobalt is prepared by adding a small amount has been Permalloy (usually expressed as Ni-Fe / Co), the nonmagnetic layer is made of aluminum oxide (usually expressed as Al ₂ O ₃₎ The The magnetic memory cell 200 including two ferromagnetic layers and a nonmagnetic layer is formed on the lower first magnetic layer 201 in the two ferromagnetic layers, with the nonmagnetic layer 203 interposed therebetween. The magnetic layer 202 is laminated.

  As shown in FIGS. 19D and 19E, depending on whether the directions of the magnetic moments of the first magnetic layer 201 and the second magnetic layer 202 are parallel or antiparallel to each other. A difference occurs in the magnetoresistive effect due to the magnetic interaction between the first magnetic layer 201 and the second magnetic layer 202, and thus the resistance value of the magnetic memory cell 200 is different. More specifically, when the directions of the magnetic moments of the first magnetic layer 201 and the second magnetic layer 202 are parallel to each other (FIG. 19D), the resistance values are anti-parallel to each other ( It becomes smaller than the resistance value of (e) of FIG. Corresponding to the magnitude of the resistance value, data of “0” or “1” is stored in the magnetic memory cell.

  Here, as shown in FIG. 19A, before data is written to the magnetic memory cell 200, the directions of the magnetic moments of the first magnetic layer 201 and the second magnetic layer 202 are parallel to each other. For example, a state in which data “0” is stored is assumed. As shown in FIG. 19B, the writing of “1” data to the magnetic memory cell 200 in such a state is performed by using a current line (for example, a word line and a line provided near the second magnetic layer 202). This is performed by passing a current through the bit line 204 and reversing the direction of the magnetic moment of the second magnetic layer 202 by the magnetic field B generated by this current. After that, as shown in FIG. 19C, even when the current of the current line 204 is set to zero and the magnetic field B is removed, the state of the magnetic moment of the second magnetic layer 202 is reversed. 1 ″ data is stored in the magnetic memory cell. In this case, the magnetic moment of the second magnetic layer 202 is changed by changing the component ratio of each element (iron, nickel, cobalt, etc.) of the magnetic material of the first magnetic layer 201 and the second magnetic layer 202. Inversion is performed with a magnetic field smaller than that of one magnetic layer 201. In this way, it is possible to easily reverse only the magnetic moment of the upper second magnetic layer 202 without affecting the magnetic moment of the lower first magnetic layer 201.

  On the other hand, when data stored in the magnetic memory cell 200 is read, the magnetic memory cell 200 is supplied from the power source Vd through the current line 204 as shown in FIGS. By supplying a weak current, the resistance value of the magnetic memory cell 200 when the directions of the magnetic moments of the first magnetic layer 201 and the second magnetic layer 202 are parallel to each other and the case where they are antiparallel to each other A difference from the resistance value is detected to determine data of “0” or “1”.

  In the conventional spin-valve type ferromagnetic memory device 100 shown in FIG. 20, data is read by passing a current in the horizontal direction through the two ferromagnetic layers in the magnetic memory cell 200 as described above. Is going. In this case, the relative resistance value generated by the giant magnetoresistive effect (generally abbreviated as GMR) of the two ferromagnetic layers is detected. On the other hand, in the conventional tunnel junction type ferromagnetic memory device 101 shown in FIG. 21, a current is passed in the perpendicular direction to the two ferromagnetic layers in the magnetic memory cell 200 as described above. Reading data. In this case, the relative resistance value generated by the tunneling magnetoresistive effect (usually abbreviated as TMR) of the two ferromagnetic layers is detected.

  More specifically, in each of the conventional magnetic memory devices of the first example and the second example, a plurality of magnetic memory cells 200 as described above are prepared, and a plurality of word lines (here, only w0 and w1) are prepared. The magnetic memory cells are arranged in a matrix along intersections of a plurality of bit lines (here, only b0, b1, and b2 are shown) intersecting these word lines.

  In the conventional spin valve type ferromagnetic memory device 100 of FIG. 20, the magnetic memory cells arranged corresponding to the intersections of the word lines w0, w1 and the bit lines b0, b1, and b2 are respectively MS11, Defined as MS12, MS13, MS21, MS22 and MS23. Current guide portions 205 are formed at both ends of each of the magnetic memory cells MS11 to MS23. When reading data from a magnetic memory cell that is a target of data reading, a word line and a bit line at a position corresponding to the magnetic memory cell are selected. Further, these word lines and bit lines are set to a predetermined potential, and a current I is passed in the horizontal direction to the ferromagnetic layer in the magnetic memory cell via the current guide unit 205. Further, the current flowing out of the magnetic memory cell is amplified by a sense amplifier or the like and compared with a reference current, thereby detecting the relative resistance value of the magnetic memory cell and determining data of “0” or “1”. .

  On the other hand, in the conventional tunnel junction type ferromagnetic memory device 101 of FIG. 21, the magnetic memory cells arranged corresponding to the intersections of the word lines w0 and w1 and the bit lines b0, b1 and b2, respectively. Are defined as MT11, MT12, MT13, MT21, MT22, and MT23. Here, unlike the conventional first example described above, word lines and bit lines are directly joined to the lower and upper layers of the magnetic memory cells MT11 to MT23, respectively. When reading data from a magnetic memory cell that is a target of data reading, a word line and a bit line at a position corresponding to the magnetic memory cell are selected. Further, these word lines and bit lines are set to a predetermined potential, and a current I is passed in a direction perpendicular to the ferromagnetic layer in the magnetic memory cell. Further, the current flowing out of the magnetic memory cell is amplified by a sense amplifier or the like and compared with a reference current, thereby detecting the relative resistance value of the magnetic memory cell and determining data of “0” or “1”. .

  As described above, in a conventional magnetic memory device having a magnetic memory cell having a structure in which two ferromagnetic layers are stacked, data “0” or “1” is detected by detecting a current flowing out of the magnetic memory cell. I am trying to read it out.

  However, in such a conventional magnetic memory device, only binary (2-bit) data of “0” or “1” can be stored in each magnetic memory cell. Therefore, when it is required to provide a memory element having a higher storage density or a multifunctional memory element as the capacity of a computer system increases, it becomes difficult to meet such a demand. Inconvenience arises.

  On the other hand, in the magnetic memory device as described above, data is written to the magnetic memory cell by passing current through the word line and bit line, or data is detected by detecting the current flowing out from the selected magnetic memory cell. Is read out, causing a disadvantage that the power consumption of the entire magnetic memory device becomes relatively large.

  The present invention has been made in view of the above problems, and realizes a magnetic memory cell and a multifunctional magnetic memory cell having a higher storage density than conventional ones, and can reduce power consumption. And a method for reading data in the magnetic memory device.

  In order to solve the above problems, a magnetic memory device of the present invention includes a magnetic memory cell in which at least three magnetic layers including a first magnetic layer, a second magnetic layer, and a third magnetic layer are stacked. The magnetic memory cell has a resistance value that differs depending on the direction of the magnetic moment of the first, second, and third magnetic layers, and the plurality of magnetic memory cells are connected to the plurality of first lines and The first line, the second line, and the second line are arranged along intersections of a plurality of second lines intersecting the first line, and a predetermined current is selectively passed through the first line and the second line. Data is written to a specific magnetic memory cell by controlling the direction of the magnetic moment of the third magnetic layer.

  In such a configuration, each of the first lines is composed of at least two word lines, and each of the word lines is a magnetic moment of any one of the first, second, and third magnetic layers. By individually controlling the direction, the binary data or more is stored in the specific magnetic memory cell.

  Preferably, in the magnetic memory device of the present invention, each of the first lines is composed of two word lines, and the two word lines are provided in an upper layer portion and a lower layer portion of each of the magnetic memory cells, respectively. The upper layer word line controls the direction of the magnetic moment of the magnetic layer formed in the upper layer part, and the lower word line is the direction of the magnetic moment of the magnetic layer formed in the lower layer part. Is to control.

  Further preferably, in the magnetic memory device according to the present invention, each of the second lines includes two bit lines, and the two bit lines include upper and lower portions of each of the magnetic memory cells. The upper word line and the upper bit line control the direction of the magnetic moment of the magnetic layer formed on the upper layer, and the lower word line and the lower bit. The line stores multi-value data by controlling the direction of the magnetic moment of the magnetic layer formed in the lower layer.

  Furthermore, it is preferable that the magnetic memory device of the present invention detects the difference between the resistance values of the magnetic memory cells selected by the first line and the second line to read data when the data is read out. Of the two word lines constituting the first line, the magnetic layer of the magnetic memory cell in which one word line located on the side that does not affect the current flowing through the second line is disposed. The direction of the magnetic moment is configured to be controlled for each of the one word lines.

  In the magnetic memory device configured as described above, a data reading method for reading data by detecting a difference in resistance value of the magnetic memory cell selected by the first line and the second line is as follows. Controlling the direction of the magnetic moment of the magnetic layer of the magnetic memory cell on which one word line located on the side not affecting the current flowing through the second line is arranged for each one word line; The direction of the magnetic moment of the magnetic layer is made to correspond to the selection or non-selection of the magnetic memory cell by the first line.

  In the magnetic memory device and the data reading method as described above, the magnetic layer on the side where one word line is arranged has a function equivalent to that of a separation diode or a separation transistor for separating a plurality of magnetic memory cells from each other. Therefore, the separation diode or the separation transistor can be made unnecessary.

  On the other hand, the magnetic memory device of the present invention forms a magnetic memory cell by laminating a plurality of magnetic layers, and this magnetic memory cell has a resistance value that varies depending on the direction of the magnetic moment of the plurality of magnetic layers. The plurality of magnetic memory cells are arranged along the intersections of the plurality of first lines and the plurality of second lines intersecting the first line, and the capacitance value of each of the magnetic memory cells is substantially the same. A voltage reading means such as a capacitor having the same capacitance value is connected in series to each of the magnetic memory cells. In such a configuration, a voltage obtained by measuring the potential of the contact point between the one end of the magnetic memory cell selected by the first line and the second line and the voltage reading means at a predetermined timing. By determining the level, the data of the magnetic memory cell is read out.

  In the magnetic memory device configured as described above, a data reading method for reading data by detecting a difference in resistance value of the magnetic memory cell selected by the first line and the second line is as follows. A voltage reading means having a capacitance value substantially the same as the capacitance value of each of the magnetic memory cells is connected in series to each of the magnetic memory cells, and is selected by the first line and the second line. The voltage level obtained by measuring the potential of the contact point between one end of the magnetic memory cell and the voltage reading means at a predetermined timing is determined.

  In summary, according to the present invention, in a magnetic memory cell having a structure in which at least three magnetic layers are stacked, the direction of the magnetic moment of any one of at least three magnetic layers using at least two word lines or the like. By individually controlling the memory, data of two or more values is stored in a specific magnetic memory cell, so that it is possible to realize a magnetic memory cell having a higher storage density or a multifunctional magnetic memory cell than before. become.

  Furthermore, in the present invention, voltage reading means such as a capacitor is connected in series to a magnetic memory cell having a structure in which a plurality of magnetic layers are stacked, and the voltage level obtained by charging the voltage reading means is determined. Thus, the data of the magnetic memory cell is read out, so that the power consumption can be kept lower than before.

  The configuration and operation of a preferred embodiment of the present invention will be described below with reference to the accompanying drawings (FIGS. 1 to 18).

  FIG. 1 is a perspective view showing the main part of the first embodiment of the present invention. However, here, the configuration of the main part of the magnetic memory device according to the first embodiment of the present invention is shown in a simplified manner. Hereinafter, the same components as those described above are denoted by the same reference numerals.

A magnetic memory device 1 according to the first embodiment of FIG. 1 includes a three-layer structure including a first magnetic layer 21 in a lower layer portion, a second magnetic layer 22 in an intermediate layer portion, and a third magnetic layer 23 in an upper layer portion. A three-layer magnetic memory cell 2 having a structure in which the magnetic layers are stacked is provided. A first nonmagnetic layer 24 is formed between the first magnetic layer 21 and the second magnetic layer 22 in the magnetic memory cell in order to electrically and magnetically separate these magnetic layers. Is done. Further, a second nonmagnetic layer 25 is formed between the second magnetic layer 22 and the third magnetic layer 23. Preferably, the ferromagnetic thin film made of the first to third magnetic layers is made of permalloy (Ni—Fe / Co) to which a small amount of cobalt is added, and is made of the first and second nonmagnetic layers. The magnetic thin film is made of aluminum oxide (Al ₂ O ₃ ).

  In general, a tunnel junction type ferromagnetic memory device (see FIG. 21) that reads data by flowing a current in a direction perpendicular to a ferromagnetic layer in a magnetic memory cell is horizontal to the ferromagnetic layer in the magnetic memory cell. Compared with a spin-valve type ferromagnetic memory device (see FIG. 20) that reads data by flowing a current in the direction, the change in resistance value for “0” or “1” data is large, and the sensitivity at the time of data reading is high. It is good. Therefore, in the first embodiment of FIG. 1, a tunnel junction type ferromagnetic memory device is used as the magnetic memory device 1.

  In the first embodiment of FIG. 1, a plurality of magnetic memory cells 2 having the above structure are prepared, and a plurality of word lines (only w0 and w1 are shown here) and a plurality of control word lines ( Here, only w0 'and w1' are shown), and a plurality of bit lines intersecting with these two types of word lines w0, w1, w0 'and w1' (here, only b0, b1 and b2 are shown) A plurality of magnetic memory cells are arranged in a matrix along the intersections. More specifically, a plurality of word lines w0 and w1 are provided in the lower layer portion of the magnetic memory cell, and a plurality of control word lines w0 ′ and w1 ′ are provided in the upper layer portion of the magnetic memory cell. Here, three-layer magnetic memory cells arranged corresponding to the intersections of the word lines w0, w1 (or control word lines w0 ′, w1 ′) and the bit lines b0, b1, and b2, respectively, are denoted by MC11, MC12, It is defined as MC13, MC21, MC22, and MC23. Furthermore, the first line according to the magnetic memory device of the present invention is composed of a plurality of word lines w0, w1 and control word lines w0 ′, w1 ′, and the second line is composed of a plurality of bit lines b0, It is comprised by b1 and b2.

  Further, in the first embodiment of FIG. 1, the word lines w0 and w1 are formed in the lower layer portion of the three-layer type magnetic memory cell by causing a predetermined current to flow and generating a magnetic field. The direction of the magnetic moment of the magnetic layer 21 is controlled. On the other hand, the control word lines w0 'and w1' also generate a magnetic field by flowing a predetermined current, thereby causing the third magnetic layer 23 formed in the upper layer portion of the three-layer type magnetic memory cell. Control the direction of the magnetic moment. Further, when data is written to a specific three-layer magnetic memory cell, one of the control word lines w0 'and w1' is selected, and the control word lines w0 'and w1' are crossed and adjacent to each other. One of the provided bit lines b0, b1, and b2 is selected. Further, by simultaneously applying a predetermined current to the control word line and the bit line thus selected to generate a combined magnetic field, the control word line and the bit line are positioned at the intersection of the selected control word line and the bit line. The direction of the magnetic moment of the third magnetic layer 23 formed in the upper layer portion of the three-layer type magnetic memory cell is controlled.

  Further, the magnetic moment of the second magnetic layer 22 formed in the middle layer portion is increased by a relatively large current using either the upper control word line or the lower word line or both. By generating a magnetic field, it can be directed in a certain direction. It is not necessary to apply a strong magnetic field every time as long as the second magnetic layer 22 is once magnetized to determine the direction of the magnetic moment. In this case, the first magnetic layer 21 and the third magnetic layer 23 are changed by changing the component ratio of each element of the magnetic material of the first magnetic layer 21 and the third magnetic layer 23 and the second magnetic layer 22. Is reversed with a magnetic field smaller than that of the second magnetic layer 22. In this way, without affecting the magnetic moment of the second magnetic layer 22 in the middle layer portion, the magnetic moment of the first magnetic layer 21 in the lower layer portion and the magnetic moment of the third magnetic layer 23 in the upper layer portion. The moment can be reversed independently.

  FIG. 2 is a circuit diagram showing an equivalent circuit of the magnetic memory device of FIG. 1, and FIG. 3 is a schematic diagram showing the relationship between the direction of the magnetic moment and the resistance value of the magnetic layer of FIG. As shown in FIG. 2, according to the direction of the magnetic moment of the first, second, and third magnetic layers formed in each of the three-layer type magnetic memory cells MC11, MC21, MC12, and MC22, The portion including three magnetic layers 23 has two resistance values R0 and R1 (R0 <R1), and the portion including the first magnetic layer 21 in the lower layer has resistance values R2 and R3 ( It has a binary resistance value of R2 <R3). Here, since the upper third magnetic layer 23 is adjacent to both the control word lines w0 'and w1' and the bit lines b0, b1 and b2, the selected control word line and the selected bit are selected. It is possible to reverse the direction of the magnetic moment of the specific third magnetic layer 23 located at the intersection with the line. On the other hand, the first magnetic layer 21 in the lower layer is adjacent to only the word lines w0 and w1, and is not affected by the current flowing through the bit lines b0, b1 and b2. Therefore, the direction of the magnetic moment of the lower first magnetic layer 21 is controlled for each word line.

  In general, when data stored in a three-layer magnetic memory cell is read, the selected control word line is set to a low potential, and the selected bit line is set to a high potential to form a three-layer type. By supplying a weak current to the magnetic memory cell, a change in resistance value with respect to data of “0” or “1” is detected. At this time, in order to prevent a plurality of three-layer magnetic memory cells from being selected simultaneously, a plurality of three-layer magnetic memory cells are separated from each other in series with each three-layer magnetic memory cell. It is necessary to provide a separation diode or a separation transistor. Here, instead of the isolation diode or the isolation transistor, a transfer gate including a plurality of switching transistors may be provided. Details of the isolation diode or isolation transistor will be described later with reference to FIGS.

  In FIG. 2, the resistance value of the first magnetic layer in the lower layer portion of the magnetic memory cell arranged along the word line w0 selected at the time of data reading is lowered (set to R2), and the word line that is not selected. The resistance value of the first magnetic layer in the lower layer portion of the magnetic memory cell arranged along w1 is increased (set to R3). This makes it possible to perform the same function as the above-described isolation diode (or isolation transistor).

  Preferably, in the magnetic memory device configured as shown in FIGS. 1 and 2, data is read by detecting a difference in resistance value of the magnetic memory cell selected by the control word line (or word line) and the bit line. In this case, the direction of the magnetic moment of the magnetic layer (for example, the first magnetic layer in the lower layer) of the magnetic memory cell in which the word line located on the side not affecting the current flowing through the bit line is arranged A data reading method is executed in which the control is performed for each line and the direction of the magnetic moment of the magnetic layer is made to correspond to selection or non-selection of the magnetic memory cell by the word line.

  FIG. 3 shows the relationship between the direction of the magnetic moment and the resistance value of each of the first to third magnetic layers 21 to 23 of the three-layer type magnetic memory cell. As is apparent from FIG. 3, when the directions of the magnetic moments of the second magnetic layer 22 and the third magnetic layer 23 are parallel to each other, the resistance value including the portion of the third magnetic layer 23 is R0. When they are antiparallel to each other, the resistance value is R1. As described above, the resistance value R0 is smaller than the resistance value R1 (R0 <R1). On the other hand, when the directions of the magnetic moments of the first magnetic layer 21 and the second magnetic layer 22 are parallel to each other, the resistance value including the portion of the first magnetic layer 21 is R2, which is antiparallel to each other. In this case, the resistance value is R3. As described above, the resistance value R2 is smaller than the resistance value R3 (R2 <R3). Accordingly, the resistance value when a current is passed in the direction perpendicular to the first to third magnetic layers 21 to 23 is the first to third magnetic layers as shown in FIGS. R0 + R2, R1 + R2, R0 + R3, and R1 + R3, respectively, depending on the direction of the magnetic moment of the layers 21-23. As will be described later, by selecting appropriate resistance values R0 to R3, the relationship between the magnitudes of these resistance values is set as (R0 + R2) <(R1 + R2) <(R0 + R3) <(R1 + R3). can do.

  As described above, the resistance values R0 and R1 are determined by the direction of the magnetic moment of the third magnetic layer 23 of the magnetic memory cell located at the intersection of the selected control word line and the selected bit line. Therefore, as shown in FIGS. 3A and 3B, the resistance values R0 and R1 can be made to correspond to “0” or “1” of data, respectively. On the other hand, the resistance values R2 and R3 are determined according to selection or non-selection of the word line. Therefore, as shown in FIGS. 3C and 3D, the resistance values R2 and R3 can be made to correspond to selection or non-selection of the word line, respectively. In other words, FIG. 3A shows “0” data when the word line is selected, and FIG. 3B shows “1” when the word line is selected. Represents the data. Further, FIG. 3C shows data “0” when the word line is not selected (unselected 0), and FIG. 3D shows “when the word line is not selected”. 1 "data (non-selection 1).

  Here, when the directions of the magnetic moments of the two ferromagnetic layers change from a parallel relationship to an antiparallel relationship (or vice versa), the change in resistance value is about 30%. Therefore, for example, the resistance values R0 and R1 including the third magnetic layer portion of the upper layer portion are selected as the following values, respectively.

R0 = 1kΩ (kiloohm)
R1 = 1.3kΩ (R1 = R0 + R0 × 0.3)
On the other hand, R0 + R1, R1 + R2, R0 + R3, and R1 + R3 all need to have different resistance values. Further, the resistance values R2 and R3 including the first magnetic layer portion of the lower layer are selected as follows so that the respective resistance values are equally spaced.

R2 = 2kΩ
R3 = 2.6 kΩ (R3 = R2 + R2 × 0.3)
At this time, the resistance value of the magnetic memory cell selected at the time of data reading is R0 + R1 = 3 kΩ (1 kΩ + 2 kΩ), R1 + R2 = 3.3 kΩ (1.3 kΩ + 2 kΩ), and is 3 kΩ to 3.3 kΩ. On the other hand, the resistance values of the unselected magnetic memory cells are R0 + R3 = 3.6 kΩ (1 kΩ + 2.6 kΩ), R1 + R3 = 3.9 kΩ (1.3 kΩ + 2.6 kΩ), and 3.6 kΩ to 3.9 kΩ. . In short, R0 + R1, R1 + R2, R0 + R3, and R1 + R3 are set to be equidistant from 0.3 kΩ.

  More specifically, “0” data is preferably set to a resistance value of 3.15 kΩ or less, and “1” data is preferably set to a resistance value of 3.15 kΩ or more and 3.45 kΩ or less.

  FIG. 4 is a front view showing an example of a magnetic memory cell used in the embodiment of the present invention. However, here, the portion of the intersection between the magnetic memory cell 2 of FIG. 1 and a word line (for example, the word line w0) is shown enlarged.

  In FIG. 4, the first magnetic layer 21 in the lower layer portion of the magnetic memory cell 2 is slightly embedded in the word line w0. In such a configuration, when a current is passed through the word line w0 to reverse the direction of the magnetic moment of the first magnetic layer 21, the magnetic field generated by this current can be concentrated on the first magnetic layer 21. . As a result, magnetic flux leakage to the other magnetic layer can be minimized, and by concentrating the magnetic field generated by this current on the first magnetic layer 21, the leakage of magnetic flux to the other magnetic layer. Can be minimized.

  FIG. 5 is a block diagram showing the overall structure of the magnetic memory device according to the embodiment of the present invention, and FIG. 6 is a circuit diagram showing an example of the sense amplifier unit of FIG.

  In the magnetic memory device shown in FIG. 5, as in the configuration shown in FIG. 1, a plurality of word lines (w0, w1, and w2), a plurality of control word lines (w0 ′, w1 ′), and these A configuration is disclosed in which a plurality of three-layer magnetic memory cells MC11 to MC22 are arranged in a matrix along intersections with a plurality of bit lines (b0, b1 and b2) intersecting with the word lines and the control word lines. Yes. However, here, in order to prevent a plurality of three-layered magnetic memory cells from being selected simultaneously when data is read, three-layered magnetic memory cells MC11, MC12, MC21 and MC22 are connected in series with each other. Isolation diodes D11, D12, D21, and D22 are provided for isolating the layer type magnetic memory cells from each other.

  Further, the magnetic memory device of FIG. 5 generates a control circuit for generating various control signals for enabling a data write operation and a read operation to the three-layer magnetic memory cell based on an external control signal Sc. Part 3 is provided. These control signals include a write control signal for controlling the data write operation to the selected three-layer magnetic memory cell, and a data read operation for the selected three-layer magnetic memory cell. A read control signal, a chip select signal for selecting an address of the read data, and the like are included. Further, the magnetic memory device of FIG. 2 includes a write control unit 4 for writing data by supplying a predetermined current to a word line (or control word line) and a bit line selected by a write control signal, and read control. And a sense amplifier section 5 for amplifying a current flowing out from the three-layer magnetic memory cell by setting a word line and a bit line selected by a signal to a low potential and a high potential, respectively. A signal indicating “0” or “1” data detected by the sense amplifier unit 5 is input to the data select unit 7 and finally confirmed to be correct data using the data select signal Ss. , And output as a data signal DATA.

  Further, the magnetic memory device of FIG. 5 includes an address decoder 5 that decodes external address input signals A0 to Ak (k is an arbitrary positive integer of 2 or more). The address decoder 7 sets the bit line selected in accordance with the decoded address signal to a high potential, and causes the current to flow toward the low potential word line selected by the write control unit 4, thereby corresponding 3 Data can be written to or read from the layered magnetic memory cell.

  As shown in FIG. 6, the sense amplifier unit 5 includes a single or a plurality of sense amplifiers 16. When reading data stored in the three-layer magnetic memory cell, a minute current flowing through the bit line bj corresponding to the three-layer magnetic memory cell is extracted and input to the sense amplifier 16. The sense amplifier 16 has a difference between a minute current flowing through the bit line bj and a reference current (or a voltage obtained by converting the minute current into a voltage and a reference voltage Vref obtained by converting the reference current into a voltage. Difference) is detected and amplified, and read data is output.

  Next, the reason why an isolation diode or an isolation transistor is required in order to isolate a plurality of magnetic memory cells arranged in a matrix in a general magnetic memory device will be described in detail.

  FIG. 7 is a simplified circuit diagram showing the relationship between a general magnetic memory cell and a separation diode, and FIG. 8 is a simplified circuit diagram showing an enlarged view of each memory cell portion of FIG.

  In a general magnetic memory device as shown in FIG. 7, isolation diodes (or isolation transistors) D11 to D22 are provided in series with respect to a plurality of magnetic memory cells M11 to M22 arranged in a matrix. Yes. As shown in FIG. 8, each of the four memory cell portions A, B, C, and D includes a word line wi (i is 0 or any positive integer greater than or equal to 1) and a bit line bj (j is A magnetic memory cell Mij disposed at an intersection of 0 or any positive integer greater than or equal to 1) and a separation diode Dij connected in series to the magnetic memory cell Mij.

  Here, it is assumed that not all the isolation diodes are provided in the magnetic memory device of FIG. In order to read data (information) in the memory cell portion A, a high potential voltage is applied to the corresponding bit line b0, the corresponding word line w0 is set to a low potential, and a current flowing through the magnetic memory cell M11 is detected. That's fine. At this time, the other word lines w1... Wm (m is an arbitrary positive integer of 2 or more) must be kept at a high potential. This is because the current of another memory cell part sharing the same bit line, for example, the memory cell part C flows.

  Therefore, in order to prevent this, it is necessary to set the word line w1 to a high potential. At this time, the bit line b0 is also at a high potential and the current of the memory cell portion C does not flow, but the current of all the memory cell portions such as the memory cell portion D connected to the word line w1 flows. It will be.

  In order to prevent this, it is necessary to apply a high-potential voltage to the other bit lines b1 to bn (n is an arbitrary positive integer equal to or greater than 2). Current flows, which raises the potential of the word line w0.

  From the above viewpoint, it can be seen that it is only necessary to connect a separation diode in series to each magnetic memory cell so as to keep all the word lines of the magnetic memory cells not selected at a high potential. In this case, the potential of the word line does not affect the potential of the unselected bit lines b1 to bn.

  FIG. 9 is a simplified circuit diagram showing an enlarged view of each memory cell portion when a transistor is used instead of the isolation diode of FIG.

  In the magnetic memory device as shown in FIG. 9, isolation transistors Tij are provided in series with respect to a plurality of magnetic memory cells Mij arranged in a matrix. However, here, a plurality of magnetic memory cells Mij are arranged along the intersections of a pair of word lines composed of the write word line wwi and the read word line wr and a pair of bit lines composed of the write bit line bwj and the read bit line brj. The magnetic memory device of the arrangement | positioning structure is illustrated.

  In the magnetic memory device of FIG. 9, when data is written to the magnetic memory cell Mij, the write word line wwi and the write bit line bwj are simultaneously selected and set to a predetermined potential, and a current is supplied to the magnetic memory cell Mij. The direction of the magnetic moment of the magnetic layer in the magnetic memory cell is controlled by flowing.

  When reading data stored in the magnetic memory cell Mij, the selected read word line wr is set to a high potential, and the selected read bit line brj is set to a low potential. In this way, the gate of the isolation transistor Tij connected to the selected read word line wr becomes a high potential, and the isolation transistor Tij is turned on. At this time, since the selected read bit line brj is set at a low potential, a current flows from the corresponding magnetic memory cell Mij, and data “0” or “0” stored in the magnetic memory cell Mij is stored. 1 "can be discriminated.

  On the other hand, all unselected read word lines are set to a low potential, and all unselected read bit lines are set to a high potential. In this way, the gate of the isolation transistor connected to the unselected read word line becomes a low potential, and the isolation transistor Tij is turned off. Therefore, it is possible to prevent the current from flowing from the magnetic memory cell arranged corresponding to the unselected read word line. Here, the isolation transistor connected to the selected read word line is turned on regardless of the potential of the read bit line. However, since all unselected read bit lines are set to a high potential, no current flows from the unselected magnetic memory cell to the read bit line.

  From the above viewpoint, it can be seen that the isolation transistor of FIG. 9 has substantially the same function as the isolation diode of FIGS. 7 and 8 described above. As described above, in a general magnetic memory device, it is necessary to provide an active element such as a separation diode or a separation transistor in order to prevent a plurality of magnetic memory cells from being selected simultaneously.

  In the first embodiment described above, the resistance value of the first magnetic layer in the lower layer portion of the three-layer type magnetic memory cell arranged along the word line selected at the time of data reading is lowered and not selected. By increasing the resistance value of the first magnetic layer in the lower layer portion of the magnetic memory cell arranged along the word line, the same function as the above-described isolation diode or isolation transistor is provided. Therefore, in the first embodiment described above, no isolation diode or isolation transistor is required.

  FIG. 10 is a perspective view showing the main part of the second embodiment of the present invention, and FIG. 11 is a schematic diagram showing the relationship between the direction of the magnetic moment and the resistance value of the magnetic layer of FIG. However, in FIG. 10, the configuration of the main part of the magnetic memory device according to the second embodiment of the present invention is shown in a simplified manner. In this case as well, a tunnel junction type ferromagnetic memory device is used as the magnetic memory device 1.

  The magnetic memory device 1 according to the second embodiment of FIG. 10 includes three layers including a first magnetic layer 21a in the lower layer portion, a second magnetic layer 22a in the middle layer portion, and a third magnetic layer 23a in the upper layer portion. A multi-layer magnetic memory cell 2a having a structure in which the magnetic layers are stacked. A first nonmagnetic layer 24a is formed between the first magnetic layer 21a and the second magnetic layer 22a in the magnetic memory cell to electrically and magnetically separate these magnetic layers. Is done. Further, a second nonmagnetic layer 25a is formed between the second magnetic layer 22a and the third magnetic layer 23a. In other words, the magnetic memory cell 2a of the second embodiment has a structure substantially similar to that of the magnetic memory cell 2 of the first embodiment (FIG. 1).

  In the second embodiment shown in FIG. 10, two types of word lines w0, w1, w0 'and w1 including a plurality of word lines (w0, w1) and a plurality of control word lines (w0', w1 ') are used. ', And two types of bit lines bd0, bd1, bd2, bu0, bu1 and bu2 comprising a plurality of lower bit lines (bd0, bd1 and bd2) and a plurality of upper bit lines (bu0, bu1 and bu2). Is provided. Here, a plurality of magnetic memory cells 2a having the above-described structure are prepared, and a plurality of magnetic memory cells are matrixed along the intersections of two types of word lines and two types of bit lines intersecting the word lines. Arrange in a shape.

  More specifically, a plurality of word lines w0 and w1 and lower bit lines bd0, bd1 and bd2 adjacent to these word lines w0 and w1 are provided in the lower layer portion of the magnetic memory cell. Further, a plurality of control word lines w0 ', w1' and upper bit lines bu0, bu1, and bu2 adjacent to these control word lines w0 ', w1' are provided in the upper layer portion of the magnetic memory cell. In other words, the second embodiment of FIG. 10 has a configuration in which a bit line (lower bit line) is added to the lower layer portion of the magnetic memory cell of the first embodiment (FIG. 1). . Here, the intersections of the plurality of word lines w0, w1 and the lower bit lines bd0, bd1, and bd2, that is, the intersections of the plurality of control word lines w0 ′, w1 ′ and the upper bit lines bu0, bu1, and bu2. Are defined as ML11, ML12, ML13, ML21, ML22, and ML23, respectively. Furthermore, the first line according to the magnetic memory device of the second embodiment of the present invention is composed of a plurality of word lines w0, w1 and control word lines w0 ′, w1 ′, and the second line is a plurality of lines. The lower bit lines bd0, bd1 and bd2 and the upper bit lines bu0, bu1 and bu2 are included.

  Further, in the second embodiment of FIG. 10, the word lines w0 and w1 are supplied with a predetermined current to generate a magnetic field, thereby generating a first magnetic layer formed in the lower layer portion of the multi-bit magnetic memory cell. Control the direction of the magnetic moment of the layer 21a. On the other hand, the control word lines w0 'and w1' also generate a magnetic field by flowing a predetermined current, thereby causing the magnetic field of the third magnetic layer 23a formed in the upper layer portion of the multi-bit magnetic memory cell. Control the direction of the moment. Further, since the lower first magnetic layer 21a is adjacent to both the word lines w0 and w1 and the lower bit lines bd0, bd1 and bd2, the selected word line and the selected lower bit line It is possible to reverse the direction of the magnetic moment of the specific first magnetic layer 21 located at the intersection with the. On the other hand, since the upper third magnetic layer 23a is adjacent to both the control word lines w0 'and w1' and the upper bit lines bu0, bu1 and bu2, it is selected as the selected control word line. It is possible to reverse the direction of the magnetic moment of the specific third magnetic layer 23 located at the intersection with the upper bit line. Actually, since the magnetic moments of the lower first magnetic layer 21a and the upper third magnetic layer 23a are controlled by the combined magnetic field of the word line and the bit line, the magnetic moment in the horizontal direction with respect to the magnetic layer Instead, it is facing diagonally.

  Further, the magnetic moment of the second magnetic layer 22a formed in the middle layer portion is the same as in the first embodiment described above, either the upper control word line or the lower word line, Alternatively, both can be used to direct a certain direction by generating a strong magnetic field with a relatively large current. In this way, the magnetic moment of the first magnetic layer 21a in the lower layer and the magnetic force of the third magnetic layer 23a in the upper layer are not affected without affecting the magnetic moment of the second magnetic layer 22a in the middle layer. The moment can be reversed independently. Therefore, according to the second embodiment, it is possible to store multi-value data (multi-bit data) of at least 2 bits.

  As shown in FIGS. 11A to 11D, the magnetic properties of the first, second and third magnetic layers formed in each of the multi-bit magnetic memory cells ML11, ML12, ML13, ML21, ML22 and ML23. Depending on the direction of the moment, the portion including the third magnetic layer 23a in the upper layer has binary resistance values R0 and R1 (R0 <R1), and the first magnetic layer 21a in the lower layer. The portion including, has two resistance values of resistance values R2 and R3 (R2 <R3). As described above, the direction of the magnetic moment of the upper third magnetic layer 23a is controlled by using the control word lines w0 'and w1' and the upper bit lines bu0, bu1 and b2, while the lower layer part. The direction of the magnetic moment of the first magnetic layer 21a can be controlled using the word lines w0, w1 and the lower bit lines bd0, bd1, and bd2. In short, the upper layer portion and the lower layer portion of the multi-bit magnetic memory cell can store “0” or “1” data independently of each other.

  11A to 11D, when the directions of the magnetic moments of the second magnetic layer 22a and the third magnetic layer 23a are parallel to each other, as in the case of FIG. When the resistance value including the portion of the third magnetic layer 23a is R0 and antiparallel to each other, the resistance value is R1. As described above, the resistance value R0 is smaller than the resistance value R1 (R0 <R1). On the other hand, when the directions of the magnetic moments of the first magnetic layer 21a and the second magnetic layer 22a are parallel to each other, the resistance value including the portion of the first magnetic layer 21a becomes R2 and is antiparallel to each other. In this case, the resistance value is R3. As described above, the resistance value R2 is smaller than the resistance value R3 (R2 <R3). Therefore, the resistance value when a current is passed in the direction perpendicular to the first to third magnetic layers 21a to 23a is the first to third magnetic layers as shown in FIGS. R0 + R2, R1 + R2, R0 + R3, and R1 + R3, respectively, depending on the direction of the magnetic moment of the layers 21a-23a. As in the case of the first embodiment (FIG. 3), the relationship between the magnitudes of these resistance values is set as (R0 + R2) <(R1 + R2) <(R0 + R3) <(R1 + R3).

  As described above, the resistance values R0 and R1 are determined by the direction of the magnetic moment of the third magnetic layer 23a of the magnetic memory cell located at the intersection of the selected control word line and the selected upper bit line. The Therefore, as shown in FIGS. 11A and 11B, the resistance values R0 and R1 can be made to correspond to “0” or “1” of the data in the upper layer portion of the magnetic memory cell, respectively. Further, the resistance values R2 and R3 are determined by the direction of the magnetic moment of the first magnetic layer 21a of the magnetic memory cell located at the intersection of the selected word line and the selected lower bit line.

  Therefore, as shown in FIGS. 11C and 11D, the resistance values R2 and R3 can be made to correspond to “0” or “1” of the data in the lower layer portion of the magnetic memory cell, respectively. In other words, in (a) of FIG. 11, the upper layer data and the lower layer data are both “0” (“00”), and in FIG. 11 (b), the upper layer data is “0”. The data in the lower layer is “1” (“01”). Further, in FIG. 11C, the upper layer data is “1” and the lower layer data is “0” (“10”), and in FIG. Are both “1” (“11”). Since these quaternary data can correspond to logical values, the second embodiment can be applied to a multifunctional magnetic memory device.

  Here, in the second embodiment, unlike the first embodiment, the isolation diode for isolating a plurality of magnetic memory cells from each other in the lower ferromagnetic layer of the magnetic memory cell. It should be noted that the function of the isolation transistor cannot be provided. Therefore, in the second embodiment, it is necessary to provide a separation diode or a separation transistor in series with each magnetic memory cell. By providing isolation diodes for isolating the multi-bit magnetic memory cells from each other in series with the multi-bit magnetic memory cells ML11 to ML23 in FIG. And the data of the lower layer can be individually controlled. As a result, four-value independent control can be performed with one memory cell, so that a multi-bit MRAM can be achieved.

  12 is a simplified circuit diagram showing the main part of the third embodiment of the third invention of the present invention, FIG. 13 is a simplified circuit diagram showing the configuration of the entire magnetic memory cell according to the embodiment of FIG. And FIG. 14 is a graph which shows the time change of the voltage of the one end of the capacitor | condenser in the Example of FIG. Here, a magnetic memory cell having a structure in which two or more ferromagnetic layers are stacked is assumed as the magnetic memory cell (that is, a conventional magnetic memory cell is also included).

  In the magnetic memory device shown in FIG. 12, isolation transistors Tij are provided in series with respect to a plurality of magnetic memory cells Mij arranged in a matrix. However, in this case, a magnetic memory device having a configuration in which the magnetic memory cell Mij is arranged at the intersection of one word line wi and one bit line bj is illustrated.

  In the overall configuration of the magnetic memory cell shown in FIG. 13, a plurality of the magnetic memory cells (M11 to M23) are prepared, a plurality of word lines (only w0, w1, and w2 are shown here), and these The magnetic memory cells are arranged in a matrix along intersections with a plurality of bit lines (only b0 and b1 are shown here) intersecting the word lines. Further, isolation transistors T11 to T22 for isolating the magnetic memory cells from each other are provided in series with the plurality of magnetic memory cells M11 to M22.

  In the magnetic memory device having such a configuration, when data is written to the magnetic memory cell Mij, the word line wi and the bit line bj are simultaneously selected and set to a predetermined potential, and a current is supplied to the magnetic memory cell Mij. The direction of the magnetic moment of the magnetic layer in the magnetic memory cell is controlled by flowing.

  When reading data stored in the magnetic memory cell Mij, the selected word line wi is set to a high potential, and the selected bit line bj is set to a low potential. In this way, the gate of the isolation transistor Tij connected to the selected read word line wi becomes a high potential, and the isolation transistor Tij is turned on. At this time, since the selected read bit line bj is set to a low potential, a current flows from the corresponding magnetic memory cell Mij. By detecting this current with a sense amplifier or the like and comparing it with a reference current, it is possible to determine “0” or “1” of the data stored in the magnetic memory cell Mij. As described with reference to FIG. 9, the function of the isolation transistor Tij makes it possible to prevent current from flowing from unselected magnetic memory cells.

  As described above, in a general magnetic memory device, data is written to or read from the magnetic memory cell by simultaneously supplying current to selected word lines and bit lines. Is relatively inconvenient.

  In order to cope with this inconvenience, in the above third embodiment, voltage reading means 8 such as a capacitor Cij having a capacitance value almost the same as the capacitance value of each magnetic memory cell is connected in series to each magnetic memory cell. It is configured to connect to. However, the capacitance value of the capacitor Cij is allowed to vary within an identifiable range. Preferably, the plurality of capacitors (C11 to C22) are provided between one terminal of the plurality of magnetic memory cells M11 to M22 and the ground terminal, as shown in FIG.

  In the third embodiment described above, instead of detecting the current flowing out of the selected magnetic memory cell and determining whether the data is “0” or “1”, one terminal of each magnetic memory cell Mij and the capacitor Cij The level of the voltage obtained by measuring the potential of the contact P with the above at a predetermined timing is determined.

More specifically, a predetermined voltage (for example, a high potential voltage) is applied to the word line wi selected at the time of data reading, and charges are injected into the capacitor Cij connected in series to the magnetic memory cell Mij. . This charging takes advantage of the fact that the resistance value differs depending on whether the data stored in the magnetic memory cell Mij is “0” or “1”, so that a difference occurs in the charging characteristics (charging curve) of the capacitor Cij. Data “0” or “1” is determined by detecting the difference in characteristics as a voltage level. Note that when the word line wi is set to a high potential, the gate of the isolation transistor Tij becomes a high potential, but since the bit line bj is set to a high potential or a high impedance, charge can be injected into the capacitor Cij. .

  More specifically, as shown in the graph of FIG. 14, the change in the voltage Vo at one terminal (contact P) of the capacitor Cij is measured using the time t for charging the capacitor Cij as a parameter. Further, by detecting the voltage level obtained by voltage conversion at a predetermined measurement timing tm and comparing this voltage level with a reference voltage (reference voltage) Vr, data “0” or “1” is obtained. "Is discriminated. FIG. 14 illustrates a charge curve when the resistance value of the magnetic memory cell storing “0” data is larger than the resistance value of the magnetic memory cell storing “1” data. . In this case, data “1” is read when the voltage level detected at the measurement timing tm is higher than the reference voltage Vr, and data “0” is read when the voltage level is lower than the reference voltage Vr.

  According to the third embodiment described above, the difference between the charge curves when a charge is injected into a capacitor connected in series to the magnetic memory cell without detecting the current flowing out of the magnetic memory cell is used as the voltage level. Therefore, the power consumption of the entire magnetic memory device can be greatly reduced.

  Preferably, in the magnetic memory device configured as shown in FIGS. 12 and 13, when data is read by detecting a difference in resistance value of the magnetic memory cell selected by the word line and the bit line, each magnetic memory device A capacitor having a capacitance value substantially the same as the capacitance value of the cell is connected in series to each magnetic memory cell, and a contact point between one terminal of the magnetic memory cell selected by the word line and the bit line and the capacitor A data reading method is executed in which the level of the voltage obtained by measuring the potential is determined at a predetermined timing.

  FIG. 15 is a timing chart showing a first example for discharging the capacitor charge before the read operation in the embodiment of FIG.

  As apparent from the charging curve of FIG. 14 described above, in order to accurately detect the level of the voltage Vo at a predetermined measurement timing, the charge of the capacitor Cij is discharged before the data reading operation is performed. The level of the voltage Vo at the timing of starting charging the capacitor needs to be zero.

  As shown in the timing chart of FIG. 15, the first example for discharging the charge of the capacitor Cij is to discharge the charge accumulated in the capacitor Cij toward the bit line bj before executing the data read operation. It is something to be made.

  In the first example, before the data of the magnetic memory cell selected by the word line and the bit line is read, the word line wi connected to the terminal opposite to the contact P of the magnetic memory cell is set to the high potential (“H (High) "), and the bit line bj connected to one terminal of the magnetic memory cell via the isolation transistor Tij is set to a low potential (" L (Low) "). At this time, the gate of the isolation transistor Tij becomes a high potential, and the isolation transistor Tij is turned on. In this way, the electric charge accumulated in the capacitor Cij connected to one terminal of the magnetic memory cell is discharged toward the bit line bj, and the magnetic memory cell is reset.

At this time, the capacitor Cij changes from an indefinite state to a reset state. However, in this case, it is assumed that a current that is so large that the direction of the magnetic moment of the magnetic layer in the magnetic memory cell is reversed does not flow. Thereafter, the difference in the charging curve when the capacitor Cij is charged by injecting electric charge is detected as the voltage level. To charge the capacitor Cij , the potential of the driver connected to the bit line bj is set to a low level, and then the driver is set to a high impedance state (Hi-Z state) so as to charge the capacitor . Potential charged in the capacitor would read the data is done by enabling a receiver connected to the bit line bj.

  Further, in the first example, the word line connected to the other terminal of the plurality of non-selected magnetic memory cells is set to a high potential, and the bit line is set to a low potential, whereby the non-selected magnetic memory cell It is preferable to discharge the electric charge stored in the capacitor connected in series toward the bit line. As a result, the charges of the capacitors connected in series to the non-selected magnetic memory cells are all discharged, and the data read operation of the selected magnetic memory cell is not affected.

  FIG. 16 is a timing chart showing a second example for discharging the capacitor charge before the read operation in the embodiment of FIG.

  As shown in the timing chart of FIG. 16, the second example for discharging the charge of the capacitor Cij is to discharge the charge stored in the capacitor Cij toward the word line wi before executing the data read operation. It is something to be made.

  In the second example, before the data of the magnetic memory cell selected by the word line and the bit line is read, the word line wi connected to the terminal opposite to the contact P of the magnetic memory cell is set to the low potential (“L”). ”) To the power line. At this time, the electric charge accumulated in the capacitor Cij connected to one terminal of the magnetic memory cell is discharged to the word line wi through the magnetic memory cell, and the magnetic memory cell is reset. At this time, the capacitor Cij changes from an indefinite state to a reset state. That is, an operation similar to writing data “0” in the magnetic memory cell is performed. However, in this case, it is assumed that a current that is so large that the direction of the magnetic moment of the magnetic layer in the magnetic memory cell is reversed does not flow. Thereafter, the difference in the charge curve when the capacitor Cij is charged by injecting electric charge is detected as the voltage level.

  Further, in the second example, the word line connected to the other terminal of the plurality of non-selected magnetic memory cells is connected in series to the non-selected magnetic memory cells by connecting to the low-potential power line. It is preferable to discharge the electric charge accumulated in the capacitor toward the word line. As a result, the charges of the capacitors connected in series to the non-selected magnetic memory cells are all discharged, and the data read operation of the selected magnetic memory cell is not affected.

  FIG. 17 is a simplified circuit diagram showing the configuration of the modification of FIG. 12, and FIG. 18 is a simplified circuit diagram showing the configuration of the entire magnetic memory cell of FIG.

  In the magnetic memory device shown in FIGS. 17 and 18, isolation diodes Dij (D11 to D22) are provided in place of the isolation transistors Tij in the third embodiment of FIGS. More specifically, in FIGS. 17 and 18, a plurality of magnetic memory cells Mij (M11 to M22) arranged in a matrix are connected in series with a separation diode Dij for separating the magnetic memory cells from each other. (D11 to D22) are connected to each other.

  As described with reference to FIGS. 7 and 8, the function of the isolation diode Dij can prevent current from flowing from a non-selected magnetic memory cell. However, in the magnetic memory device shown in FIGS. 17 and 18, it should be noted that the connection relationship between the isolation diode and the word line and the bit line is different from that in FIGS. Here, only the selected word line is set to a high potential, and only the selected bit line is set to a low potential, so that no current flows from unselected magnetic memory cells.

  Since the components (especially the capacitor Cij) other than the isolation diode Dij are the same as those in the third embodiment described above, here, a magnetic memory device in which a capacitor Cij is provided in series with each magnetic memory cell Mij. A detailed description of the configuration and operation thereof is omitted.

  In the above modification, as in the case of the third embodiment described above, charging is performed when a charge is injected into a capacitor connected in series to the magnetic memory cell without detecting the current flowing out of the magnetic memory cell. Since the difference between the curves is used as the voltage level to determine whether the data is “0” or “1”, the power consumption of the entire magnetic memory device can be greatly reduced.

Additional Notes The present invention has the following features.

(Supplementary Note 1) A magnetic memory cell is formed by stacking at least three magnetic layers including a first magnetic layer, a second magnetic layer, and a third magnetic layer, and the magnetic memory cell includes the first, The second and third magnetic layers have different resistance values depending on the direction of the magnetic moment, and the plurality of magnetic memory cells are divided into a plurality of first lines and a plurality of second lines intersecting the first lines. Arranged along the intersection of the lines, a predetermined current is selectively passed through the first line and the second line to control the direction of the magnetic moment of the first, second and third magnetic layers. Thus, a magnetic memory device for writing data to a specific magnetic memory cell,
Each of the first lines is composed of at least two word lines, and each of the word lines individually controls the direction of the magnetic moment of any one of the first, second and third magnetic layers. By doing so, data of two or more values is stored in the specific magnetic memory cell.

  (Supplementary Note 2) Each of the first lines is composed of two word lines, and the two word lines are provided in an upper layer portion and a lower layer portion of each of the magnetic memory cells, respectively. The line controls the direction of the magnetic moment of the magnetic layer formed in the upper layer part, and the word line of the lower layer part controls the direction of the magnetic moment of the magnetic layer formed in the lower layer part. The magnetic memory device according to appendix 1.

  (Supplementary Note 3) When data is read by detecting a difference in resistance value of the magnetic memory cells selected by the first line and the second line, a plurality of the magnetic memory cells are simultaneously selected. In order to prevent the occurrence of the failure, a separation diode or a separation transistor for separating the plurality of magnetic memory cells from each other is provided in series with each of the magnetic memory cells. Magnetic memory device.

  (Supplementary Note 4) When data is read by detecting a difference in resistance value of the magnetic memory cell selected by the first line and the second line, the second line constituting the first line The direction of the magnetic moment of the magnetic layer of the magnetic memory cell in which one word line located on the side that does not affect the current flowing through the second line among the two word lines is arranged, Separation for separating the plurality of magnetic memory cells from each other by controlling each word line and making the direction of the magnetic moment of the magnetic layer correspond to selection or non-selection of the magnetic memory cells by the first line 3. The magnetic memory device according to appendix 2, wherein a diode or a separating transistor is not required.

  (Supplementary Note 5) Each of the second lines includes two bit lines, and the two bit lines are provided in an upper layer portion and a lower layer portion of each of the magnetic memory cells, respectively. The word line and the upper bit line control the direction of the magnetic moment of the magnetic layer formed in the upper layer, and the lower word line and the lower bit line are formed in the lower layer. The magnetic memory device according to appendix 2, wherein multivalued data is stored by controlling the direction of the magnetic moment of the magnetic layer.

(Supplementary Note 6) A magnetic memory cell is formed by stacking at least three magnetic layers including a first magnetic layer, a second magnetic layer, and a third magnetic layer, and the magnetic memory cell includes the first, The second and third magnetic layers have different resistance values depending on the direction of the magnetic moment, and the plurality of magnetic memory cells are divided into a plurality of first lines and a plurality of second lines intersecting the first lines. In a magnetic memory device arranged along an intersection of lines, for reading data by detecting a difference in resistance value of the magnetic memory cells selected by the first line and the second line A data reading method comprising:
Of the two word lines constituting the first line, the magnetic layer of the magnetic memory cell in which one word line located on the side not affecting the current flowing through the second line is disposed. Control the direction of the magnetic moment for each one of the word lines;
The direction of the magnetic moment of the magnetic layer corresponds to the selection or non-selection of the magnetic memory cell by the first line,
A method of reading data in a magnetic memory device, characterized in that a separating diode or a separating transistor for separating a plurality of the magnetic memory cells from each other is unnecessary.

(Supplementary Note 7) A magnetic memory cell is formed by laminating a plurality of magnetic layers, and the magnetic memory cell has a resistance value that differs depending on the direction of the magnetic moment of the plurality of magnetic layers, and the plurality of magnetic memories In a magnetic memory device in which cells are arranged along intersections of a plurality of first lines and a plurality of second lines intersecting with the first lines,
Voltage reading means having a capacitance value substantially the same as the capacitance value of each of the magnetic memory cells is connected in series to each of the magnetic memory cells,
Determining a voltage level obtained by measuring a potential of a contact point between one end of the magnetic memory cell selected by the first line and the second line and the voltage reading unit at a predetermined timing; A magnetic memory device, wherein the data of the magnetic memory cell is read out.

  (Supplementary Note 8) In order to prevent a plurality of magnetic memory cells from being simultaneously selected when reading data from the magnetic memory cells selected by the first line and the second line, A separation diode or a separation transistor for separating the plurality of magnetic memory cells from each other is provided between one end of each of the magnetic memory cells, a contact point between the voltage reading means, and the second line. The magnetic memory device according to appendix 7, which is characterized by the following.

  (Supplementary Note 9) Before reading the data of the magnetic memory cell selected by the first line and the second line, the first line connected to the other end of the magnetic memory cell is set to a high potential. The voltage readout connected to one end of the magnetic memory cell by setting the second line connected to one end of the magnetic memory cell through the isolation diode or the isolation transistor to a low potential. The magnetic memory device according to appendix 8, wherein the electric charge accumulated in the means is discharged toward the second line.

  (Supplementary Note 10) A first line connected to the other end of a non-selected magnetic memory cell not selected by the first line and the second line is set to a high potential, and the isolation diode or the isolation diode By setting the second line connected to one end of the non-selected magnetic memory cell through a transistor to a low potential, the voltage is stored in the voltage reading means connected to one end of the non-selected magnetic memory cell. 10. The magnetic memory device according to appendix 9, wherein the charged electric charge is discharged toward the second line.

  (Supplementary Note 11) Before reading the data of the magnetic memory cell selected by the first line and the second line, the first line connected to the other end of the magnetic memory cell is connected to the power supply line. The magnetic material according to claim 8, wherein the electric charge accumulated in the voltage reading means connected to one end of the magnetic memory cell is discharged toward the first line through the magnetic memory cell. Memory device.

  (Supplementary Note 12) A first line connected to the other end of the non-selected magnetic memory cell not selected by the first line and the second line is connected to a power supply line, and the non-selected magnetic memory cell is 13. The magnetic memory device according to appendix 11, wherein the charge accumulated in the voltage reading means connected to one end of the non-selected magnetic memory cell is discharged toward the first line.

(Supplementary Note 13) A plurality of magnetic layers are stacked to form a magnetic memory cell, and the magnetic memory cell has a resistance value that differs depending on the direction of the magnetic moment of the plurality of magnetic layers. In a magnetic memory device in which cells are arranged along intersections of a plurality of first lines and a plurality of second lines intersecting with the first lines, the cells are selected by the first lines and the second lines A data reading method for reading data by detecting a difference in resistance value of the magnetic memory cell,
Voltage reading means having a capacitance value substantially the same as the capacitance value of each of the magnetic memory cells is connected in series to each of the magnetic memory cells,
Determining a voltage level obtained by measuring a potential of a contact point between one end of the magnetic memory cell selected by the first line and the second line and the voltage reading unit at a predetermined timing; A method for reading data in a magnetic memory device, characterized in that the data in the magnetic memory cell is read out.

It is a perspective view which shows the principal part of the 1st Example of this invention. FIG. 2 is a circuit diagram showing an equivalent circuit of the magnetic memory device of FIG. 1. It is a schematic diagram which shows the relationship between the direction of the magnetic moment of a magnetic layer of FIG. 1, and resistance value. It is a front view which shows an example of the shape of the word line used in the Example of this invention. 1 is a block diagram showing an overall structure of a magnetic memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an example of a sense amplifier unit in FIG. 5. It is a simplified circuit diagram which shows the relationship between a general magnetic memory cell and the isolation diode. FIG. 8 is a simplified circuit diagram illustrating each memory cell portion of FIG. 7 in an enlarged manner. FIG. 9 is a simplified circuit diagram showing an enlarged view of each memory cell portion when a transistor is used instead of the isolation diode of FIG. 8. It is a perspective view which shows the principal part of the 2nd Example of this invention. It is a schematic diagram which shows the relationship between the direction of the magnetic moment of a magnetic layer of FIG. 10, and resistance value. It is a simplified circuit diagram which shows the principal part of the 3rd Example of this invention. FIG. 13 is a simplified circuit diagram illustrating a configuration of an entire magnetic memory cell according to the example of FIG. 12. It is a graph which shows the time change of the voltage of the one end of the capacitor | condenser in the Example of FIG. FIG. 13 is a timing chart showing a first example for discharging the capacitor charge before the read operation in the embodiment of FIG. 12; FIG. FIG. 13 is a timing chart showing a second example for discharging the capacitor charge before the read operation in the embodiment of FIG. 12; FIG. It is a simplified circuit diagram which shows the structure of the modification of FIG. FIG. 18 is a simplified circuit diagram illustrating a configuration of the entire magnetic memory cell of FIG. 17. It is a schematic diagram which shows the operation principle of the magnetic memory cell using a general magnetoresistive effect. It is a perspective view which shows the structure of the magnetic memory device of the conventional 1st example. It is a perspective view which shows the structure of the magnetic memory device of the conventional 2nd example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Magnetic memory device 2 Magnetic memory cell 3 Control circuit part 4 Write circuit part 5 Address decoder 6 Sense amplifier part 7 Data selector part 8 Voltage reading means 16 Sense amplifier 21 1st magnetic layer 22 2nd magnetic layer 23 3rd Magnetic layer 24 First non-magnetic layer 25 Second non-magnetic layer Cij Capacitor Mij Magnetic memory cell MCij Three-layer magnetic memory cell MLij Multi-bit magnetic memory cell

Claims (5)

A plurality of magnetic layers are stacked to form a magnetic memory cell, and the magnetic memory cell has a resistance value that differs depending on a magnetic moment direction of the plurality of magnetic layers. In a magnetic memory device arranged along the intersection of a first line and a plurality of second lines intersecting with the first line,
Voltage reading means having a capacitance value substantially the same as the capacitance value of each of the magnetic memory cells is connected in series to each of the magnetic memory cells,
The voltage level obtained by measuring the transient potential at the contact point between the one end of the magnetic memory cell selected by the first line and the second line and the voltage reading means at a predetermined timing. A magnetic memory device which reads data of the magnetic memory cell by determining.   When reading data from the magnetic memory cells selected by the first line and the second line, in order to prevent a plurality of the magnetic memory cells from being selected at the same time, An isolation diode or an isolation transistor for isolating a plurality of the magnetic memory cells from each other is provided between one end of the memory cell, a contact point between the voltage reading means, and the second line. Item 2. A magnetic memory device according to Item 1.   Before reading the data of the magnetic memory cell selected by the first line and the second line, the first line connected to the other end of the magnetic memory cell is set to a high potential, and the separation By setting the second line connected to one end of the magnetic memory cell through a diode or the isolation transistor to a low potential, the voltage is stored in the voltage reading means connected to one end of the magnetic memory cell. The magnetic memory device according to claim 2, wherein the charged electric charge is discharged toward the second line.   Before reading the data of the magnetic memory cell selected by the first line and the second line, the first line connected to the other end of the magnetic memory cell is connected to the power supply line, and the magnetic memory 3. The magnetic memory device according to claim 2, wherein the charge accumulated in the voltage reading means connected to one end of the magnetic memory cell is discharged through the cell toward the first line. A plurality of magnetic layers are stacked to form a magnetic memory cell, and the magnetic memory cell has a resistance value that differs depending on the direction of the magnetic moment of the plurality of magnetic layers. In a magnetic memory device arranged along the intersection of a first line and a plurality of second lines intersecting with the first line, the magnetic material selected by the first line and the second line A data reading method for detecting a difference in resistance value of a memory cell and reading data,
Voltage reading means having a capacitance value substantially the same as the capacitance value of each of the magnetic memory cells is connected in series to each of the magnetic memory cells,
The voltage level obtained by measuring the potential of the transient state of the contact point between the one end of the magnetic memory cell selected by the first line and the second line and the voltage reading means at a predetermined timing. A data reading method in a magnetic memory device, wherein the data of the magnetic memory cell is read out by determining.

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