JP3566531B2 - Magnetic device - Google Patents

Description

【００６０】
となり、状態密度は図３に示すように階段状になる。なお、式（１）において、ｌは膜厚をしめしている。一方、トンネル電流の角度依存性
【数２】

【００６１】
を考慮すると、絶縁膜をトンネルする電子の波数ベクトルは図４に示すようにトンネル接合面にほぼ垂直（θ_ｃ 〜１０゜）であり、図３の状態のうち斜線を施した部分の電子のみがトンネル電流に寄与することが分かる。なお、式（２）において、ｓはトンネル障壁の厚さを示している。
【００６２】
ここで、斜線を施した部分のエネルギー幅は約１００ｍｅＶであり、ｌ＝４ｎｍの場合、フェルミエネルギーＥ_Ｆ を５ｅＶ程度とすると、フェルミエネルギーＥ_Ｆ 近くでの斜線を施した部分のエネルギー間隔は約１．０ｅＶと大きい。すなわち、磁性体超薄膜中のｓ電子はトンネル接合においてあたかも絶縁膜中の電子のように振る舞い、トンネル電流には寄与しない。
【００６３】
なお、ここでは、磁性体超薄膜の膜厚を４ｎｍとしたが、一般には５ｎｍ以下とすれば、トンネル電流を少なくできる。要はフェルミエネルギーＥ_Ｆ 近くでの斜線を施した部分のエネルギー間隔が大きくなり、ｓ電子がトンネル電流に寄与しなくなる薄い厚さを選べば良い。
【００６４】
しかしながら、磁性体超薄膜のみを電極に用いるとシート抵抗が増大してしまうので、図５に示すように、磁性体電極を磁性体超薄膜８と十分な厚さをもった導電性のバックアップ膜６とで構成することが好ましい。
【００６５】
その際、磁性体超薄膜８の２次元性（２ＤＥＧ）を損なわないためには、磁性体超薄膜８とバックアップ膜６との間に絶縁物からなるバリア膜７を設けることが必要になるが、そのバリア膜７の厚さはトンネル絶縁膜のそれよりも十分に薄くなければならない。なお、図中、５はＳｉ基板を示している。
【００６６】
また、これまでの説明から分かるように、磁性体超薄膜を一層だけでなく、図６に示すように、磁性体超薄膜８の積層膜を用いることも可能である。その場合にもバリア膜７の厚さはトンネル絶縁膜のそれよりも十分薄いことが必要である。
【００６７】
磁性体トンネル接合素子１としては、例えば図７に示すように、Ｃｏ／ＡｌＯｘ／Ｃｏトンネル接合を有するものがあげられる。
【００６８】
これを製造工程に従って説明すると、まず、Ｓｉ（１００）基板１０の表面に厚さ５ｎｍのＳｉＯ_２ 膜１１を熱酸化法により形成する。
【００６９】
次にＳｉＯ_２ 膜１１上に下部電極としての厚さ５０ｎｍ、幅０．２ｍｍのＣｏ膜１２を真空蒸着法により形成する。ここで、真空蒸着の際の真空度、基板温度はそれぞれ１×１０^−８ｔｏｒｒ、７７Ｋに設定する。さらに、５００Ｏｅの外部磁場を印加し、磁気容易軸が一方向に揃うようにする。
【００７０】
次にＣｏ膜１２上に厚さ１．２ｎｍのＡｌ膜を真空蒸着法により形成した後、基板温度を室温に戻し、続いて酸素雰囲気中でのグロー放電により上記Ａ１膜を酸化し、Ａｌ_ｘ Ｏからなるトンネル絶縁膜１３を形成する。真空蒸着の際の真空度、基板温度は前と同じである。
【００７１】
次に再び基板温度を７７Ｋに設定し、トンネル絶縁膜１３上に上部電極としての厚さ４ｎｍ、幅０．２ｎｍのＣｏ超薄膜１４を真空蒸着法により形成する。真空蒸着の際の真空度は前と同じである。
【００７２】
次に基板温度を室温に戻した後、Ｃｏ超薄膜１４の表面を１×１０^−３ｔｏｒｒの酸素雰囲気中に１分間曝すことにより、Ｃｏ超薄膜１４の表面にバリア膜１５を形成する。
【００７３】
最後に、バリア膜１５上にＡｕからなる厚さ５０ｎｍのバックアップ膜１６を形成する。
【００７４】
このようにして作成された磁性体トンネル接合素子の磁気抵抗効果を測定してみた。この測定は、交流ブリッジを用い、トンネル接合面内に外部磁場を印加して行なった。
【００７５】
図８に、その測定結果を示す。磁化曲線を反映した磁気抵抗特性が見られ、ＭＲ比は約２６％である。また、飽和磁場の下での接合抵抗の絶対値は約２０Ωであった。
【００７６】
図９に、他のＣｏ／ＡｌＯｘ／Ｃｏトンネル接合からなる磁性体トンネル接合素子の断面図を示す。なお、図７の磁性体トンネル接合素子と対応する部分には図７と同一符号を付してあり、詳細な説明は省略する。
【００７７】
図７の磁性体トンネル接合素子と異なる点は、上部電極だけではなく、下部電極にもＣｏ超薄膜１４を用い、さらに下部電極側にもバックアップ膜１７およびバリア膜１８を形成したことにある。バックアップ膜１７としては、厚さ５０ｎｍのＣｕ膜を用いている。このようにして下部電極側にもトンネル接合が形成される。
【００７８】
バックアップ膜１７であるＣｕ膜は基板温度を７７Ｋにして真空蒸着法により形成し、バリア膜１８はバックアップ膜１７の形成後に基板温度を室温に戻して、バックアップ膜１７を１×１０^−３ｔｏｒｒの酸素雰囲気中に１分晒すことにより形成する。その他の膜の形成方法は図７の素子の場合と同じである。
【００７９】
図７の磁性体トンネル接合素子の場合と同様な方法で本素子の磁気抵抗効果を測定したところ、飽和磁場下の接合抵抗は２２Ωであったが、ＭＲ比は３５％に増大していた。
【００８０】
また、比較例として、図７の磁性体トンネル接合素子において、上部電極である厚さ４ｎｍのＣｏ超薄膜を厚さ５０ｎｍのＣｏ膜に置き換えた磁性体トンネル接合素子を形成した。その形成は図７の磁性体トンネル接合素子のそれに準じる。
【００８１】
図７の磁性体トンネル接合素子と同様な方法で本素子の磁気抵抗効果を測定したところ、飽和磁場下の接合抵抗は１８Ωであったが、ＭＲ比は１５％であり、図７、図８の素子のＭＲ比よりも小さかった。
【００８２】
（第２の実施形態）
図１０に、本発明の第２の実施形態に係る磁気メモリセルを示す。なお、図１の磁気メモリセルと対応する部分には図１と同一符号を付してあり、詳細な説明は省略する。
【００８３】
本実施形態は、ＧＭＲ素子としては、ホットエレクトロン・トランジスタを用いた例である。ホットエレクトロン・トランジスタは、磁性体トンネル接合素子よりも大きなＭＲ比を示すＧＭＲ素子である。ホットエレクトロン・トランジスタのＭＲ比は２００％を越える。したがって、メモリセルの情報を正しく読出すことがより容易になり、読取りエラーを少なくできる。
【００８４】
しかし、ホットエレクトロン・トランジスタの電流利得は小さく、ベース接地の場合、コレクタ電流がエミッタ電流より１桁以上減少してしまう。
【００８５】
このため、ｎｓ程度の高速動作をさせるためには、磁性体トンネル接合素子の場合と同様に、図１０に示すように、ホットエレクトロン・トランジスタ９（のコレクタ）はＭＯＳトランジスタ２のゲートに接続することが好ましい。
【００８６】
ところで、ベース接地での電流利得は高々０．１程度と推定されるので、高速動作のためにはエミッタ電流を大きくすること好ましい。
【００８７】
大きなエミッタ電流を流すには、図２６のトンネル注入型のホットエレクトロン・トランジスタよりも、図２７のショットキー注入型のホットエレクトロン・トランジスタのほうが好ましい。
【００８８】
図２６のホットエレクトロン・トランジスタを形成する場合、ＭＯＳ型トランジスタと同一基板上に形成するので、コレクタ層の材料にはＳｉを用いることになる。コレクタ層としてはＳｉ層で良いが、エミッタ層としては以下の条件を満足する半導体層であることが好ましい。すなわち、バンドギャップが広く、かつ成膜温度が低い半導体層が好ましい。
【００８９】
成膜温度が低いことが好ましい理由は、エミッタ層はベース層の後に形成するため、成膜温度が高いと、ベース層である磁性積層膜の特性が劣化する恐れがあるからである。
【００９０】
また、バンドギャップが広いことが好ましい理由は、エネルギーの高い電子を用いることにより、ベース／コレクタ界面の量子力学的反射を低減できるからである。
【００９１】
このような２つの条件を満たす半導体層としては、Ｎｂがドープされたｎ型のチタン酸ストロンチュウム（ＳＴＯ）層（Ｎｂドープｎ型ＳＴＯ層）が最も適している。
【００９２】
図１１に、エミッタ層としてＮｂドープｎ型ＳＴＯ層を用いた場合のエミッタ電流（Ｉ_Ｅ ）のコレクタ・ベース間電圧（Ｖ_ＥＢ）の依存性を示す。
【００９３】
図から、０．９Ｖ程度の電圧をコレクタ・ベース間に印加することにより、１０^３ Ａ／ｃｍ^２ 程度のエミッタ電流が流れることが分かる。この場合、電流利得が０．１であるとすると読出し時間は０．１ｎｓとなり、また、電流利得が０．０１であっても読出し時間１ｎｓとなる。
【００９４】
（第３の実施形態）
図１２に、本発明の第３の実施形態に係る磁気ヘッドを示す。なお、図１の磁気メモリセルと対応する部分には図１と同一符号を付してあり、詳細な説明は省略する。
【００９５】
本実施形態の磁気ヘッドは、図１の磁気メモリセルからビット線ＢＬ、ワード線ＷＬ、磁化手段を取り除いた構成になっている。
【００９６】
磁性体トンネル接合素子１の磁気抵抗は、磁気記録媒体上を走査する際に変化し、これに対応した電圧変化をセンスアンプで検出することにより、磁気記録媒体に書き込まれた情報を読み出すことができる。
【００９７】
本実施形態の磁気ヘッドも、第１の実施形態の磁気メモリの場合と同様の理由により、高速な読出しが可能となる。
【００９８】
（第４の実施形態）
図１３に、本発明の第４の実施形態に係る磁気ヘッドを示す。なお、図１０の磁気メモリセルと対応する部分には図１０と同一符号を付してあり、詳細な説明は省略する。
【００９９】
本実施形態の磁気ヘッドは、図１０の磁気メモリセルからビット線ＢＬ、ワード線ＷＬ、磁化手段を取り除いた構成になっている。
【０１００】
ホットエレクトロン・トランジスタ９の磁気抵抗は、磁気記録媒体上を走査する際に変化し、これに対応した電圧変化をセンスアンプで検出することにより、磁気記録媒体に書き込まれた情報を読出すことができる。
【０１０１】
本実施形態の磁気ヘッドも、第２の実施形態の磁気メモリの場合と同様の理由により、高速な読出しが可能となる。また、磁性体トンネル接合素子よりも大きなＭＲ比が得られるので、読取りエラーを少なくできる。
【０１０２】
（第５の実施形態）
ところで、本発明者の研究によれば、磁性体電極として、数ｎｍ以下の磁性体超薄膜、または磁性体超薄膜と異種金属膜等のバリア膜との積層膜を用いることによって、ＭＲ比が増大することを見出した。
【０１０３】
先に説明したように、Ｆｅ、Ｃｏ，Ｎｉなどの強磁性金属中では、局在性の強いｄバンドと自由電子に近いｓバンドの電子が共存しているが、トンネル電流は主としてｓ電子によって担われている。
【０１０４】
磁性体トンネル接合のＭＲ比が実用電圧領域で著しく低下する原因は、電子のスピンが反転すること、つまり電子のスピンフリップ現象によるものと考えられる。したがって、実用電圧領域で大きなＭＲ比を示すトンネル接合を得るためには、何らかの方法でこのスピンフリップ現象を抑制することが必要である。
【０１０５】
ここで、図３に示したように、磁性体超薄膜中のｓ電子はトンネル接合において離散的なエネルギー準位に量子化されるが、本発明者は、そのエネルギー準位がアップスピン電子とダウンスピン電子とで異なっていることを今回初めて見出した。
【０１０６】
例えば、磁性体超薄膜として厚さ１ｎｍのＦｅ超薄膜を用いた場合、アップスピン電子とダウンスピン電子とのエネルギー準位の差は１ｅＶ程度という極めて大きな値となる。
【０１０７】
このように磁性体超薄膜からなる電極を用いた磁性体トンネル接合では、トンネル電子がスピン反転するためには、１ｅＶ程度のエネルギーが関与した非弾性散乱を受けなければならないため、スピンフリップ現象の起こる確率は著しく低くなる。
【０１０８】
このようなスピンフリップ現象の発生確率の低減化により、実用電圧領域で１０％を越える大きなＭＲ比を示す磁性体トンネル接合素子を実現することが可能となる。
【０１０９】
なお、磁性体超薄膜のみを電極に用いるとシート抵抗が増大してしまうので、図５に示したように、磁性体電極を磁性体超薄膜８と十分な厚さをもった導電性のバックアップ膜６とで構成することが好ましい。
【０１１０】
この場合も、先に説明したように、磁性体超薄膜８の２次元性（２ＤＥＧ）を損なわないためには、薄いバリア膜７を設けると良い。また、図６に示したように、磁性体超薄膜８の積層膜を用いることも可能であり、その場合にも薄いバリア膜７を設けると良い。
【０１１１】
以下、本実施形態のＧＭＲ素子（トンネル注入型のホットエレクトロン・トランジスタ）について具体的に説明する。
【０１１２】
本ＧＭＲ素子は、図１４に示すように、ｎ型Ｓｉからなるコレクタ２１（半導体領域）と、Ａｕ膜（膜厚：１．５ｎｍ）／Ｆｅ膜（膜厚：１．５ｎｍ）／Ａｌ膜（膜厚：１０ｎｍ）の積層膜からなるベース２２と、ＡｌＯ_ｘ 膜（トンネル絶縁膜）／Ｆｅ膜の積層膜からなるエミッタ２３（磁性体電極）と、Ａｕ膜（膜厚：１００ｎｍ）からなるバックアップ膜（不図示）が順次接合した構成になっている。
【０１１３】
このＧＭＲ素子のＭＲ比を調べたところ、その大きさはエミッタ２３のＦｅ膜の膜厚に大きく依存することが分かった。本発明者は、エミッタ２３のＦｅ膜の膜厚ｄが異なる３種類のＧＭＲ素子（ｄ＝０．８ｎｍ、１ｎｍ、２ｎｍ）を作成し、そのＭＲ比のエミッタ電圧依存性を調べた。
【０１１４】
図１５にその結果を示す。測定は温度７７Ｋの環境で行った。また、図１４に示すように、エミッタ２３にはコレクタ２１に対して負のエミッタ電圧を印加した。図１５から、同じエミッタ電圧でも、エミッタ２３のＦｅ膜の膜厚ｄが薄いほどＭＲ比は大きいことが分かる。
【０１１５】
また、本発明者は、ＭＲ比のエミッタ２３のＦｅ膜の膜厚依存性を調べた。図１６にその結果を示す。なお、エミッタ電圧は１Ｖである。また、図には、これまでに報告されているベース中の伝導パラメータを利用してＭＲ比から求めたスピン偏極度も示してある。
【０１１６】
図１６から、エミッタ（Ｆｅ）膜厚が５ｎｍでもＭＲ比は得られるが、２ｎｍを下ると、ＭＲ比は急激に増加し、例えば０．８ｎｍでは２倍（１００％）を越え、そして０．６ｎｍでＭＲ比が急激に低下し、０．５ｎｍを下るとＭＲ比が得られなくなる。
【０１１７】
また、図１６から、３ｎｍを越えるとスピン偏極度は０．０５（５％）未満になり、一方、２ｎｍを下るとスピン偏極度は急激に増加し、例えば０．８ｎｍでは０．４（４０％）を越えることが分かる。
【０１１８】
０．８ｎｍにおける結果は、これまでに報告されている数ｍＶの低電圧領域で測定されたトンネル電子のスピン偏極度にほぼ等しい。すなわち、エミッタ２３のＦｅ膜の膜厚を１ｎｍ以下にすると、１Ｖ程度の高い電圧を印加しても電子はほとんどスピンフリップせずにトンネルリングするため、スピン偏極した電子電流を流すことができる。
【０１１９】
以上の結果から、エミッタ（Ｆｅ）膜厚は、０．５ｎｍ以上５ｎｍ以下が好ましく、０．６ｎｍ以上２ｎｍ以下がより好ましい
かくして本実施形態によれば、エミッタ２３のＦｅ膜を薄膜化することによって、１Ｖ程度の高い電圧、つまり実用電圧領域の電圧をエミッタ２３に印加しても、十分に大きなＭＲ比を示すＧＭＲ素子を実現できるようになる。
【０１２０】
（第６の実施形態）
図１７は、本発明の第６の実施形態に係る磁性体トンネル接合素子を示す断面図である。
【０１２１】
これを製造工程に従って説明すると、まず、Ｓｉ（１００）基板３１（半導体領域）上に厚さ５ｎｍのＳｉＯ_２ 膜３２を形成する。次に基板温度を７７Ｋに設定し、ＳｉＯ_２ 膜３２上にＣｕからなるバックアップ膜３３を形成する。この後、室温に戻して１×１１０^−６Ｔｏｒｒの酸素雰囲気中での１分間の酸化により、バックアップ膜３３の表面にバリア膜３４を形成する。
【０１２２】
次にバリア膜３４上に下部電極としての厚さ０．８ｎｍのＣｏ超薄膜３５を真空蒸着により形成する。このとき、５００ｅの外部磁場を印加し、磁気容易軸が一方向に揃うようにする。また、真空蒸着の際の真空度、基板温度はそれぞれ１×１０^−８ｔｏｒｒ、７７Ｋである。
【０１２３】
次にＣｕ超薄膜３５上に厚さ１．２ｎｍのＡｌ膜（不図示）を形成した後、基板温度を室温に戻し、続いて酸素雰囲気中でのグロー放電により上記Ａ１膜を酸化し、Ａｌ_ｘ Ｏからなるトンネル絶縁膜３６を形成する。真空蒸着の際の真空度、基板温度は前と同じである。
【０１２４】
次に再び基板温度を７７Ｋに設定し、トンネル絶縁膜３６上に上部電極としての厚さ１ｎｍのＣｏ超薄膜３７を真空蒸着法により形成する。真空蒸着の際の真空度、基板温度は前と同じである。
【０１２５】
次に基板温度を室温に戻した後、Ｃｏ超薄膜３７の表面を１×１０^−６ｔｏｒｒの酸素雰囲気中に１分間曝すことにより、Ｃｏ超薄膜３７の表面にバリア膜３８を形成する。
【０１２６】
最後に、バリア膜３８上にＡｕからなる厚さ５０ｎｍのバックアップ膜３９を形成する。
【０１２７】
このようにして作成された磁性体トンネル接合素子の磁気抵抗効果を測定してみた。この測定は、交流ブリッジを用い、トンネル接合面内に外部磁場を印加して行なった。
【０１２８】
その結果、磁化曲線を反映した磁気抵抗特性が見られ、ＭＲ比は約３０％である。また、飽和磁場の下での接合抵抗の絶対値は約２０Ωであった。
【０１２９】
また、比較例として、本実施形態の磁性体トンネル接合素子の上部電極および下部電極３５，３７を厚さ５０ｎｍのＣｏ膜に置き換えたものを形成した。その形成は本実施形態のそれに準じる。
【０１３０】
同様な方法で比較例の磁気抵抗効果を評価したところ、飽和磁場下の接合抵抗は１８Ωであったが、ＭＲ比は５％であり、本実施形態の磁性体トンネル接合素子のＭＲ比よりもはるかに小さかった。
【０１３１】
（第７の実施形態）
図１８は、本発明の第７の実施形態に係る磁性体素子を示す断面図である。
【０１３２】
図中、４１は半導体基板（半導体領域）を示しており、この半導体基板４１の一端側には磁性体超薄膜からなる第１の磁性体電極４２が設けられ、他端側には磁性体超薄膜からなる第２の磁性体電極４３が設けられている。半導体基板としては、例えばＳｉ基板、磁性体超薄膜としては、例えばＦｅ超薄膜を用いる。
【０１３３】
半導体基板４１と第１の磁性体電極４２はショットキー接合を形成し、同様に半導体基板４１と第２の磁性体電極４３もショットキー接合を形成する。また、第１および第２の磁性体電極４２，４３の膜厚は、０．５ｎｍ以上（好ましくは０．６以上）５ｎｍ以下（好ましくは２ｎｍ以下）である。
【０１３４】
このように構成された磁性体素子によれば、第１の磁性体電極４２に第２の磁性体電極４３に対して負の電圧を印加すると、スピンフリップ現象を招かずに、第１の磁性体電極４２からショットキー接合を介して半導体基板４１に電子を注入できる。
【０１３５】
したがって、本実施形態によれば、第１の磁性体電極４２から第２の磁性体電極４３に向かってスピン偏極した電子電流Ｉｅを半導体基板４１内に流すことができるようになる。
【０１３６】
図１９に、本実施形態の変形例を示す。これは上下方向に電子電流Ｉｅを流す場合の構造を示している。また、本実施形態では、磁性体電極４２，４３として磁性体超薄膜の単層膜を用いたが、例えば磁性体超薄膜と電子に対してのバリア膜との積層膜を用いても良い。バリア膜としては、バリアとして働くものであればその膜種には制限はなく、例えば絶縁膜、半導体膜、半金属膜、異種金属膜を用いることができる。
【０１３７】
（第８の実施形態）
図２０は、本発明の第８の実施形態に係る磁性体素子を示す断面図である。なお、図１８の磁性体素子と対応する部分には図１８と同一符号を付してあり、詳細な説明は省略する（以下の他の実施形態についても同様）。
【０１３８】
本実施形態は、第１の磁性体電極（ソース電極）４２と第２の磁性体電極（ドレイン電極）４３との間の半導体基板４１の表面にゲート電極４４を設け、ＦＥＴを構成したことにある。半導体基板４１とゲート電極４４とはショットキー接合を形成する。
【０１３９】
本実施形態によれば、スピン偏極した電子電流Ｉｅをゲート電圧で制御することができるので、アップスピン電子とダウンスピン電子が混在した電子電流を制御する場合に比べて、相互コンダクタンスｇ_ｍ の大きなＦＥＴを実現できるようになる。
【０１４０】
なお、半導体基板４１上にゲート絶縁膜を形成し、その上に第１の磁性体電極（ソース電極）４２、第２の磁性体電極（ドレイン電極）４３、ゲート電極４４を形成しても良い。
【０１４１】
（第９の実施形態）
図２１は、本発明の第９の実施形態に係る磁性体素子を示す断面図である。
【０１４２】
本実施形態は本発明をＬＥＤに適用した例であり、第１の磁性体電極４２からアンドープの半導体基板４１にスピン偏極した電子電流Ｉｅを注入し、第２の磁性体電極４３から半導体基板４１にスピン偏極した正孔電流Ｉｈを注入する。これにより、電子と正孔との再結合が起こり、発光が生じる。
【０１４３】
本実施形態によれば、スピン偏極した電子電流Ｉｅと正孔電流Ｉｈとで再結合を起こすことができるので、アップスピン電子とダウンスピン電子が混在した電子電流と正孔電流とで再結合を起こす場合に比べて、発光に必要な電圧が低くて済む。
【０１４４】
なお、図中、４５をアンドープの半導体層を示している。この半導体層４５の印加電圧で再結合速度を制御することができる。
【０１４５】
（第１０の実施形態）
図２２は、本発明の第１０の実施形態に係る磁性体素子を示す断面図である。本実施形態も本発明をＬＥＤに適用した例である。
【０１４６】
本実施形態が第９の実施形態と異なる点は、不純物ドープ半導体を用いてＬＥＤを構成したことにある。第１の磁性体電極４２はｐ型半導体層４５ｐを介してｎ型半導体基板４１に接合している。また、アンドープの半導体層４５の代わりに、ｐ型半導体層４５ｐを用いている。本実施形態でも第９の実施形態と同様な効果が得られる。
【０１４７】
（第１１の実施形態）
図２３は、本発明の第１１の実施形態に係る磁性体素子を示す断面図である。本実施形態は本発明をレーザに適用した例である。図中、４６ｐはｐ型半導体層（半導体領域）、４６ｉはｉ型半導体層（半導体領域）、４６ｎはｎ型半導体層（半導体領域）を示している。
【０１４８】
本実施形態によれば、スピン偏極した電子電流Ｉｅと正孔電流Ｉｐとで反転分布を形成することができるので、アップスピン電子とダウンスピン電子が混在した電子電流と正孔電流とで反転分布を形成する場合に比べて、レーザ発振に必要な電圧（しきい値電圧）が低くなる。
【０１４９】
（第１２の実施形態）
図２４は、本発明の第１２の実施形態に係る磁性体素子を示す断面図である。本実施形態は本発明をスピン・トランジスタに適用した例である。図中、４７はトンネル絶縁膜、４８は常磁性体層（磁性体領域）を示している。常磁性体層４８は接地されている。
【０１５０】
本実施形態によれば、第１の磁性体電極４２からスピン偏極した電子電流Ｉｅを常磁性体層４８に注入できるので、アップスピン電子とダウンスピン電子が混在した電子電流を注入する場合に比べて、第２の磁性体電極４３と常磁性体層４８との間により大きな電圧差を発生させることができる。
【０１５１】
（第１３の実施形態）
図２５は、本発明の第１３の実施形態に係る磁性体素子を示す断面図である。本実施形態は本発明をホットエレクトロン・トランジスタに適用した例である。図中、４９は強磁性体層、５０は半導体層（半導体領域）を示している。
【０１５２】
本実施形態によれば、第１の磁性体電極４２からスピン偏極した電子電流Ｉｅをトンネル絶縁膜４７を介して半導体層５０に注入できるので、アップスピン電子とダウンスピン電子が混在した電子電流を注入する場合に比べて、より大きなＭＲ比が得られる。
【０１５３】
【発明の効果】
以上詳述したように本発明（請求項１〜７）によれば、遅延時間の原因となるＣＲ時定数を小さくできるので、読出し速度の速い磁気装置を実現できるようになる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る磁性体トンネル接合素子とＭＯＳトランジスタとからなる磁気メモリセルを示す図
【図２】磁性体の状態密度のスピン依存性を示す図
【図３】超薄膜の状態密度を示す図
【図４】絶縁膜をトンネルする電子の波数ベクトルを示す図
【図５】磁性体電極を示す断面図
【図６】他の磁性体電極を示す断面図
【図７】磁性体トンネル接合素子を示す断面図
【図８】図７の磁性体トンネル接合素子の磁気抵抗効果の測定結果を示す図
【図９】他の磁性体トンネル接合素子を示す断面図
【図１０】本発明の第２の実施形態に係る磁気メモリセルを示す図
【図１１】エミッタ層としてＮｂドープｎ型ＳＴＯ層を用いた場合のエミッタ電流のコレクタ・ベース間電圧の依存性を示す図
【図１２】本発明の第３の実施形態に係る磁気ヘッドを示す図
【図１３】本発明の第４の実施形態に係る磁気ヘッドを示す図
【図１４】本発明の第５の実施形態に係る磁性体素子を示す断面図
【図１５】ＭＲ比のエミッタ電圧依存性を示す図
【図１６】ＭＲ比のエミッタ中のＦｅ膜の膜厚依存性を示す図
【図１７】本発明の第６の実施形態に係る磁性体素子を示す断面図
【図１８】本発明の第７の実施形態に係る磁性体素子を示す断面図
【図１９】図７の磁性体素子の変形例を示す断面図
【図２０】本発明の第８の実施形態に係る磁性体素子を示す断面図
【図２１】本発明の第９の実施形態に係る磁性体素子を示す断面図
【図２２】本発明の第１０の実施形態に係る磁性体素子を示す断面図
【図２３】本発明の第１１の実施形態に係る磁性体素子を示す断面図
【図２４】本発明の第１２の実施形態に係る磁性体素子を示す断面図
【図２５】本発明の第１３の実施形態に係る磁性体素子を示す断面図
【図２６】従来のトンネル注入型のホットエレクトロン・トランジスタを示す図
【図２７】従来のショットキー注入型のホットエレクトロン・トランジスタを示す図
【図２８】従来の磁性体トンネル接合素子とＭＯＳトランジスタとからなる磁気メモリセルを示す図
【符号の説明】
１…磁性体トンネル接合素子（メモリセル本体，磁気ヘッド本体）
２…ＭＯＳトランジスタ
３…比較抵抗（第２の抵抗）
４…ゲート抵抗（第１の抵抗）
５…Ｓｉ基板
６…バックアップ膜
７…バリア膜
８…磁性体超薄膜
９…ホットエレクトロン・トランジスタ（メモリセル本体，磁気ヘッド本体）
１０…Ｓｉ基板
１１…ＳｉＯ_２ 膜
１２…Ｃｏ膜（下部電極）
１３…トンネル絶縁膜
１４…Ｃｏ超薄膜（上部電極）
１５…バリア膜
１６，１７…バックアップ膜
１８…バリア膜
２１…コレクタ（半導体領域）
２２…ベース
２３…エミッタ（磁性体電極）
３１…Ｓｉ基板（半導体領域）
３２…ＳｉＯ_２ 膜
３３，３９…バックアップ膜
３４，３８…バリア膜
３５，３７…Ｃｏ超薄膜（磁性体電極）
３６…トンネル絶縁膜
４１…半導体基板（半導体領域）
４１ｎ…ｎ型半導体基板（半導体領域）
４２，４３…磁性体電極
４４…ゲート電極
４５…半導体層（アンドープ）
４６ｐ…ｐ型半導体層（半導体領域）
４６ｎ…ｎ型半導体層（半導体領域）
４６ｉ…ｉ型半導体層（半導体領域）
４７…トンネル絶縁膜
４８…磁性体層（磁性体領域）
４９…強磁性体層
５０…半導体層（半導体領域）
Ｃ１…浮遊容量
Ｃ２…入力キャパシタンス
ＢＬ…ビット線
ＷＬ…ワード線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a magnetic device such as a magnetic head and a magnetic memory, and a magnetic element using a magnetic electrode as an electrode.
[0002]
[Prior art]
Higher densities and higher speeds of magnetic recording, in addition to improvements in magnetic recording media, often depend on advances in magnetic recording devices, and in particular, advances in magnetic heads used for writing and reading magnetic recording.
[0003]
In recent years, the size and capacity of magnetic recording media have been increasing. With such miniaturization and increase in capacity, the relative speed between the magnetic recording medium and the read magnetic head has decreased, and the time change rate (output) of the magnetic flux density has decreased.
[0004]
Even in such a case, a giant magnetoresistive head (GMR head) is being developed as a new type of reading magnetic head capable of extracting a large output. The GMR head has an excellent characteristic that the magnetoresistance ratio (MR ratio) is larger than that of the conventional MR head.
[0005]
As such a GMR head, for example, as shown in FIG. 26, a tunnel injection type hot electron transistor in which a base layer is formed of a magnetic laminated film and electrons are injected into the base layer through a tunnel junction. Those using are rapidly attracting attention.
[0006]
Further, as a GMR head exhibiting an even larger (several 100%) MR ratio by an order of magnitude, as shown in FIG. 27, for example, as shown in FIG. A device using a Schottky injection type hot electron transistor performed through a junction has also been reported.
[0007]
Information read from a magnetic recording medium by a magnetic head such as a GMR head is used after being read into a semiconductor memory (for example, DRAM or SRAM) in a computer.
[0008]
Although semiconductor memories have many excellent characteristics, they also have a major drawback that they consume a large amount of power for retaining information. In recent years, flash memories, FRAMs, and the like have been developed as semiconductor memories that do not require power for retaining information, but all have the major drawback that the number of times of rewriting is limited.
[0009]
On the other hand, the development of a magnetic memory (MRAM) that can be rewritten virtually infinitely has also begun. To achieve this, it is necessary to develop materials and devices that exhibit a large MR ratio.
[0010]
As a device exhibiting an MR ratio larger than that of a spin bulk film (a magnetic laminated film having two laminated layers), a magnetic tunnel junction device and a hot electron transistor in which the above-described base layer is formed of a magnetic laminated film are attracting attention. ing.
[0011]
In recent years, attempts have been made to form a magnetic head or a magnetic memory by using a magnetic tunnel junction element or a hot electron transistor alone and forming a magnetic head or a magnetic memory by combining them with a MOS transistor. Have been. The reason is that an element (GMR element) having a large MR ratio, such as a magnetic tunnel junction element or a hot electron transistor, has no power gain.
[0012]
However, a magnetic head and a magnetic memory configured by combining a GMR element and a MOS transistor have the following problems. This problem will be specifically described using a magnetic memory as an example.
[0013]
FIG. 28 shows a conventional magnetic memory cell including a magnetic tunnel junction element and a MOS transistor. This magnetic memory cell has a configuration in which a capacitor of a normal DRAM cell is replaced with a magnetic tunnel junction element.
[0014]
In the figure, 81 is a magnetic tunnel junction element, 82 is a MOS transistor, 83 is a comparative resistor, BL is a bit line, WL is a word line, and C1 is a stray capacitance by a bit line. The word line WL is connected to a constant voltage source (not shown). As the level of the constant voltage source, a value higher than the threshold voltage of the MOS transistor 82 is selected.
[0015]
The writing of the information (1, 0) is performed by making the magnetization of the magnetic tunnel junction element 81 parallel or anti-parallel by a magnetizing means (not shown).
[0016]
The information is read out by utilizing the fact that the magnetic resistance of the magnetic tunnel junction element 81 changes depending on whether the magnetization is parallel or antiparallel. The magnetoresistance is higher when the magnetization is antiparallel. The value of the magnetic resistance when the magnetization is antiparallel is selected as the value of the comparison resistor 83.
[0017]
Therefore, when the magnetization is antiparallel, the magnetic resistance is large, and the voltage drop due to the comparison resistance 83 detected by the sense amplifier is large. Conversely, when the magnetization is parallel, the magnetic resistance is small, and the voltage drop due to the comparison resistance 83 detected by the sense amplifier is small. In this manner, information can be read based on the magnitude of the voltage drop caused by the comparison resistor 83 detected by the sense amplifier.
[0018]
By the way, the stray capacitance C1 due to the bit line BL is about 300 fF. Therefore, in order to reduce the CR time constant and perform reading in a time of about nsec or less, the value of the comparison resistor 83 must be about 3 kΩ or less.
[0019]
This resistance value is 30 μΩcm per unit area when the size of the tunnel junction of the magnetic tunnel junction element 81 is 1 μm × 1 μm.²Which is an extremely small value.
[0020]
Here, the thickness of the tunnel insulating film is reduced to 30 μΩcm per unit area.²Although it is possible to form a tunnel junction, there is the following problem.
[0021]
Since reading by a sense amplifier requires a voltage change of several hundred mV, the tunnel junction must have a withstand voltage of several hundred mV.
[0022]
However, 30μΩcm per unit area²In the tunnel junction, since the tunnel insulating film is thin, dielectric breakdown easily occurs, and it is difficult to provide a withstand voltage of several 100 mV.
[0023]
Therefore, the conventional magnetic memory has a problem that it is difficult to increase the reading speed. Such a problem becomes more remarkable when the bonding size becomes submicron. The stray capacitance due to the word line (up to 300 fF)Also existsThere is no problem because a large resistor such as the comparison resistor 83 is not connected to the word line.
[0024]
By the way, the conventional magnetic tunnel junction device exhibits a large MR ratio exceeding 30% in a low voltage region of several tens mV or less. %.
[0025]
[Problems to be solved by the invention]
As described above, in the magnetic memory using the conventional magnetic memory cell including the magnetic tunnel junction element and the MOS transistor, the value of the comparative resistance connected to the bit line is determined by the magnetic tunnel junction when the magnetization is antiparallel. The resistance of the element was chosen.
[0026]
In order to increase the reading speed, it is necessary to reduce the value of the comparison resistor to reduce the CR time constant. For that purpose, it is necessary to make the tunnel insulating film of the magnetic tunnel junction element thin.
[0027]
However, when the thickness of the tunnel insulating film is reduced, dielectric breakdown easily occurs, and the voltage change required for reading by the sense amplifier may not be tolerated.become unable. For this reason, the conventional magnetic memory has a problem that it is difficult to increase the reading speed.
[0028]
Further, the conventional magnetic tunnel junction device has a problem that a sufficient MR ratio cannot be obtained due to a spin flip phenomenon of tunnel electrons in a practical voltage region of several hundred mV or more.
[0029]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a magnetic device using a GMR element with a high reading speed.
[0030]
Another object of the present invention is to provide a magnetic element capable of suppressing characteristic deterioration due to electron spin flip phenomenon in a practical voltage range.
[0032]
[Means for Solving the Problems]
[Constitution]
In order to achieve the above object, according to the present inventionThe magnetic device (magnetic memory) is characterized in that memory cells each comprising a MOS transistor and a GMR element connected to the gate of the MOS transistor and serving as a memory cell body are arranged in a matrix.1)
Here, a RAM can be realized by adding magnetization control means for controlling the direction of magnetization of the GMR element to the magnetic memory.2).
[0033]
Here, the gate of the MOS transistor is connected to a constant voltage source via a GMR element and grounded via a first resistor, the source of the MOS transistor is connected in series to a second resistor, and The drain is preferably grounded.3).
[0034]
Preferably, the GMR element is a magnetic tunnel junction element or a hot electron transistor having a base layer formed of a magnetic laminated film.4).
[0035]
In this case, it is preferable that the electrode of the magnetic tunnel junction element is formed of a magnetic film or a laminated film of a magnetic film and an insulating film.5). Here, the magnetic film is preferably a magnetic ultrathin film having a thickness of 5 nm or less.
[0036]
Preferably, the emitter layer of the hot electron transistor is formed of a strontium titanate film doped with Nb.6).
[0040]
[Action]
According to the present invention (claims 1 to 7), the CR time constant causing the delay time is determined by the resistance and the gate capacitance of the GMR element. This gate capacitance is sufficiently smaller than the wiring capacitance of a bit line or the like.
[0041]
Therefore, according to the present invention (claims 1 to 7), the CR time constant causing the delay time is sufficiently smaller than that of the related art, so that a magnetic device with a high read speed can be realized.
[0045]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings.
[0046]
(1st Embodiment)
FIG. 1 shows a magnetic memory cell including a magnetic tunnel junction device and a MOS transistor according to the first embodiment of the present invention.
[0047]
In the figure, 1 is a magnetic tunnel junction element, 2 is a MOS transistor, 3 is a comparative resistor, and 4 is a resistor (gate resistor) for generating a gate voltage. Further, BL is a bit line, WL is a word line, C1 is a stray capacitance due to the bit line, and C2 is an input capacitance of the MOS transistor 2.
[0048]
The word line WL is connected to a constant voltage source (not shown), and the level of the constant voltage source is selected to be higher than the threshold voltage of the MOS transistor 2. As the value of the gate resistance 4, the value of the magnetic resistance when the magnetization of the magnetic tunnel junction element 1 is parallel is selected. The magnetization of the magnetic tunnel junction element 1 is performed by magnetizing means (not shown) (for example, a magnetic field is generated by flowing a current through a wiring).
[0049]
The magnetic memory cell of the present embodiment is mainly different from the conventional magnetic memory cell shown in FIG. 16 in that one end of the magnetic tunnel junction element 1 is connected to the gate of the MOS transistor 2 and the other end is connected to the word line WL. Being connected.
[0050]
Since the input capacitance C2 of the MOS transistor 2 is about 1 fF, even if the magnetic resistance of the magnetic tunnel junction element 1 when the magnetization is parallel is about 1 MΩ, the time constant between the input capacitance C2 and the magnetic tunnel junction element 1 is The determined information reading delay time is about nsec.
[0051]
On the other hand, since the comparative resistance 3 is not connected to the magnetic tunnel junction element 81 unlike the conventional comparative resistance 83, it can be arbitrarily reduced as long as it is larger than the ON resistance of the MOS transistor 2. For this reason, even if the value of the stray capacitance C1 is 300 fF, the delay time for reading information determined by the time constant of the stray capacitance C1 and the comparison resistor 3 is about nsec.
[0052]
Thus, according to the present embodiment, the delay time of reading information can be suppressed to about nsec, so that a magnetic memory cell using a GMR element capable of reading information at high speed can be realized. Further, by arranging such magnetic memory cells in a matrix, a high-speed magnetic memory device (RAM) that can read information in about nsec can be realized. In the case of a ROM, no magnetizing means is required.
[0053]
By the way, although the MR ratio of the magnetic tunnel junction element reported at present is about 20% at room temperature, since the threshold voltage and the gain of the MOS transistor vary, the information content of the memory cell is correctly determined. Therefore, it is desirable to use a GMR element having a large MR ratio.
[0054]
Recently, as a GMR element having a large MR ratio, LaSrMnO₃Attention has been focused on a magnetic tunnel junction device using a magnetic electrode made of an oxide magnetic material such as the above. In these oxide magnetic materials, a large MR ratio can be obtained because the conduction electrons are almost 100% spin-polarized.
[0055]
However, there is a concern that this type of magnetic tunnel junction device will be put to practical use because it operates only at a low temperature and a large magnetic field is required for magnetization reversal.
[0056]
Under such circumstances, according to the research by the inventors, the MR ratio is increased by using a magnetic ultrathin film of several nm or less or a laminated film of a magnetic ultrathin film and an insulating film as a magnetic electrode. I found out. The principle will be described below.
[0057]
As shown in FIG. 2, in a ferromagnetic metal such as Fe, Co, and Ni, a highly localized d-band and an s-band electron close to a free electron coexist. As can be seen from FIG. 2, the electrons in the d-band have a spin polarization close to 100%, but the polarizability of the electrons in the s-band is low.
[0058]
From this, it is considered that the reason why the MR ratio of a magnetic tunnel junction element using a magnetic electrode made of a ferromagnetic metal is as small as about 20% is that s electrons having a small polarizability make a large contribution to a tunnel current. Therefore, it is considered that the MR ratio can be increased by reducing the contribution of s electrons to the tunnel current in some way.
[0059]
By the way, in an ultrathin film having a thickness of several nm, as is well known, the motion of electrons in the film thickness direction (z direction) is quantized, and the energy is
(Equation 1)

[0060]
, And the state density becomes stepwise as shown in FIG. In the equation (1), 1 represents the film thickness. On the other hand, the angle dependence of the tunnel current
(Equation 2)

[0061]
In consideration of the above, the wave vector of the electron tunneling through the insulating film is substantially perpendicular to the tunnel junction surface (θ as shown in FIG. 4)._c3 to 10 °), indicating that only the shaded portions of the state in FIG. 3 contribute to the tunnel current. In equation (2), s indicates the thickness of the tunnel barrier.
[0062]
Here, the energy width of the hatched portion is about 100 meV, and when l = 4 nm, the Fermi energy E_FIs about 5 eV, the Fermi energy E_FThe energy interval near the hatched portion is as large as about 1.0 eV. That is, s electrons in the magnetic ultrathin film behave like electrons in the insulating film at the tunnel junction, and do not contribute to the tunnel current.
[0063]
Although the thickness of the magnetic ultrathin film is set to 4 nm here, the tunnel current can be reduced if the thickness is generally set to 5 nm or less. In short, Fermi Energy E_FIt is sufficient to select a thin thickness in which the energy interval in the shaded portion nearby becomes large and s electrons do not contribute to the tunnel current.
[0064]
However, if only a magnetic ultrathin film is used as an electrode, the sheet resistance increases. Therefore, as shown in FIG. 6 is preferable.
[0065]
At this time, it is necessary to provide the barrier film 7 made of an insulator between the magnetic ultrathin film 8 and the backup film 6 in order not to impair the two-dimensionality (2DEG) of the magnetic ultrathin film 8. The thickness of the barrier film 7 must be sufficiently smaller than that of the tunnel insulating film. In the figure, reference numeral 5 denotes a Si substrate.
[0066]
Further, as can be understood from the above description, it is possible to use not only one layer of the magnetic ultrathin film but also a laminated film of the magnetic ultrathin film 8 as shown in FIG. Also in that case, the thickness of the barrier film 7 needs to be sufficiently thinner than that of the tunnel insulating film.
[0067]
As the magnetic tunnel junction element 1, for example, as shown in FIG. 7, an element having a Co / AlOx / Co tunnel junction is exemplified.
[0068]
This will be described in accordance with a manufacturing process. First, a 5 nm thick SiO 2 is formed on the surface of a Si (100) substrate 10.₂The film 11 is formed by a thermal oxidation method.
[0069]
Next, SiO₂A Co film 12 having a thickness of 50 nm and a width of 0.2 mm as a lower electrode is formed on the film 11 by a vacuum evaporation method. Here, the degree of vacuum and the substrate temperature at the time of vacuum deposition were 1 × 10^-8set tor, 77K. Further, an external magnetic field of 500 Oe is applied so that the magnetic easy axis is aligned in one direction.
[0070]
Next, after forming an Al film having a thickness of 1.2 nm on the Co film 12 by a vacuum evaporation method, the substrate temperature is returned to room temperature, and then the A1 film is oxidized by a glow discharge in an oxygen atmosphere, and_xA tunnel insulating film 13 made of O is formed. The degree of vacuum and the substrate temperature during vacuum deposition are the same as before.
[0071]
Next, the substrate temperature is again set to 77 K, and a 4 nm-thick and 0.2 nm-wide ultra-thin Co film 14 as an upper electrode is formed on the tunnel insulating film 13 by a vacuum evaporation method. The degree of vacuum at the time of vacuum deposition is the same as before.
[0072]
Next, after the substrate temperature was returned to room temperature, the surface of the^-3The barrier film 15 is formed on the surface of the ultra-thin Co film 14 by exposing it to an oxygen atmosphere of torr for one minute.
[0073]
Finally, a backup film 16 made of Au and having a thickness of 50 nm is formed on the barrier film 15.
[0074]
The magnetoresistance effect of the magnetic tunnel junction device thus manufactured was measured. This measurement was performed by using an AC bridge and applying an external magnetic field within the tunnel junction surface.
[0075]
FIG. 8 shows the measurement results. Magnetoresistance characteristics reflecting the magnetization curve are observed, and the MR ratio is about 26%. The absolute value of the junction resistance under a saturation magnetic field was about 20Ω.
[0076]
FIG. 9 shows a cross-sectional view of another magnetic tunnel junction device made of a Co / AlOx / Co tunnel junction. Parts corresponding to those of the magnetic tunnel junction element in FIG. 7 are denoted by the same reference numerals as in FIG. 7, and detailed description is omitted.
[0077]
The difference from the magnetic tunnel junction device of FIG. 7 lies in that not only the upper electrode but also the lower electrode is made of the ultra-thin Co film 14, and the backup film 17 and the barrier film 18 are formed on the lower electrode side. As the backup film 17, a Cu film having a thickness of 50 nm is used. Thus, a tunnel junction is also formed on the lower electrode side.
[0078]
The Cu film serving as the backup film 17 is formed by a vacuum deposition method at a substrate temperature of 77 K, and the barrier film 18 is returned to room temperature after the backup film 17 is formed.^-3It is formed by exposing to an oxygen atmosphere of torr for one minute. The other method of forming the film is the same as that of the device of FIG.
[0079]
When the magnetoresistance effect of this element was measured in the same manner as in the case of the magnetic tunnel junction element of FIG. 7, the junction resistance under a saturation magnetic field was 22Ω, but the MR ratio was increased to 35%.
[0080]
Further, as a comparative example, a magnetic tunnel junction device was formed in which the ultra-thin 4 nm-thick Co film as the upper electrode was replaced with a 50 nm-thick Co film in the magnetic tunnel junction device of FIG. The formation is similar to that of the magnetic tunnel junction device of FIG.
[0081]
When the magnetoresistance effect of this device was measured in the same manner as in the magnetic tunnel junction device of FIG. 7, the junction resistance under a saturation magnetic field was 18Ω, but the MR ratio was 15%. Was smaller than the MR ratio of the device.
[0082]
(Second embodiment)
FIG. 10 shows a magnetic memory cell according to the second embodiment of the present invention. Note that portions corresponding to those of the magnetic memory cell of FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted.
[0083]
This embodiment is an example in which a hot electron transistor is used as a GMR element. A hot electron transistor is a GMR element that exhibits a higher MR ratio than a magnetic tunnel junction element. The MR ratio of hot electron transistors is over 200%. Therefore, it is easier to correctly read the information of the memory cell, and reading errors can be reduced.
[0084]
However, the current gain of a hot electron transistor is small, and in the case of a common base, the collector current is reduced by one digit or more than the emitter current.
[0085]
For this reason, in order to operate at a high speed of about ns, the hot electron transistor 9 (collector) is connected to the gate of the MOS transistor 2 as shown in FIG. Is preferred.
[0086]
By the way, since the current gain at the common base is estimated to be at most about 0.1, it is preferable to increase the emitter current for high-speed operation.
[0087]
In order to flow a large emitter current, the Schottky injection type hot electron transistor of FIG. 27 is more preferable than the tunnel injection type hot electron transistor of FIG.
[0088]
When the hot electron transistor of FIG. 26 is formed, it is formed on the same substrate as the MOS transistor, so that Si is used as the material of the collector layer. The collector layer may be a Si layer, but the emitter layer is preferably a semiconductor layer satisfying the following conditions. That is, a semiconductor layer having a wide band gap and a low deposition temperature is preferable.
[0089]
The reason why the film formation temperature is preferably low is that, since the emitter layer is formed after the base layer, if the film formation temperature is high, the characteristics of the magnetic laminated film as the base layer may be deteriorated.
[0090]
The reason why the band gap is preferably wide is that quantum mechanical reflection at the base / collector interface can be reduced by using electrons having high energy.
[0091]
As a semiconductor layer satisfying these two conditions, an n-type strontium titanate (STO) layer doped with Nb (Nb-doped n-type STO layer) is most suitable.
[0092]
FIG. 11 shows an emitter current (I) when an Nb-doped n-type STO layer is used as the emitter layer._E) Collector-base voltage (V_EB).
[0093]
According to the figure, by applying a voltage of about 0.9 V between the collector and the base, 10³A / cm²It can be seen that a certain amount of emitter current flows. In this case, if the current gain is 0.1, the read time is 0.1 ns, and even if the current gain is 0.01, the read time is 1 ns.
[0094]
(Third embodiment)
FIG. 12 shows a magnetic head according to the third embodiment of the present invention. Note that portions corresponding to those of the magnetic memory cell of FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted.
[0095]
The magnetic head of this embodiment has a configuration in which the bit line BL, word line WL, and magnetizing means are removed from the magnetic memory cell of FIG.
[0096]
The magnetic resistance of the magnetic tunnel junction element 1 changes when scanning over the magnetic recording medium, and a voltage change corresponding to the change is detected by a sense amplifier, so that information written on the magnetic recording medium can be read. it can.
[0097]
The magnetic head of the present embodiment also enables high-speed reading for the same reason as in the case of the magnetic memory of the first embodiment.
[0098]
(Fourth embodiment)
FIG. 13 shows a magnetic head according to the fourth embodiment of the present invention. Parts corresponding to those of the magnetic memory cell in FIG. 10 are denoted by the same reference numerals as those in FIG. 10, and detailed description is omitted.
[0099]
The magnetic head of this embodiment has a configuration in which the bit line BL, word line WL, and magnetizing means are removed from the magnetic memory cell of FIG.
[0100]
The magnetic resistance of the hot electron transistor 9 changes when scanning over the magnetic recording medium, and by detecting a voltage change corresponding to the change with a sense amplifier, it is possible to read information written on the magnetic recording medium. it can.
[0101]
The magnetic head of the present embodiment can also perform high-speed reading for the same reason as the magnetic memory of the second embodiment. Further, since a larger MR ratio than that of the magnetic tunnel junction element can be obtained, reading errors can be reduced.
[0102]
(Fifth embodiment)
By the way, according to the research of the present inventor, the MR ratio is increased by using a magnetic ultrathin film of several nm or less or a laminated film of a magnetic ultrathin film and a barrier film such as a dissimilar metal film as a magnetic electrode. Found to increase.
[0103]
As described above, in a ferromagnetic metal such as Fe, Co, and Ni, a highly localized d-band and an s-band electron close to a free electron coexist, but the tunnel current mainly depends on the s-electron. Is being carried.
[0104]
It is considered that the cause of the remarkable decrease in the MR ratio of the magnetic tunnel junction in the practical voltage range is that the electron spin is reversed, that is, the electron spin-flip phenomenon. Therefore, in order to obtain a tunnel junction having a large MR ratio in a practical voltage region, it is necessary to suppress this spin flip phenomenon by some method.
[0105]
Here, as shown in FIG. 3, the s electrons in the magnetic ultrathin film are quantized into discrete energy levels at the tunnel junction. For the first time, we have found that they are different from downspin electrons.
[0106]
For example, when an ultra-thin Fe thin film having a thickness of 1 nm is used as the ultra-thin magnetic material, the difference between the energy levels of up-spin electrons and down-spin electrons is an extremely large value of about 1 eV.
[0107]
As described above, in a magnetic tunnel junction using an electrode made of a magnetic ultrathin film, in order for the tunnel electrons to undergo spin inversion, they must undergo inelastic scattering involving energy of about 1 eV. The probability of occurrence will be significantly lower.
[0108]
By reducing the probability of occurrence of such a spin flip phenomenon, it becomes possible to realize a magnetic tunnel junction element having a large MR ratio exceeding 10% in a practical voltage region.
[0109]
Note that if only the magnetic ultrathin film is used as the electrode, the sheet resistance will increase. Therefore, as shown in FIG. It is preferable that the film 6 and the film 6 are formed.
[0110]
Also in this case, as described above, a thin barrier film 7 is preferably provided in order not to impair the two-dimensionality (2DEG) of the magnetic ultrathin film 8. Further, as shown in FIG. 6, it is also possible to use a laminated film of the magnetic ultrathin film 8, and in such a case, it is preferable to provide a thin barrier film 7.
[0111]
Hereinafter, the GMR element (tunnel injection type hot electron transistor) of the present embodiment will be specifically described.
[0112]
As shown in FIG. 14, the present GMR element has a collector 21 (semiconductor region) made of n-type Si, an Au film (thickness: 1.5 nm) / Fe film (thickness: 1.5 nm) / Al film ( A base 22 made of a laminated film having a thickness of 10 nm) and AlO_xThe structure is such that an emitter 23 (magnetic electrode) formed of a film (tunnel insulating film) / Fe film and a backup film (not shown) formed of an Au film (thickness: 100 nm) are sequentially bonded.
[0113]
When the MR ratio of this GMR element was examined, it was found that the size greatly depends on the thickness of the Fe film of the emitter 23. The present inventor produced three types of GMR elements (d = 0.8 nm, 1 nm, 2 nm) in which the thickness d of the Fe film of the emitter 23 was different, and examined the dependence of the MR ratio on the emitter voltage.
[0114]
FIG. 15 shows the result. The measurement was performed in a 77K temperature environment. Further, as shown in FIG. 14, a negative emitter voltage was applied to the emitter 23 with respect to the collector 21. From FIG. 15, it can be seen that, even at the same emitter voltage, the MR ratio increases as the thickness d of the Fe film of the emitter 23 decreases.
[0115]
Further, the inventor examined the dependency of the MR ratio on the thickness of the Fe film of the emitter 23. FIG. 16 shows the result. The emitter voltage is 1V. The figure also shows the spin polarization determined from the MR ratio using the conduction parameters in the base reported so far.
[0116]
From FIG. 16, the MR ratio can be obtained even when the thickness of the emitter (Fe) film is 5 nm, but when it falls below 2 nm, the MR ratio sharply increases. For example, at 0.8 nm, the MR ratio exceeds twice (100%). At 6 nm, the MR ratio sharply decreases, and at 0.5 nm, the MR ratio cannot be obtained.
[0117]
Also figure16From 3 nm, the spin polarization is less than 0.05 (5%) when the thickness exceeds 3 nm, while the spin polarization sharply increases when the thickness is below 2 nm, and exceeds 0.4 (40%) at 0.8 nm, for example. You can see that.
[0118]
The result at 0.8 nm is approximately equal to the spin polarization of tunneling electrons measured in the low voltage region of a few mV reported so far. In other words, when the thickness of the Fe film of the emitter 23 is set to 1 nm or less, even if a high voltage of about 1 V is applied, electrons are tunneled with almost no spin flip, so that a spin-polarized electron current can flow. .
[0119]
From the above results, the emitter (Fe) film thickness is preferably 0.5 nm or more and 5 nm or less, more preferably 0.6 nm or more and 2 nm or less.
Thus, according to the present embodiment, by reducing the thickness of the Fe film of the emitter 23, the GMR element exhibiting a sufficiently large MR ratio even when a high voltage of about 1 V, that is, a voltage in a practical voltage range is applied to the emitter 23. Can be realized.
[0120]
(Sixth embodiment)
FIG. 17 is a sectional view showing a magnetic tunnel junction device according to the sixth embodiment of the present invention.
[0121]
This will be described in accordance with a manufacturing process. First, a 5 nm-thick SiO 2 is formed on a Si (100) substrate 31 (semiconductor region).₂A film 32 is formed. Next, the substrate temperature was set to 77 K,₂A backup film 33 made of Cu is formed on the film 32. Thereafter, the temperature is returned to room temperature and 1 × 110^-6The barrier film 34 is formed on the surface of the backup film 33 by oxidation for one minute in an oxygen atmosphere of Torr.
[0122]
Next, a 0.8 nm thick ultra-thin Co film 35 as a lower electrode is formed on the barrier film 34 by vacuum evaporation. At this time, an external magnetic field of 500e is applied so that the magnetic easy axis is aligned in one direction. In addition, the degree of vacuum and the substrate temperature at the time of vacuum deposition were 1 × 10^-8torr, 77K.
[0123]
Next, after forming an Al film (not shown) having a thickness of 1.2 nm on the Cu ultra-thin film 35, the substrate temperature is returned to room temperature, and then the A1 film is oxidized by glow discharge in an oxygen atmosphere, and_xA tunnel insulating film 36 made of O is formed. The degree of vacuum and the substrate temperature during vacuum deposition are the same as before.
[0124]
Next, the substrate temperature is set to 77K again, and a 1 nm thick ultra-thin Co film 37 as an upper electrode is formed on the tunnel insulating film 36 by a vacuum evaporation method. The degree of vacuum and the substrate temperature during vacuum deposition are the same as before.
[0125]
Next, after the substrate temperature was returned to room temperature, the surface of the Co^-6The barrier film 38 is formed on the surface of the ultra-thin Co film 37 by exposing it to an oxygen atmosphere of torr for one minute.
[0126]
Finally, a backup film 39 made of Au and having a thickness of 50 nm is formed on the barrier film 38.
[0127]
The magnetoresistance effect of the magnetic tunnel junction device thus manufactured was measured. This measurement was performed by using an AC bridge and applying an external magnetic field within the tunnel junction surface.
[0128]
As a result, a magnetoresistance characteristic reflecting the magnetization curve is observed, and the MR ratio is about 30%. The absolute value of the junction resistance under a saturation magnetic field was about 20Ω.
[0129]
As a comparative example, a magnetic tunnel junction device of the present embodiment in which the upper electrode and the lower electrodes 35 and 37 were replaced with a 50 nm-thick Co film was formed. The formation is similar to that of the present embodiment.
[0130]
When the magnetoresistance effect of the comparative example was evaluated by the same method, the junction resistance under a saturation magnetic field was 18Ω, but the MR ratio was 5%, which was higher than the MR ratio of the magnetic tunnel junction device of the present embodiment. It was much smaller.
[0131]
(Seventh embodiment)
FIG. 18 is a sectional view showing a magnetic element according to the seventh embodiment of the present invention.
[0132]
In the figure, reference numeral 41 denotes a semiconductor substrate (semiconductor region). A first magnetic electrode 42 made of a magnetic ultrathin film is provided at one end of the semiconductor substrate 41, and a magnetic superconductor is formed at the other end. A second magnetic electrode 43 made of a thin film is provided. For example, a Si substrate is used as a semiconductor substrate, and an Fe ultrathin film is used as a magnetic ultrathin film.
[0133]
The semiconductor substrate 41 and the first magnetic electrode 42 form a Schottky junction, and similarly, the semiconductor substrate 41 and the second magnetic electrode 43 also form a Schottky junction. The thickness of the first and second magnetic electrodes 42 and 43 is 0.5 nm or more (preferably 0.6 or more) and 5 nm or less (preferably 2 nm or less).
[0134]
According to the magnetic element configured as described above, when a negative voltage is applied to the first magnetic electrode 42 to the second magnetic electrode 43, the first magnetic electrode 42 does not cause the spin flip phenomenon, Electrons can be injected from the body electrode 42 into the semiconductor substrate 41 via the Schottky junction.
[0135]
Therefore, according to the present embodiment, the spin-polarized electron current Ie can flow from the first magnetic electrode 42 toward the second magnetic electrode 43 into the semiconductor substrate 41.
[0136]
FIG. 19 shows a modification of the present embodiment. This shows a structure in which the electron current Ie flows in the vertical direction. Further, in the present embodiment, a single-layer film of a magnetic ultra-thin film is used as the magnetic electrodes 42 and 43, but a laminated film of a magnetic ultra-thin film and a barrier film for electrons may be used, for example. The type of the barrier film is not limited as long as it functions as a barrier. For example, an insulating film, a semiconductor film, a semimetal film, or a dissimilar metal film can be used.
[0137]
(Eighth embodiment)
FIG. 20 is a sectional view showing a magnetic element according to the eighth embodiment of the present invention. The parts corresponding to those of the magnetic element in FIG. 18 are denoted by the same reference numerals as those in FIG. 18, and detailed description is omitted (the same applies to other embodiments described below).
[0138]
In this embodiment, a gate electrode 44 is provided on the surface of a semiconductor substrate 41 between a first magnetic material electrode (source electrode) 42 and a second magnetic material electrode (drain electrode) 43 to form an FET. is there. The semiconductor substrate 41 and the gate electrode 44 form a Schottky junction.
[0139]
According to this embodiment, since the spin-polarized electron current Ie can be controlled by the gate voltage, the mutual conductance g can be reduced as compared with the case of controlling the electron current in which up-spin electrons and down-spin electrons coexist._mCan be realized.
[0140]
Note that a gate insulating film may be formed on the semiconductor substrate 41, and a first magnetic material electrode (source electrode) 42, a second magnetic material electrode (drain electrode) 43, and a gate electrode 44 may be formed thereon. .
[0141]
(Ninth embodiment)
FIG. 21 is a sectional view showing a magnetic element according to the ninth embodiment of the present invention.
[0142]
The present embodiment is an example in which the present invention is applied to an LED, in which a spin-polarized electron current Ie is injected from a first magnetic electrode 42 into an undoped semiconductor substrate 41, and a semiconductor substrate is injected from a second magnetic electrode 43. A spin-polarized hole current Ih is injected into 41. Thereby, recombination of electrons and holes occurs, and light emission occurs.
[0143]
According to the present embodiment, recombination can be caused by the spin-polarized electron current Ie and the hole current Ih. Therefore, recombination is performed by an electron current and a hole current in which up-spin electrons and down-spin electrons are mixed. The voltage required for light emission can be lower than in the case where the light emission occurs.
[0144]
In the figure, reference numeral 45 denotes an undoped semiconductor layer. The recombination speed can be controlled by the voltage applied to the semiconductor layer 45.
[0145]
(Tenth embodiment)
FIG. 22 is a sectional view showing a magnetic element according to the tenth embodiment of the present invention. This embodiment is also an example in which the present invention is applied to an LED.
[0146]
This embodiment is different from the ninth embodiment in that an LED is formed using an impurity-doped semiconductor. The first magnetic electrode 42 is joined to the n-type semiconductor substrate 41 via the p-type semiconductor layer 45p. Further, a p-type semiconductor layer 45p is used instead of the undoped semiconductor layer 45. In this embodiment, the same effects as in the ninth embodiment can be obtained.
[0147]
(Eleventh embodiment)
FIG. 23 is a sectional view showing a magnetic element according to the eleventh embodiment of the present invention. This embodiment is an example in which the present invention is applied to a laser. In the figure, 46p indicates a p-type semiconductor layer (semiconductor region), 46i indicates an i-type semiconductor layer (semiconductor region), and 46n indicates an n-type semiconductor layer (semiconductor region).
[0148]
According to the present embodiment, an inversion distribution can be formed by the spin-polarized electron current Ie and the hole current Ip. Therefore, the inversion is performed by the electron current and the hole current in which the up spin electrons and the down spin electrons are mixed. The voltage (threshold voltage) required for laser oscillation is lower than in the case of forming a distribution.
[0149]
(Twelfth embodiment)
FIG. 24 is a sectional view showing a magnetic element according to the twelfth embodiment of the present invention. This embodiment is an example in which the present invention is applied to a spin transistor. In the figure, 47 indicates a tunnel insulating film, and 48 indicates a paramagnetic layer (magnetic region). The paramagnetic layer 48 is grounded.
[0150]
According to the present embodiment, since the spin-polarized electron current Ie can be injected from the first magnetic electrode 42 into the paramagnetic layer 48, the injection of an electron current in which up-spin electrons and down-spin electrons coexist is performed. In comparison, a larger voltage difference can be generated between the second magnetic electrode 43 and the paramagnetic layer 48.
[0151]
(Thirteenth embodiment)
FIG. 25 is a sectional view showing a magnetic element according to a thirteenth embodiment of the present invention. This embodiment is an example in which the present invention is applied to a hot electron transistor. In the figure, 49 indicates a ferromagnetic layer, and 50 indicates a semiconductor layer (semiconductor region).
[0152]
According to the present embodiment, the spin-polarized electron current Ie from the first magnetic electrode 42 can be injected into the semiconductor layer 50 via the tunnel insulating film 47, so that an electron current in which up-spin electrons and down-spin electrons coexist is mixed. Larger MR ratio can be obtained than in the case of implanting.
[0153]
【The invention's effect】
As described above in detail, according to the present invention (claims 1 to 7), the CR time constant causing the delay time can be reduced, so that a magnetic device with a high read speed can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a magnetic memory cell including a magnetic tunnel junction device and a MOS transistor according to a first embodiment of the present invention.
FIG. 2 is a diagram showing the spin dependence of the density of states of a magnetic material.
FIG. 3 is a diagram showing the density of states of an ultrathin film.
FIG. 4 is a diagram showing a wave number vector of electrons tunneling through an insulating film.
FIG. 5 is a sectional view showing a magnetic material electrode.
FIG. 6 is a cross-sectional view showing another magnetic electrode.
FIG. 7 is a sectional view showing a magnetic tunnel junction element.
8 is a view showing a measurement result of a magnetoresistance effect of the magnetic tunnel junction device of FIG. 7;
FIG. 9 is a sectional view showing another magnetic tunnel junction element.
FIG. 10 is a diagram showing a magnetic memory cell according to a second embodiment of the present invention;
FIG. 11 is a diagram showing the dependence of the emitter current on the collector-base voltage when an Nb-doped n-type STO layer is used as the emitter layer.
FIG. 12 is a diagram showing a magnetic head according to a third embodiment of the present invention.
FIG. 13 is a view showing a magnetic head according to a fourth embodiment of the present invention.
FIG. 14 is a sectional view showing a magnetic element according to a fifth embodiment of the present invention.
FIG. 15 is a diagram showing the emitter voltage dependence of the MR ratio.
FIG. 16 is a diagram showing the dependency of the MR ratio on the thickness of the Fe film in the emitter.
FIG. 17 is a sectional view showing a magnetic element according to a sixth embodiment of the present invention.
FIG. 18 is a sectional view showing a magnetic element according to a seventh embodiment of the present invention.
FIG. 19 is a sectional view showing a modification of the magnetic element shown in FIG. 7;
FIG. 20 is a sectional view showing a magnetic element according to an eighth embodiment of the present invention.
FIG. 21 is a sectional view showing a magnetic element according to a ninth embodiment of the present invention.
FIG. 22 is a sectional view showing a magnetic element according to a tenth embodiment of the present invention.
FIG. 23 is a sectional view showing a magnetic element according to an eleventh embodiment of the present invention;
FIG. 24 is a sectional view showing a magnetic element according to a twelfth embodiment of the present invention;
FIG. 25 is a sectional view showing a magnetic element according to a thirteenth embodiment of the present invention;
FIG. 26 is a diagram showing a conventional tunnel injection type hot electron transistor.
FIG. 27 is a view showing a conventional Schottky injection type hot electron transistor.
FIG. 28 shows a conventional magnetic memory cell including a magnetic tunnel junction element and a MOS transistor.
[Explanation of symbols]
1. Magnetic tunnel junction element (memory cell body, magnetic head body)
2 ... MOS transistor
3: Comparison resistance (second resistance)
4: Gate resistance (first resistance)
5 ... Si substrate
6. Backup film
7 ... barrier film
8 ... magnetic thin film
9 hot electron transistor (memory cell body, magnetic head body)
10 ... Si substrate
11 ... SiO₂film
12 ... Co film (lower electrode)
13 ... Tunnel insulating film
14 Co ultra-thin film (upper electrode)
15 ... Barrier film
16, 17 ... backup film
18 ... Barrier film
21: Collector (semiconductor area)
22 ... Base
23 ... Emitter (magnetic electrode)
31 ... Si substrate (semiconductor area)
32 ... SiO₂film
33, 39 ... backup film
34, 38 ... barrier film
35,37 ... Co ultra-thin film (magnetic electrode)
36 ... Tunnel insulating film
41 ... Semiconductor substrate (semiconductor area)
41n n-type semiconductor substrate (semiconductor region)
42, 43 ... Magnetic electrode
44 ... Gate electrode
45 ... Semiconductor layer (undoped)
46p ... p-type semiconductor layer (semiconductor region)
46n... N-type semiconductor layer (semiconductor region)
46i ... i-type semiconductor layer (semiconductor region)
47 ... Tunnel insulating film
48 ... Magnetic layer (magnetic region)
49 ... ferromagnetic layer
50: semiconductor layer (semiconductor region)
C1: Stray capacitance
C2: Input capacitance
BL: bit line
WL: Word line

Claims (7)

A magnetic device, wherein memory cells each comprising a MOS transistor and a GMR element connected to the gate of the MOS transistor and serving as a memory cell body are arranged in a matrix. 2. The magnetic device according to claim 1, further comprising a magnetization control unit that controls a direction of magnetization of the GMR element. The gate of the MOS transistor is connected to a constant voltage source via the GMR element and grounded via a first resistor, and the source of the MOS transistor is connected to a second resistor having a lower resistance than the first resistor. 2. The magnetic device according to claim 1 , wherein the drain of the MOS transistor is grounded. 2. The magnetic device according to claim 1, wherein the GMR element is a magnetic tunnel junction element or a hot electron transistor having a base layer formed of a magnetic laminated film. The electrode of the magnetic tunnel junction element is a magnetic film in contact with a tunnel insulating film of the magnetic tunnel junction element , or a magnetic film in contact with the tunnel insulating film and a surface of the magnetic film in contact with the tunnel insulating film. 5. The magnetic device according to claim 4, wherein the magnetic device is formed of a laminated film including an insulating film formed on the opposite side of the magnetic device. The magnetic device according to claim 4, wherein the emitter layer of the hot electron transistor is formed of a strontium titanate film doped with Nb. A MOS transistor;
A GMR element connected to the gate of the MOS transistor and serving as a magnetic head body and
Comprising
The gate of the MOS transistor is connected to a constant voltage source via the GMR element and grounded via a first resistor, and the source of the MOS transistor is connected to a second resistor having a lower resistance than the first resistor. Wherein the drain of the MOS transistor is grounded.

Images