KR100418537B1 - Magnetic memory device - Google Patents

Abstract

The magnetic memory device includes a memory cell consisting of first and second tunnel junctions and a switch, each of the first and second tunnel junctions having a fixed layer in which the magnetization direction is fixed and a recording layer in which the magnetization direction changes according to an external magnetic field. It is formed by lamination. The first data line is connected to the first end of the first tunnel junction. The second data line is connected to the first end of the second tunnel junction. The bit line is connected to the second end of the first tunnel junction and the second end of the second tunnel junction via a switch.

Description

Magnetic Memory Device {MAGNETIC MEMORY DEVICE}

The present application claims priority to Japanese Patent Application No. Hei 11-357469, filed December 16, 1999, and Japanese Patent Application No. 2000-075168, filed March 17, 2000, which are priorities. The entire contents of are incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording technology using a ferromagnetic material, and more particularly to a magnetic memory device using a magnetic tunnel junction.

Magnetic random access memory (hereafter abbreviated as MRAM) is a solid state memory that can rewrite, retain, and read information at any time using the magnetization direction of a ferromagnetic material as an information recording medium. state memory). This MRAM records information by correlating binary coded information " 1 " and " 0 " according to whether the magnetization direction of the ferromagnetic material is parallel or antiparallel to the reference direction.

Recording information is written by switching the magnetization direction of the ferromagnetic material of each cell by a magnetic field generated by supplying a current to the write lines arranged in a cross stripe form. The power consumption during storage is in principle zero.

Stored information is a phenomenon in which the electrical resistance of a memory cell changes depending on the relative angle between the magnetization direction of the ferromagnetic material constituting the cell and the direction of the sensing current, or the relative angle of magnetization between a plurality of ferromagnetic layers, so-called magnetoresistance. It is read using a magneto resistance effect.

MRAM has the following advantages when compared with a conventional semiconductor memory.

(a) Completely nonvolatile, endurance cycles of 10 ¹⁵ or more are possible.

(b) Non-destructive reads are possible, and no refresh operation is required, thus reducing read cycles.

(c) Resistance to radiation is stronger than that of charge storage type memory cells.

It is expected that the degree of integration per unit area for MRAM and the write and read times are approximately equal to the density per unit area of DRAM and the write and read times. Therefore, it is further expected to apply MRAM to an external memory device, a wireless IC card, and a mobile personal computer (PC) for portable digital audio equipment by utilizing important nonvolatile features.

In the MDRAM having a recording capacity of 1 Mb, which is currently discussed for practical use, a Giant Magnetro-Resistance (hereinafter abbreviated as GMR effect) is adopted to read stored information. Examples of MRAMs using elements that exhibit the GMR effect (hereinafter abbreviated as GMR elements) are described in IEEE Trans. Mag., 33,3289 (1997).

The value of the GMR effect of the three layer film consisting of unbound NiFe / Cu / Co is approximately 6% to 8%. For example, in an MRAM cell using the above-described PseudoSpin-Valve structure, the distribution of magnetic direction during the reading of the recorded information is controlled, thereby effectively obtaining a resistance change of 5% or more. have. In general, however, the sheet resistance of the GMR element is approximately tens of Ω / μm 2. Therefore, even when a sheet resistance of 100 Ω / μm 2 and a resistance change rate of 5% are assumed, the output signal related to the sense current of 10 mA is only 5 mV. Currently, in a practically available MOS type field effect transistor, the value of the source-drain current I _ds is proportional to the ratio between the channel width W and the channel length L, so that the value of I _ds is W = 3.3. , L = 1 Is about 0.1 mA. Thus, the sense current value of 10 mA as used herein is a very excessive value for transistors with sub-micron dimensions.

In order to solve this problem, in a MRAM cell using a GMR element, a method of constructing a data line after connecting a plurality of GMR elements in series is adopted (for example, IEEE Trans. Comp. Pac. Manu. Tech). pt.A, 17,373 (1994)). However, when the memory cells are connected in series, there is a disadvantage that the power consumption efficiency during reading is significantly lowered.

In order to solve this problem, a method using a ferromagnetic tunnel effect (hereinafter, abbreviated as TMR effect) instead of the GMR effect has been proposed. An element exhibiting a TMR effect (hereinafter abbreviated as TMR element) mainly consists of a three-layer film composed of a ferromagnetic layer 1, an insulating layer, and a ferromagnetic layer 2, and a current flows through the insulating barrier. The tunnel resistance value changes in proportion to the cosine of the relative angles between the magnetization directions of the two ferromagnetic metal layers, and a maximum value can be obtained when the two magnetization directions are completely opposite to each other.

For example, in tunnel junctions of NiFe / Co / Al ₂ O ₃ / Co / NiFe, a magnetoresistance ratio of more than 25% is found in low magnetic fields below 50Oe (e.g. IEEE Trans. Mag., 33, 3553 (1997). The cell resistance value of the TMR element is typically from 10 ⁴ kPa to 10 ⁶ kPa per junction area (μm ² ). Thus, assuming that the resistance value is 10 mA and the magnetoresistance ratio is 25% in a cell of 1 mu m ² , a cell read signal of 25 mA is obtained at a sense current of 10 mA.

In an MRAM cell array using TMR elements, multiple TMR elements are connected in parallel on data lines. Detailed structures as described below are employed.

(1) A structure in which a select semiconductor element is arranged in series with each TMR element

(2) a structure in which a selection transistor is disposed for each data line to which a plurality of TMR elements are connected in parallel; And

(3) A structure in which a plurality of TMR elements are arranged in a matrix, and a selection transistor is arranged for each row data line or each column data line (see, for example, J. Appl. Phys., 81,3758 (1997)).

Among these structures, the structure of (1) has the best characteristics in terms of power consumption efficiency during cell output voltage reading.

However, in the MRAM cell having the structure of (1), it is necessary to supply a current to the semiconductor element connected to the TMR element during reading. As the semiconductor element, a MOS transistor, a diode element using the transistor, and a diode element using a pn junction or a Schottky junction are used. Therefore, when a deviation occurs in the characteristics of such a semiconductor element, the noise caused by such a deviation cannot be ignored.

For example, in the case of a MOS transistor, the voltage drop between the source and the drain reaches 100 kV or more in a rule of 0.25 mu m. That is, when there is a deviation of 10% in the characteristics of the semiconductor device, noise of 10 Hz or more is generated by this deviation. In addition, the noise level is greater than 10 dB when considering noise generated in the peripheral circuits, such as noise combined with data lines or noise due to characteristic variations in the sense amplifier. At current cell output voltages of about 20 kV to 30 kV, only a few kW signal-to-noise ratios can be obtained.

In order to improve the signal-to-noise ratio, in conventional MRAM cell arrays, a method of comparing the output voltage V of one selected memory cell with the reference V _REF and differentially amplifying the differential voltage V _sig therebetween is often used. . The first purpose of this is to eliminate noise generated in the pair of data lines to which the memory cells are connected, and the second purpose is the cell output voltage due to the deviation in the characteristics of the semiconductor element for driving the sense line or selecting the cell. Is to remove the offset of V _sig . As a circuit for generating the reference voltage V _REF , a circuit using a semiconductor element or a dummy cell is used. However, in this method, the circuit for generating the selected memory cell and the reference voltage is connected to their respective cell select semiconductor elements, making it impossible to completely eliminate the offset of the cell output voltage V due to the deviation in the characteristics of the semiconductor elements. Let's do it.

Also, in the prior art, the reference voltage V _REF is generally defined as an intermediate voltage between the output voltages V _F and V _AF corresponding to the cell information " 1 " and " 0 ". For example, in the case of current sensing or voltage detection, it is assumed that the sensing current value is defined as I _s , the resistance value of the TMR element used in the cell is defined as R, and the magnetoresistance ratio is defined as MR. V _F and V _AF can be obtained as follows.

Assuming that the reference voltage is set to an intermediate voltage between V _F and V _AF , the differential voltage input to the sense amplifier is as follows.

The factor of denominator 2 is because the reference voltage V _REF is set to an intermediate voltage. In the case of voltage sensing and current detection, assuming that the bias voltage is defined as V _bias and the detection load resistance is defined as R _L , the following formula can be similarly obtained.

In the derivation process of Equation 6, the point that MR ² <

Therefore, in the prior art, only half of the magnetoresistance ratio of the TMR element can be used.

In order to solve this problem, for example, there is a method of using a magnetic field while reading information by employing a TMR element in which the ferromagnetic layer 1 and the ferromagnetic layer 2 are ferromagnetically or antiferromagnetically coupled to each other (eg, See, for example, US Pat. No. 5,734,605). However, this method is not suitable for handheld devices because of the increased power consumption during reading.

In addition, a method of configuring a memory cell by arranging selection transistors for two TMR elements, respectively, is disclosed (see, for example, ISSCC 2000 Digest paper TA 7.2). In this method, recording is performed while the magnetization directions of the recording layers of the two TMR elements are always antiparallel to each other. That is, a complementary write is adopted in which the magnetization configuration of any of the elements enters the antiparallel state and the other magnetization enters the parallel state. In this method, the outputs of these two devices are differentially amplified, removing noise in the same phase and improving S / N. However, there is a problem that the cell area is increased and the degree of integration is lowered because two select transistors are adopted for one cell.

As described above, the TMR element is applied to a memory cell so that a decrease in the sense current during reading and an increase in the cell output signal can be simultaneously obtained, thereby providing a higher density MRAM than an MRAM using a conventionally adopted GMR effect. Makes it possible. However, even when a TMR element is used for a memory cell, the cell output voltage is about several tens of mV. In view of the strength of the noise due to the variation of the semiconductor device characteristics for driving the sense line or selecting the cell, or the strength of the noise from the data line and the peripheral circuit, a sufficient signal-to-noise ratio is not currently obtained. In order to improve the signal-to-noise ratio, a method using a magnetic field is proposed, but has the disadvantage of increasing power consumption during reading.

It is an object of the present invention to provide a magnetic memory device which can increase the cell output voltage during reading and can improve the signal-to-noise ratio without increasing the power consumption during reading, which has low power consumption and fast read characteristics. Has both.

According to the present invention, there is provided a magnetic memory cell device comprising a plurality of tunnel junctions for laminating a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field, and forming single, double and more tunnel junctions. A memory cell serving as an information recording apparatus is composed of two tunnel junction portions (first and second TMR elements), and the first end is connected to each data line in the stacking direction of each of the first and second TMR elements. And the second end is connected to the bit line via the same cell select semiconductor element.

In addition, according to the present invention, there is provided a magnetic memory cell apparatus comprising a plurality of tunnel junctions which form a single or multiple tunnel junctions by laminating a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field. Provided, the magnetic memory cell array is divided into a plurality of divided cell arrays, each divided cell array having first and second data lines arranged in parallel with each other, a plurality of word lines crossing the data lines, data A bit line arranged in parallel with the line, and a plurality of magnetic memory cells. The magnetic memory cell is composed of two tunnel junctions (first and second TMR elements), the first ends of the first and second TMR elements in the stacking direction are connected to the first and second data lines, respectively, The two ends are connected to the same bit line through the same cell select semiconductor element.

Further, according to the present invention, a magnetic memory cell having a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field and having a plurality of tunnel junctions constituting a single, double or more tunnel junctions An apparatus is provided, wherein the magnetic memory cell array is divided into a plurality of divided cell arrays, each divided cell array intersecting the first and second auxiliary data lines arranged parallel to each other, these auxiliary data lines. It consists of a plurality of word lines, an auxiliary bit line disposed in parallel with these auxiliary data lines, and a plurality of magnetic memory cells. The magnetic memory cell consists of two tunnel junctions (first and second TMR). First ends of the first and second TMR elements in the stacking direction are connected to the first and second auxiliary data lines, respectively. The second end is connected to the same auxiliary bit line through the same cell semiconductor element. The first and second auxiliary data lines and the auxiliary bit lines are connected to the first and second data lines and the bit lines through select transistors, respectively.

Preferred embodiments of the present invention are illustrated as follows.

(1) The resistance value and the magnetoresistance ratio of the first and second tunnel junctions are substantially the same, and the magnetization configurations of both recording layers of the tunnel junction are always antiparallel.

(2) One end of each of the first and second TMR elements is connected to each of the first and second data lines, and the other end is connected to the bit line via a cell select semiconductor element.

(3) The stored information is read by comparing the magnitudes of currents flowing in the first and second data lines when a potential difference is applied between the first and second data lines and the bit lines. In addition, the first and second data lines are maintained at the same potential.

(4) The stored information is read by comparing the magnitude of the voltage appearing at the bit line when a potential difference is applied between the first and second data lines.

(5) The first writing line is arranged at one end in the stacking direction of the first TMR element, and the second writing line is arranged at one end in the stacking direction of the second TMR element. A common write line is disposed at the first or second end of the first TMR element in the stacking direction and at the first or second end of the second TMR element in the stacking direction. These common write lines are configured such that the current direction through the first write line and the current direction through the second write line are diagonal.

(6) The first and second TMR elements are arranged in the same plane. The first and second write lines are arranged parallel to each other in the same plane. The third write line and the first and second write lines are in different planes and are arranged to cross each other in the vicinity of the first and second TMR elements. Each of the first and second write lines is connected to the outside of the memory cell array region at one end.

(7) The first and second TMR elements are arranged in the vertical direction, and the first and second writing lines are arranged parallel to the vertical direction. The third writing line and the first and second writing lines are arranged parallel to each other in the vertical direction in one plane. The third write line and the first and second write lines are in different planes and are arranged to cross each other in the vicinity of the first and second TMR elements. Each of the first and second write lines is connected to the outside of the memory cell array region at one end.

(8) Cell selection A semiconductor element is a MOS field effect transistor, a diode element using a MOS field effect transistor, or a junction diode element using a pn junction or a Schottky junction.

(9) The number of memory cells included in one auxiliary cell array is 1000 or less.

In the above-described magnetic memory device, a method of reading stored information about a memory cell includes firstly activating a cell select transistor semiconductor element in a low impedance state during readout, wherein a potential difference between the first and second data lines and a bit line is determined. Comparing the magnitude of current flowing through the first and second data lines when applied. The first and second data lines are controlled to be at the same potential. In this way, sense currents flow in the first and second data lines, which depend on the potential difference and resistance value of each TMR element. The resistance value of the TMR element differs depending on whether the relative angles of magnetization between the fixed layer and the storage layer of the TMR element are parallel or antiparallel to each other.

In the magnetic memory device according to the present invention, the resistance values and the magnetoresistance ratios of the two TMR elements are equal to each other, and the magnetization directions of the respective recording layers are antiparallel to each other. Therefore, the potential difference is defined as V _bias , the resistance value of the first TMR element is defined as R (1-MR / 2), and the resistance value of the second TMR element is defined as R (1 + MR / 2). Assuming, the values I ₁ and I ₂ of the sense currents flowing through the first and second data lines are as follows.

That is, the sense current difference I _sig is obtained by I _sig = (V / R) × MR, and a larger difference signal can be obtained than in the prior art. The memory cell is a current driven device. Thus, when a variation in resistance occurs when the cell select semiconductor is connected in series with the TMR element, it appears as a variation in the output signal as a result. In the present invention, since the first and second TMR elements share the same cell select semiconductor element, the deviation caused by the variation in the characteristics of the semiconductor element can be completely eliminated. This is a great advantage that the prior art does not have.

In addition, a second of the read methods may include: activating a cell select semiconductor element in a low impedance state during readout, and if a potential difference is applied between the first data line and the second data line, the voltage appearing at the bit line associated with the reference potential. Comparing the sizes. The potential difference between the first data line and the second data line is defined as V _bias , the resistance value of the first TMR element is defined as R (1-MR / 2), and the resistance value of the second TMR element is R (1). Assuming that + MR / 2) is defined, the potential difference V between the second data line and the bit line is obtained as follows.

At this time, the reference voltage V _REF is set as follows.

Then, the signal voltage V _sig is obtained as follows.

In this reading method, since the reference voltage is used, although the amount of change in the signal voltage is smaller than the amount of change in the first reading method, the following useful effects are provided.

(1) The differential voltage does not depend on the current value flowing through the TMR element. That is, even when the number of memory cells in the memory cell array changes and thus the impedance between data lines changes, the output is not affected.

(2) Since the bias voltage is distributed by two TMR elements, the decrease in the magnetoresistance ratio which depends on the applied voltage can be reduced.

(3) Since almost no current flows through the bit line, variations in the characteristics of the selected semiconductor element can be eliminated.

In the magnetic memory device according to the present invention, the storage information is written to the memory cells by supplying current to the first, second and third write lines. During this period, the value of the magnetic field is set to exceed the value of the switching magnetic field of the TMR element only in the intersection region of the first, second and third write lines, so that cell selection can be made during writing.

In the magnetic memory device according to the present invention, the direction of the current flowing in the first write line arranged in the first TMR element is opposite to the direction of the current flowing in the second write line arranged in the second TMR element. That is, in the magnetic memory device according to the present invention, the magnetization directions of the recording layers of the first and second TMR elements constituting the memory cell during the write operation are always antiparallel to each other. The information " 1 " and " 0 " is determined according to whether the relative angle of magnetization between the fixing layer and the recording layer of the element is parallel or antiparallel in the first TMR element.

According to the present invention, a first fixing layer having a fixed magnetization direction, a first tunnel barrier adjacent to the first fixing layer, and a first tunneling layer facing the first fixing layer through the first tunnel barrier, and the magnetization direction is changed according to an external magnetic field. A first magnetic layer, antiferromagnetically coupled to the first magnetic layer, interposed between the first and second magnetic layers, and between the first and second magnetic layers, the second magnetic layer having a magnetization direction that varies with an external magnetic field, and A magnetic memory layer formed of a stack of nonmagnetic conductive layers antiferromagnetically coupled to a second tunnel barrier adjacent to the second magnetic layer: and a second anchoring layer facing the second magnetic layer through the second tunnel barrier. A tunnel junction; And a detector configured to differentially detect a current difference or a voltage difference between the first tunnel current flowing through the first magnetic layer and the first fixed layer and the second tunnel current flowing through the second magnetic layer and the second fixed layer. A magnetic memory device is provided that includes.

According to the present invention, a first fixing layer having a fixed magnetization direction, a first tunnel barrier adjacent to the first fixing layer, a first tunneling layer facing the first fixing layer through the first tunnel barrier and the magnetization direction varying with an external magnetic field Between a first magnetic layer, a second magnetic layer antiferromagnetically coupled to the first magnetic layer, and a magnetization direction varying with an external magnetic field, and between the first and second magnetic layers, between the first and second magnetic layers A magnetic memory layer formed of a stack of antiferromagnetically coupled non-magnetic conductive layers: a second tunnel barrier adjacent the second magnetic layer: and a second anchoring layer facing the second magnetic layer through the second tunnel barrier; Tunnel junction; A bit line electrically connected to all or one of the first magnetic layer, the nonmagnetic conductive layer, and the second magnetic layer; A first data line electrically connected to the first anchor layer; And a second data line electrically connected to the second fixing layer.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, and will be learned by practice of the invention. The objects and advantages of the present invention can be realized and obtained by combination with the specific means pointed out below.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention, and together with the general description above, the following detailed description of the preferred embodiments is provided to illustrate the principles of the present invention.

1 shows an electrical equivalent circuit of a magnetic memory cell array according to the first embodiment;

2 is a view showing changes in current values I ₁ and I ₂ flowing through the data lines DL and / DL according to the first embodiment.

3 is a chart showing waveforms in the case where write information of a plurality of memory cells according to the first embodiment is continuously read;

4 is an equivalent circuit diagram in which elements other than the selection cell are assumed to be short circuit resistances.

FIG. 5 shows the results of a simulation using the equivalent circuit shown in FIG. 4. FIG.

Fig. 6 is a schematic diagram illustrating an arrangement of TMR elements and write lines constituting a magnetic memory cell array according to the first embodiment.

Fig. 7 is a diagram showing the planar structure of the memory cell used in the first embodiment.

8A and 8B show cross sections along lines 8A-8A and 8B-8B in the memory cell structure shown in FIG.

9A and 9B illustrate cross sections of a memory cell structure in which both write lines and data lines are used together.

Fig. 10 is a schematic view for explaining arrangement of TMR elements and write lines constituting a magnetic memory cell array according to the second embodiment.

Fig. 11 shows the planar structure of the memory cell according to the second embodiment.

12A and 12B show cross-sections along lines 12A-12A and 12B-12B in the memory cell structure shown in FIG.

Fig. 13 is a schematic diagram illustrating an arrangement of a TMR element and a write element constituting the magnetic memory cell array according to the third embodiment.

Fig. 14 shows a cross-sectional structure of elements of the magnetic memory cell array according to the third embodiment.

Fig. 15 shows an electrical equivalent circuit of the magnetic memory cell array according to the fourth embodiment.

16 is a cross-sectional structure of a magnetic memory cell array element according to the fifth embodiment of the present invention.

FIG. 17 shows a cross-sectional structure of a magnetic memory cell array element according to a sixth embodiment of the present invention. FIG.

18A and 18B show cross-sectional structures of the magnetic memory cell array elements according to the seventh embodiment of the present invention, respectively.

Fig. 19 shows a cross-sectional structure of a magnetic memory cell array element according to the eighth embodiment of the present invention.

20 is a cross sectional view showing a memory cell structure of a magnetic memory cell according to the ninth embodiment;

FIG. 21 shows an electrical equivalent circuit of a magnetic memory cell array according to the tenth embodiment.

Fig. 22 shows an electrical equivalent circuit of the magnetic memory cell array according to the eleventh embodiment.

Fig. 23 shows an electrical equivalent circuit of the magnetic memory cell array according to the twelfth embodiment.

Fig. 24 shows an electrical equivalent circuit of the magnetic memory cell array according to the thirteenth embodiment.

Fig. 25 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the fourteenth embodiment.

Fig. 26 shows an electrical equivalent circuit of the magnetic memory cell array according to the fifteenth embodiment.

FIG. 27 shows an electrical equivalent circuit of a magnetic memory cell array according to the embodiment according to the sixteenth embodiment.

FIG. 28 shows an electrical equivalent circuit of a magnetic memory cell array according to the seventeenth embodiment.

Fig. 29 shows an electrical equivalent circuit of the magnetic memory cell array according to the eighteenth embodiment.

30 is an electric equivalent circuit of the magnetic memory cell array according to the nineteenth embodiment;

FIG. 31 shows an electrical equivalent circuit of a magnetic memory cell array according to the twentieth embodiment; FIG.

FIG. 32 shows an equivalent circuit in the case where the pn diode of the magnetic memory cell array according to the modification of the twentieth embodiment is replaced with the MOS transistor;

FIG. 33 shows an electrical equivalent circuit of a magnetic memory cell array according to the twenty-first embodiment; FIG.

FIG. 34 shows the results obtained when the current flowing through the bit line in the twenty-first embodiment is measured as a function of the offset voltage Voff. FIG.

35 illustrates an electrical equivalent circuit of the magnetic memory cell array according to the twenty-second embodiment.

36 is a timing chart for explaining a read operation of the magnetic memory array in the twenty-second embodiment;

FIG. 37 shows the overall structure of a magnetic memory cell array in accordance with a twenty-second embodiment; FIG.

<Explanation of symbols for the main parts of the drawings>

11, 21, 13, 23: TMR element

30: word line

31, 32, 33, 34: select transistor

41, 42: data line

44: cell plate

51, 52: write line

101: recording layer

102: tunnel barrier

103: fixing layer

111: tunnel junction element

201: memory cell

401: Current Sensing Differential Amplifier

420: bias voltage clamping circuit

Hereinafter, the present invention will be described in detail by the present embodiment.

<First Embodiment>

1 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a first embodiment of the present invention.

In the figure, the region enclosed by the dotted lines corresponds to the memory cell 201, which is made of two TMR elements and a selection transistor. That is, the first memory cell is made of the TMR elements 11 and 21 and the select transistor 31; The second memory cell is made of TMR elements 12 and 22 and select transistor 32; The third memory cell is made of the TMR elements 13 and 23 and the select transistor 33; The fourth memory cell is made of the TMR elements 14 and 24 and the select transistor 34. In the drawing, four memory cells are arranged in relation to the data line direction to be described later, but the number of arranged memory cells can, of course, be changed as necessary.

In the first memory cell 201, one end of the TMR element 11 is connected to the data line DL, and one end of the TMR element 21 is connected to the data line / DL. The other end of each of the TMR elements 11 and 21 is connected to the same bit line BL through the cell select transistor 31. The other cell is also likewise connected to one end of each TMR element to the data lines DL and / DL and the other end to the same bit line BL via cell select transistors 32 to 34.

Independent word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively. As will be described later, adjacent memory cell arrays share the drain region and the bit line of the select transistor. The data lines DL and / DL are connected to the current detection type differential amplifier 401 through a select transistor having a common word line DSL. The bias voltage clamping circuit 420 is connected to the bit line BL through a select transistor to which the word line BSL is connected.

Next, the operation of this circuit will be described taking the memory cell 201 as an example.

From now on, when the magnetization configurations of the recording layer and the fixing layer of the TMR element 11 are parallel to each other, and the magnetization configurations of the recording layer and the fixing layer of the TMR element 21 are antiparallel to each other (recording information " 1 &quot;)Let's consider that. In the initialization state, the potentials of WL1, BSL, and DSL are zero. At this time, the potentials of DSL and BSL are set to V _DD , DL and / DL are set to zero potential, and V _bias is applied to BL. In this state, when WL1 is set to V _DD , the selection transistor 31 is in a conductive state. Assuming that the resistance value of the TMR element 11 is set to R (1-MR / 2) and the resistance value of the TMR element 21 is set to R (1 + MR / 2), the data lines DL and / DL The sense currents I ₁ and I ₂ flowing through are as follows.

Namely, the result is I ₁ I ₂ and the difference is I _sig = (V / R) x MR. When the recording information is "0", that is, the magnetization configurations of the TMR elements 11 are antiparallel to each other, When the magnetization configurations of 21) are parallel to each other, I ₁ and I ₂ are as follows.

That is, the result is I ₁ <I ₂ , and the difference is the same as in the case where the recording information is “1”. Therefore, the magnitudes of I ₁ and I ₂ are compared by the current detection type differential amplifier 401, so that the information can be read.

2 shows the change in currents I ₁ and I ₂ flowing through the data lines DL and / DL over time. Here, the bias voltage V _bias is 400 kV, and the resistance values of the TMR elements 11 and 21 are 40 kV in the parallel state in the case of the predetermined bias, and 60 kV in the anti-balance state. The potential WL1 is held at VDD for 5ns to 10ns. As described above, it has been found that depending on the device resistance value, different values of sense current flow through the data lines DL and / DL. Stray capacitance of the data lines causes some time delay.

3 shows waveforms in the case where write information for a plurality of memory cells is read continuously. In this embodiment, since the low impedance data lines DL and / DL are current driven, the delay due to the stray capacitance of the data lines is as small as 0.5 ns or less, as shown in FIG. This high speed read feature is a great advantage of the present invention.

In the present embodiment, the unselected cell functions as a short circuit resistance between the data lines DL and / DL, and the resistance value is 2R regardless of the stored information. For example, in the case where N + 1 cells are connected to the data lines DL and / DL, the equivalent circuit is as shown in FIG. In this circuit, the connection between the data lines DL and / DL is shorted by a resistance of 2R / N. While the sense current flows from the selected cell to the data lines DL and / DL, the potential difference is generated little by little in the data lines DL and / DL by the wiring resistance R _D of the data lines DL and / DL, so that the current is short-circuited R _D Flows on. As a result, the potential difference acts in the direction in which the current difference between the data lines DL and / DL is removed.

FIG. 5 shows simulation results using the equivalent circuit shown in FIG. 4. Here, it is estimated that R = 250 ms. When the size of the short-circuit resistance R _dummy is 2.5 kW, that is, when the number of connected cells is N = 100, the reduction in the current difference is within 10% without causing any practical problem. However, if the number of connected cells is N = 1000, the reduction in the current difference will exceed 50%, and the output signal will double due to the compensation reading, and the advantages of the present invention will be lost. Therefore, in this embodiment, the number of memory cells per cell block is preferably 100 or less, and at most about 1000 are required.

Fig. 6 schematically shows the arrangement of TMR elements and write lines constituting the magnetic memory array according to this embodiment. In Fig. 6, reference numerals 10 to 14 and reference numerals 20 to 24 denote TMR elements, and reference numerals 51 and 52 denote writing lines. For a better understanding of the present invention, configurations other than those of the TMR element and the write line will be omitted here. In the figure, the region enclosed by the dotted lines indicates the memory cell 201. In the figure, five memory cells are arranged along the direction in which the write lines 51 are arranged, but the number of such arrays can be changed as necessary.

The memory cell 201 includes two TMR elements (first and second TMR elements 11 and 12), and write lines 51 and 52 that vertically cross each other in their respective device regions. The TMR elements 11 and 21 constitute one or two or more tunnel junctions as described later, have a fixed layer with a fixed magnetization direction, and have a recording layer with a changed magnetization direction. In addition, these elements are manufactured such that the resistance value, the magnetoresistance ratio, and the magnitude of the switching magnetic field of the recording layer are the same in the two elements. The write lines 51 have a folded U-shape and are arranged so that the current flow direction is reverse with respect to the TMR elements 11 and 21.

Write information is written into the memory cell 201 using the write lines 51 and 52. Now, if the potential of one end 511 of the write line 51 is set to be higher than the other end 512, the write current flows through the write line 51 as indicated by the arrow. The directions of the write currents are the upper right part of the paper surface associated with the TMR element 21 and the lower left part of the paper surface associated with the TMR element 11. By the write current, a magnetic field in the direction indicated by the arrow shown by the dotted line in the figure is generated around the write line, but its orientation is on the left side of the paper surface associated with the TMR element 21 and on the right side of the paper surface associated with the TMR element 11. to be. Therefore, by this magnetic field, the writing operation can be made so that the magnetization directions of the TMR elements 11 and 21 are always opposite to each other.

The information " 1 " and " 0 " can be determined according to whether the relative angle between the magnetization of the recording layer of the TMR element 11 and the magnetization of the fixing layer is parallel or antiparallel. In addition, the information "1 " and " 0 " In the write line 51, the first write line 51a is connected to the terminal 511 and the second write line 51b is connected to the terminal 512.

In order to select a cell during writing, a write line 52 (third write line) is used together with the write line 51. That is, as shown, when the write current in the upper left direction of the paper surface flows through the write line 52, a magnetic field in the direction indicated by the arrow shown by the dotted line in the figure is generated around the write line 52. The direction of the magnetic field from the write line 52 is the same as that of the TMR elements 11 and 21 and is perpendicular to the direction of the magnetic field from the write line 51. Therefore, the value of the write current flowing through each of the write lines 51 and 52 is set such that the value of the synthesized magnetic field from the write lines 51 and 52 is larger than the value of the inverted magnetic field, so that cell selection and writing is performed. Can be achieved.

In the writing operation using magnetic fields orthogonal to each other as described above, it is preferable that the gentle magnetization axis of the recording layer of the TMR element is parallel to the direction of the magnetic field from the writing line 51. In addition, the write lines 51 and 52 do not always have to be orthogonal to each other in the vicinity of the TMR element, and can be set at any angle.

FIG. 7 shows a planar structure of the memory cell 201 corresponding to that shown in FIG. 1. The memory cell according to the present embodiment has two TMR elements in one structure, and the TMR elements are formed in the upper layer of the semiconductor circuit portion on the Si substrate 70.

In Fig. 7, reference numerals 71 and 72 denote diffusion regions of cell select transistors serving as drains or sources of transistors, 41 and 42 denote data lines, 30 denote word lines of cell select transistors, and 44 denote TMR elements 11 and 12. Cell plate 45 formed in the lower layer represents a contact portion between cell plate 44 and the drain region of the cell select transistor. The source region 72 of the cell select transistor is shared with the memory cells of an adjacent memory cell array (not shown) and connected to the bit line. Considering the device isolation region, the size of one memory cell range is 20 to 25F ² . Where F represents the data line spacing.

In this embodiment, the two TMR elements share one transistor, so that the two TMR elements can double the cell area compared to a differential amplifier having its own transistor.

8A and 8B are cross-sectional views taken along lines 8A-8A and 8B-8B in the planar structure of the memory cell shown in FIG. The semiconductor circuit portion and each metal layer formed on the Si substrate 70 are separated by the interlayer insulating layer 60. The TMR elements 11 and 21 each have a stacked structure of a recording layer 101, a tunnel barrier 102 and a fixing layer 103. The TMR elements 11 and 21 are formed on the common cell plate 44. The cell plate 44 is formed such that electrical contact is made between the cell select transistors and the respective TMR elements 11 and 21. This node consists of a nonmagnetic conductive layer such as W, Al or Ta.

Although the write lines 51 and 52 are shown in a separate structure from the data lines 41 and 42 in this embodiment, as shown in FIGS. 9A and 9B, all of them share the data lines 41 and 42. The function of the write line 51 may be provided. In this case, the metal wiring layer corresponding to the write line 51 shown in Figs. 8A and 8B is removed. Also, in the case described above, the data lines 41 and 42 must be shorted at one end thereof during the write operation, but such a short circuit mechanism can be easily configured using conventionally known circuit techniques. Although the data lines 41 and 42 are connected to each other by a plurality of TMR elements, the junction resistance of the TMR elements is sufficiently large compared to the wiring resistance of the data lines. Thus, even when a plurality of elements are connected, the magnitude of the write current flowing through the TMR element during writing can be ignored.

In a preferred embodiment, a barrier metal composed of a conductive metal nitride such as TiN or TaN to prevent mutual metal diffusion is provided at the bottom of the cell plate 44 and at the contact point of the TMR element. In addition, a seed layer such as Au, Pt, Ta, Ti, or Cr may be provided to control the crystallinity and the crystal direction of the fixing layer 103.

The fixing layer 103 is formed of a thin layer made of Fe, Co, Ni, or an alloy thereof. The magnetization direction of the fixation layer defines the reference direction during information recording and reading. Therefore, the switching magnetic field must be sufficiently larger than the switching magnetic field of the recording layer described later. For this purpose, for example, a laminated structure made of a metal antiferromagnetic material, such as an Mn alloy and Fe, Co, Ni or an alloy thereof, or Fe, Co, Ni or an alloy thereof and Cu or Ru subjected to interlayer antiferromagnetic bonding It is desirable to use alternative laminated structures of non-magnetic metals such as

The tunnel barrier 102 is made of an Al oxide layer, and is formed on the fixing layer 103 by directly sputtering alumina or forming Al to a thickness of 2 nm or less and then oxidizing the Al layer. The material used for tunnel barrier 102 should have good insulation with a very thin layer thickness of 2 nm or less. As such a material, Ta ₂ O ₅ , MgO, silicon oxide, silicon nitride and the like can be used as well as the alumina sputtering layer and Al oxide layer described above. Further, a structure in which metal particles are dispersed in an insulating material, and a structure in which a very thin metal layer of several nm is sandwiched can be provided. When an insulating layer having such a composite structure is used, the cell resistance value can be easily controlled by structural design, which is preferable from a practical point of view.

The recording layer 101 is formed of a thin layer made of Fe, Co, Ni, or an alloy thereof. In order to reduce power consumption during information recording, the switching magnetic field of the recording layer is preferably as small as possible. Preferred sizes of the switching magnetic field are 10 Oe to 30 Oe. In order to reduce the switching magnetic field of the recording layer, in a preferred embodiment, a layer in which a CoFe alloy layer having high spin polarization of conductive electrons and a NiFe alloy layer having soft magnetism are used is laminated. In addition, alloys or compounds of Fe, Co, Ni and any other elements may be used.

Data lines 41 and 42 made of a nonmagnetic conductive layer such as W, Al or Cu, or an alloy thereof are disposed in the upper layer of the recording layer 101. Alternatively, in a preferred embodiment, a barrier metal made of a conductive metal nitride such as TiN or TaN is provided at the contact site, for example, to prevent interdiffusion with these lines. In components other than the TMR element and a method of manufacturing the same, a known semiconductor element manufacturing technique may be used, and a detailed description thereof will be omitted.

As described above, in this embodiment, one memory cell (e.g., reference numeral 201) is manufactured by two TMR elements (e.g., reference numerals 11 and 21), and each memory cell is disposed in parallel with each other. Is arranged at the intersection between the write lines 51a and 51b of and the write lines 52 perpendicular to these lines. Thus, current is supplied to the write lines 51a and 51b and the write line 52 so that writing can be selectively performed for any memory cell.

The directions of the currents flowing through the write lines 51a and 51b are opposite to each other, and the magnetization directions of the recording layers 101 of the two TMR elements 11 and 21 constituting one memory cell are always antiparallel to each other during the write operation. Do. Therefore, since the difference between the outputs of the TMR elements 11 and 21 occurs during reading of the storage information, a large differential voltage can be obtained as compared with the prior art. Specifically, when the cell select transistor 31 is brought into a conductive state during reading and a potential difference is applied between each of the first and second data lines DL and / DL and the bit line BL, the data line DL, The magnitudes of the currents I ₁ , I ₂ flowing in / DL are compared with each other by the current detection type differential amplifier 401, so that the stored information can be read.

Thus, according to the present embodiment, the cell output voltage can be increased, and the signal-to-noise ratio can be improved without increasing power consumption during reading, thereby making it possible to achieve compatibility between low power consumption and high speed reading capability. In addition, the TMR elements 11 and 21 share the same cell select transistor 31, thus making it possible to completely eliminate the offset of the cell output voltage due to the difference in transistor characteristics.

Second Embodiment

FIG. 10 is a schematic diagram for explaining arrangement of TMR elements and write lines constituting a magnetic memory cell array according to a second embodiment of the present invention.

In Fig. 10, reference numerals 10 to 14 and 20 to 24 denote TMR elements, and reference numerals 51 and 52 denote writing lines. For easier understanding, structures other than the TMR element and the write line are omitted. In the figure, an area enclosed by a dotted line indicates an area of the memory cell 201 which is an information recording unit.

The memory cell 201 includes two TMR elements 11 and 12. The write lines 51 and 52 vertically cross in their respective device regions. The write line 51 has a fold-shaped U-shape in the vertical direction, and is disposed so that the current traveling directions of the TMR elements 11 and 12 face each other. In the present embodiment, unlike the first embodiment, the TMR elements 11 and 12 and the write line 51 are arranged in the same plane in the direction perpendicular to the layer plane.

That is, the write lines 51 are composed of first and second write lines 51a and 51b arranged parallel to each other in the vertical direction, and one end of each write line 51a and 51b is connected outside the cell arrangement region. do. TMR elements 10 to 14 are respectively disposed on the bottom surface of the write line 51a, and TMR elements 20 to 24 are each disposed on the top surface of the write line 51b, and the TMR elements 10 and 14 are disposed. 20, 11 and 21, 12 and 22, 12 and 23, 14 and 24 are arranged opposite each other in the vertical direction. For example, for the memory cell 201 manufactured from the TMR elements 11 and 21, the first write line 51a and the second write line such that the third write line 52 is orthogonal to the write lines 51a and 51b. It is arrange | positioned in the intermediate position between 51b. Since the configuration and functions other than those described above are the same as in the first embodiment, detailed descriptions thereof will be omitted here.

FIG. 11 illustrates a planar structure of the memory cell 201 corresponding to that shown in FIG. 10. 12A and 12B are schematic cross-sectional views of the memory cells corresponding to those shown in FIG. 11, taken along lines 12A-12A and 12B-12B.

In the present embodiment, unlike the first embodiment, the common cell plates 44 and 44 'are provided in two layers, upper and lower, and the cell plate 44 is connected to the lower end of the upper TMR element 11. The cell plate 44 ′ is connected to the lower end of the lower TMR element 21. Further, the data line 41 is connected to the upper layer of the recording layer 101 of the TMR element 11, and the data line 42 is connected to the upper layer of the recording layer 101 ′ of the TMR element 21.

As described above, in the present embodiment, unlike the first embodiment, the TMR elements 11 and 21, the write lines 51, and the data lines 41 and 42 are arranged in the same plane in the direction perpendicular to the layer plane. Configurations and functions other than those described above are similar to those in the first embodiment, and effects similar to those in the first embodiment are achieved. Further, in this embodiment, two TMR elements 11 and 21 are arranged in the vertical direction, and the area of one memory cell is about 8 to 12F ² , which is smaller than in the first embodiment.

Third Embodiment

FIG. 13 is a schematic diagram for explaining an arrangement of TMR elements and write lines constituting a magnetic memory array according to a third embodiment of the present invention.

In Fig. 13, reference numerals 10 to 14 and 20 to 24 denote TMR elements, and reference numerals 51 and 52 denote writing lines. For easier understanding, the description of structures other than the TMR element and the write line is omitted. Unlike the second embodiment shown in FIG. 10, the third write line 52 passes under the second write line 52b instead of between the first write line 51a and the second write line 51b. .

14 is a diagram schematically showing a cross section of a memory cell in the third embodiment. In the present embodiment, unlike the first and second embodiments, the TMR elements 11 and 21 are formed above and below the common cell plate 44, respectively. The data line 41 is connected to the upper layer of the recording layer 101 of the TMR element 11, and the data line 42 is connected to the lower layer of the recording layer 101 ′ of the TMR element 21.

Also, in this embodiment, the cell plate is made of ferromagnetic material. This material is characterized by functioning as a common fixing layer of the TMR elements 11 and 21. That is, the TMR element 11 is made of the recording layer 101, the tunnel barrier 102 and the cell plate 44, and the TMR element 21 is the recording layer 101 ', the tunnel barrier 102' and the cell. It is made of plate 44 '.

According to this configuration, this embodiment provides an advantage that the cell array can be easily manufactured as compared with the second embodiment, and the characteristic variation of the TMR elements 11 and 21 is reduced. In the cell plate 44, only portions forming the TMR elements 11 and 21 are made of ferromagnetic material, and the remaining portions are made of non-ferromagnetic material.

According to this embodiment, the TMR element and the write line are stacked in the direction of the layer plane, whereby the cell area can be significantly reduced. If F is defined as the data line spacing, the area of one memory cell is 8 to 12F ² , which is about half of the cell area as compared with the first embodiment.

Fourth Example

Hereinafter, a fourth embodiment related to the circuit configuration of the magnetic memory device according to the present invention will be described with reference to the circuit diagram shown in FIG.

The magnetic memory device according to the present invention includes two or more tunnel junctions for each of a plurality of memory cell components. In the fourth embodiment, a description will be made using the double tunnel junction element 111, which includes two tunnel junctions, but in the present invention extends to multiple tunnel junctions. Have an aspect.

The configuration of the double tunnel junction elements 111a and 111b shown in FIG. 15 will be described using the element 111a. The element 111a includes a tunnel junction 111a-1 formed of a first fixing layer, a first tunnel barrier, and a first magnetic layer, and a tunnel junction 111a formed of a second fixing layer, a second tunnel barrier, and a second magnetic layer. -2). When they are sequentially stacked, they are subsequently stacked in the order of the first fixing layer, the first barrier layer, the first magnetic layer, the nonmagnetic conductive layer, the second magnetic layer, the second tunnel barrier, and the second fixing layer.

The first and second fixing layers are ferromagnetic layers with fixed magnetization, and the magnetization does not change even under the write magnetic field. In the first and second magnetic layers, the magnetization of the first and second magnetic layers is always antiferromagnetically coupled because of the nonmagnetic conductive layer interposed between these magnetic layers. The first and second magnetic layers and the nonmagnetic conductive layer constitute a recording layer. The magnetization configuration of this recording layer can be changed by applying a write magnetic field.

Differential detection of the storage information of these tunnel junction elements (eg, 111a and 111b) will be explained by using the tunnel junction element 111a shown in FIG. By storing the information, one of the tunnel junctions 111a-1 and 111b-2 is the low resistance R _P and the other resistance is the high resistance R _AP . Here, the low resistance R _P is a resistance in which the magnetization of the magnetic layer and the magnetization of the fixed layer are parallel to each other, and the high resistance R _AP is a resistance in which the magnetization of the magnetic layer and the magnetization of the fixed layer are antiparallel.

In the double tunnel junction element 111a, the first fixing layer is connected to the data line 113 and the second fixing layer is connected to the data line 112. These layers are connected to the common sense amplifier 117.

The recording layer is electrically connected to the source or the drain of the transistor 114a. In this manner, all or any one of the first magnetic layer, the nonmagnetic conductive layer, and the second magnetic layer constituting the recording layer are configured to be electrically connected to the source or the drain through the conductive layer.

The other double tunnel junction element having the same configuration as the double tunnel junction 111a, for example, the double tunnel junction element 111b shown in FIG. 15, is parallel to the data lines 112 and 113 in the same form as the element 111a. Is connected. In addition, the connection between the recording layer of the double tunnel junction element 111b and the cell transistor 114a is made similar to the double tunnel junction element 111a.

A plurality of two or more tunnel junction elements connected to the same data lines 112 and 113 may be provided, and the data lines 112 and 113 shown in FIG. 15 are arranged in an array shape in the extending direction. In addition, the cell transistors 114a and 114b of the memory cell connected to the same bit line shown in FIG. 15 are commonly connected to the source or drain of the bit line select transistor 115. The gate of each cell transistor is connected to each of the corresponding word lines 116a and 116b. Although not shown, the gate electrodes of the cell transistors of the memory cells arranged in an array shape may be commonly connected to the same word line in the length direction of the word line.

In the fourth embodiment, one memory cell consists of one transistor and one double tunnel junction element, so that a differential system is achieved and there is no need to use a reference cell. In addition, the bit size can be greatly reduced, and a large memory device can be achieved. In addition, problems associated with variations in cell transistors can be reduced, and therefore noise can be greatly reduced. As a result, the obtained S / N ratio is 10 times higher than that of the conventional MRAM. In addition, since more than one multiple tunnel junction is used, the reduction in the magnetoresistance ratio which depends on the applied voltage becomes small. Also, due to the fact that the recording layers are composed of first and second ferromagnetic layers which are antiferromagnetically coupled to each other, even when the size of the memory cell is reduced to the sub-micron region, the demagnetization is still reduced. Therefore, it is possible to provide a large capacity nonvolatile memory with low power consumption.

Fifth Embodiment

In the fifth embodiment, the structure and the magnetic information writing / reading of the memory device constituting the circuit described in the fourth embodiment are described with reference to the cross-sectional view shown in FIG. In FIG. 16, the same elements as those shown in FIG. 15 are given the same reference numerals, and detailed description thereof is omitted here.

According to the double tunnel junction element 111 of the illustrated embodiment, the first fixing layer 121; First tunnel barrier 122; First magnetic layer 123; Nonmagnetic conductive layer 124; Second magnetic layer 125; Second tunnel barrier 126; And a second ferromagnetic magnetization fixing layer 127 are sequentially stacked. The first magnetic layer 123, the nonmagnetic conductive layer 124, and the second magnetic layer 125 constitute a recording layer 128. In this device 111, the first tunnel junction is formed by the first fixing layer 121, the first tunnel barrier 122, and the first magnetic layer 123, and the second tunnel junction is formed by the second magnetic layer ( 125, the second tunnel barrier 126 and the second anchoring layer 127. Although the recording layer 128 is a three-layer film, this layer may be a multilayer film.

The first and second magnetic layers 123 and 125 constituting the recording layer 128 are antiferromagnetically coupled to each other. That is, the magnetizations of the first and second magnetization layers 123 and 125 are maintained in opposite directions, and the magnetizations of these layers are maintained in opposite directions after being inverted by an external magnetic field. This antiferromagnetic coupling can be achieved by inserting a thin nonmagnetic conductive layer 124 between the first and second magnetic layers 123, 125.

The material of the nonmagnetic conductive layer 124 that promotes interlayer exchange coupling with the first and second ferromagnetic layers may be selected from known materials. However, it is preferable to use Cu, Ru, Cr, Re, Ir and an alloy containing at least 50 atomic% of one of these elements. In particular, Ru, Re and Ir thin films are preferred because they can promote strong antiferromagnetic interlayer bonding.

In addition, in order to promote the magnetization conversion due to the weak magnetic field, it is preferable that the two magnetic layers have different magnetizations. Therefore, it is preferable to form first and second magnetic layers having different layer thicknesses, or to use magnetic layers having different materials, respectively.

The magnetization directions of the first and second fixing layers 121 and 127 are fixed to be the same as shown in FIG. 16. The magnetization directions of the antiferromagnetically coupled first and second magnetic layers 123 and 125 are inverted from the state "1" shown in FIG. 16 to the state "0", whereby the storage information of these memory cells Is changed.

In the state " 1 " shown in FIG. 16, the directions of the magnetizations of the first fixing layer 121 and the first magnetic layer 123 are antiparallel to each other. Thus, the first tunnel junction is a high resistance R _AP . The magnetization directions of the second magnetic layer 125 and the second fixing layer 127 are parallel to each other. Thus, the second tunnel junction is low resistance R _P. In contrast, in the state " 0 &quot;, the directions of magnetization of the first fixing layer 121 and the first magnetic layer 123 are parallel to each other. Thus, the first tunnel junction is low resistance R _P. The magnetization directions of the second magnetic layer 125 and the second fixing layer 127 are antiparallel to each other. Thus, the resistance of the second tunnel junction may be high resistance R _AP .

Now, the method of the write operation will be described later. Information is stored by supplying a write current to the write lines 129 and 130 shown in FIG. The write line 129 extends long in the horizontal direction of the paper surface shown in FIG. 16, and the write line 130 extends long in the vertical direction of the paper surface. The write current is supplied to both sides, whereby information is stored only at the intersection points in the double tunnel junction element 111. As shown in FIG. 16, the recording layer 128 is connected to the source or drain 131 of the cell select transistor 114 through a contact column (wire) made of a conductive material, and the other of the cell select transistor 114. The source or drain 131 is connected to the bit line select transistor 115 shown in FIG. A contact column connecting the recording layer 128 and one of the source or the drain 131 is disposed in front of the paper surface indicated by the dotted line in FIG. 16 or in the depth direction, and the data line 113 and the writing via the interlayer insulating layer. Pass through line 129.

The vertically stacked double tunnel junctions shown in FIG. 15 can greatly contribute to the reduction in bit size. In addition, when the soft magnetic layer is used as two magnetic layers 123 and 125 that are antiferromagnetically coupled to each other, the coercive force is reduced. Therefore, a small magnetic field is required for writing the information. Although the device size is reduced, the write current is still small, and the power consumption is kept low.

Also, as in the fourth embodiment, no reference cell is used, and there is no need to consider the deviation of the transistor or the tunnel junction element. Thus, a significant price reduction is achieved.

In order to increase the read sensitivity, it is preferable to use a material having a high magnetoresistance ratio with respect to the magnetic material of the first and second ferromagnetic fixing layers or the first and second magnetic layers. Accordingly, the magnetic layers 123 and 125 and the fixing layers 121 and 127 may be made of Co, Fe, CoFe, CoNi, CoFeNi, and FeNi alloys and half-metals such as NiMnSb or Co ₂ MnGe. have. In semimetals, only one energy gap exists in one spin band. Therefore, the spin polarization rate is large. By using such a metal, a high magnetoresistive effect can be realized. As a result, more signal output can be obtained.

In addition, it is possible to use various means for fixing the magnetization of the fixing layers 121 and 127. For example, the magnetization of the fixing layer is fixed by means of using a ferromagnetic material having a higher coercive force than the magnetic layers 123 and 125 of the recording layer 128, and an exchange coupling between the antiferromagnetic layer and the ferromagnetic layer in contact with each other. Means are provided, and means for bringing the ferromagnetic layer into contact with the hard magnetic layer instead of the antiferromagnetic layer to fix the magnetization of the anchoring layers 121, 127 using a leakage magnetic field. Antiferromagnetic layer materials used for exchange coupling may include materials employed in common spin valve GMR such as FeMn, IrMn, and PtMn.

In addition, as the tunnel barriers 122 and 126, various insulating nonmagnetic materials such as Al ₂ O ₃ , Ta ₂ O ₅ , silicon nitride, silicon oxide, or MgO may be used. The thickness of these layers preferably amounts to 5 kPa to 30 kPa.

In addition, as described above, the magnetic element thin film layer may be manufactured by using a general apparatus for forming thin layers such as a molecular beam epitaxy (MBE) method, various sputtering methods, or vapor deposition methods. In addition, structures such as those shown in the illustrated embodiment can be manufactured by using sophisticated processing techniques and multiple stacked wiring techniques.

Sixth Embodiment

The sixth embodiment describes the writing / reading of information using another structure of the memory device constituting the circuits described in the fourth and fifth embodiments and the cross-sectional structure and schematic circuit diagram of FIG. In FIG. 17, the same parts as those of FIGS. 15 and 16 are denoted by the same reference numerals, and detailed description thereof will be omitted herein.

In the illustrated embodiment, there is a circuit in which any of the data lines 112 and 113 shown in FIG. 17 and the data line 113 and the sense amplifier 117 are connected via the transistor 133. In this way, one of the two write lines 129 and 130 in FIG. 16 can be eliminated. That is, during information writing, current is provided to the data line 112 and the write line 134, and at the same time the transistor 133 is turned off. In this way, the current flowing through the data line 112 does not flow through the tunnel junction, but only contributes to generating a magnetic field for writing.

As such, one write line can be removed by inserting transistor 133, and the number of wiring layers can be reduced.

Seventh Example

The seventh embodiment describes the writing / reading of information by using another configuration of the memory device constituting the circuit described in the fourth embodiment and the cross-sectional structure and schematic circuit diagram shown in Figs. 18A and 18B. In Figs. 18A and 18B, the same parts as those in Figs. 15 to 17 are denoted by the same reference numerals, and detailed description will be omitted here.

As shown in FIGS. 18A and 18B, in the seventh embodiment, one of the source or drain 131 of the cell select transistor 114 is connected to the recording layer 128 via the cell plate 138 and the contact 139. Is connected to. This is formed by providing holes in the second tunnel barrier 126 and the second anchoring layer 127 shown in FIG. 16 to pad the holes with an insulating material. In addition, a nonmagnetic conductive layer 137 may be used. In this case, it is required to laminate and process the nonmagnetic conductive layer.

With the configuration as shown in Figs. 18A and 18B, when information is written, current is supplied to the data line 112 and the write line 134. When the switch transistor 133 connected to the data line 113 is turned off, the tunnel current does not flow to the double tunnel junction 111. Information can be written into the recording layer 128 by a composite magnetic field for two currents flowing in the data line 112 and the write line 134.

In addition, when the stored information is read, the switch transistor 133 shown in FIGS. 18A and 18B is turned on so that current flows through the data lines 112 and 113. When transistor 114 is turned on, power may be supplied to double tunnel junction 111.

<Eighth Embodiment>

The eighth embodiment describes the writing / reading of information with reference to the structure of the memory device constituting the circuit described in the fifth embodiment, the cross-sectional structure and schematic circuit diagram shown in FIG. In Fig. 19, the same parts as those in Figs. 15 to 18 are denoted by the same reference numerals, and detailed description will be omitted here.

19 is a sectional view of a magnetic memory cell according to the ninth embodiment. This embodiment is characterized by using a junction diode 151 as a cell select semiconductor element. The double tunnel junction element 111 is inserted vertically between the first and second data lines 112 and 113 extending in the vertical direction with respect to the sheet of the drawing. The recording layer 128 and the diode 151 are connected to each other by the cell plate 138 and the contact portion 139. Diode 151 is connected to the write line 134. The rectifying direction of the diode 151 may be determined according to the configuration of the write / read circuit as shown later. The write line 134 is perpendicular to the first and second data lines 112 and 113 and also functions as a bit line. The write operation is performed by flowing a signal current through the data lines 112 and 113 and the write line 137 perpendicular thereto. In this case, the diode prevents the write current from flowing into the double tunnel junction element 111. The diode 151 may be formed of a device having a rectifying function such as a pn junction diode, a Schottky junction diode, a MIS junction diode, and the like.

In the above-mentioned fifth to seventh and ninth embodiments, a double tunnel junction element in which layers are formed so as to be stacked in the vertical direction of the substrate surface is used for the tunnel junction element in the memory and the cell, but the tunnel junction element of the present invention is similar to this. The present invention is not limited thereto, and may be variously changed. That is, the present invention can be applied to double or more tunnel elements. In addition, these layers need not always be stacked.

<Example 9>

20 is a sectional view of a magnetic memory cell according to the ninth embodiment.

The memory cell 201 includes a first fixing layer 121 having a fixed magnetization direction; First tunnel barrier 122; The recording layer 128 formed of the first magnetic layer 123 whose magnetization direction changes depending on the magnetic field, the nonmagnetic conductive layer 124, and the second magnetic layer 125 whose magnetization direction changes depending on the magnetic field. ); Second tunnel barrier 126; And the second fixing layer 127 having a fixed magnetization direction are laminated and manufactured in the order described. In other words, the first anchor layer 121, the first tunnel barrier 122, and the first magnetic layer form a first tunnel junction. The second magnetic layer 125, the second tunnel barrier 126, and the second anchor layer 127 form a second tunnel junction. The nonmagnetic conductive layer 124 and the cell select transistor 131 are interconnected through the cell plate 138 and the contact 139.

The first and second data lines 112 and 113 insert the first and second tunnel junctions vertically therebetween and are perpendicular to the write line 134. The write operation is performed by flowing a write current to the data lines 112 and 118 and the write line 137 perpendicular to it. In this case, the switch transistor 133 may be provided on the front end of the sense amplifier 117 to prevent leakage current from flowing through the data lines 112 and 123.

The nonmagnetic conductive layer 124 is formed of a metal selected from Cu, Ru, Cr, Re, and Ir, or an alloy containing at least 50 atomic% Cu, Ru, Cr, Re, and Ir.

In the magnetic memory device of this embodiment, the first magnetic layer 123 and the second magnetic layer 125 connected to the nonmagnetic conductive layer 124 are formed to be separated from each other by a distance from which the coupling between the magnetic layers is removed. do. This embodiment differs in function from the embodiments of FIGS. 4 to 9. In other words, this embodiment utilizes a state in which one tunnel junction has a low resistance and the other tunnel junction has a high resistance, thereby eliminating the need for antiferromagnetic coupling between the first and second magnetic layers. Independently control the transition to achieve differential readings.

In this embodiment, since the two tunnel junctions are made in a stacked configuration, the area of the cell can be greatly reduced. If the wiring line spacing is F, the cell area is 8 to 12F ² .

<Example 10>

21 is an electrical equivalent circuit diagram of a magnetic memory cell array according to a tenth exemplary embodiment of the present invention. The same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the figure, the region enclosed by the dotted line corresponds to the memory cell 201, and two TMR elements are each connected at one end thereof to separate data lines DL and / DL, and the other end thereof is the same bit through the cell select transistor. It is connected to the line BL. The separate word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively, and the select transistors 31 and 32 and the select transistors 33 and 34 each share a drain region. The data lines DL and / DL are connected to the current detecting differential amplifier 401 through a select transistor having a word line DSL, and the bit line BL is connected to the bias voltage clamping circuit 420 through a select transistor connected to the word line BSL. Connected.

In this embodiment, the present invention is characterized in that adjacent cells share the drain region and the bit line of the select transistor. Thus, the advantage is that the number of bit lines can be halved by neighboring cells sharing the bit lines.

<Eleventh embodiment>

22 is an electrical equivalent circuit diagram of a magnetic memory cell array according to an eleventh embodiment of the present invention. The same elements as shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the drawing, the region enclosed by the dotted lines corresponds to the memory cell 201. In each cell, the TMR elements are each connected at one end thereof to the data lines DL and / DL, and the other ends thereof are connected to the remaining bit lines BL1 and BL2, respectively, through the cell select transistor. The separate word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively, and the select transistors 31 and 32 and the select transistors 33 and 34 each share a drain region. The data lines DL and / DL are connected to the current detection type differential amplifier 401 through a select transistor having a common word line DSL.

Bit lines BL1 and BL2 are connected to bit lines CBL1 and CBL2 parallel to data lines DL and / DL. Also, CBL1 and CBL2 are connected to bias voltage clamping circuit 420 through select transistors having separate word lines BSL1 and BSL2, respectively, outside of the memory cell array region.

In the present embodiment, the present invention is characterized in that the bit line BL intersects with the data lines DL and / DL and is shared by adjacent memory cell arrays. In addition, adjacent memory arrays share the BL, and finally, the BL is connected to one CBL that is parallel to the data lines DL and / DL, so that the number of lines that are paralleled to overlap on the data lines DL and / DL is determined. By reducing, it becomes possible to reduce the array area even more. In the case where the bit line BL and the word line WL become parallel to each other, the bit line BL and the word line WL are simultaneously activated to enable the memory cells in the row direction to be read at the same time, that is, to execute a so-called page mode read. do.

<Twelfth Example>

23 is an electrical equivalent circuit diagram of a magnetic memory cell array according to a twelfth embodiment of the present invention. The same as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the drawing, the region enclosed by the dotted lines corresponds to the memory cell 201. The two TMR elements each have one end connected to separate data lines DL1 and / DL, and the other end connected to the same bit line BL1 through a cell select transistor. Further, in these memory cells and memory cells adjacent to each other in the word line direction, these two TMR elements have one end connected to the data lines DL2 and / DL, respectively, and the other end of the same bit line BL2 through the cell select transistor. Is connected to. That is, data line / DL is shared by adjacent memory cells in the word line direction.

The separate word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively. The data lines DL1 and / DL are connected to the current detection type differential amplifier 401 through a select transistor having a common word line DLS1. The data line / DL is shared by adjacent memory cell arrays, but with different select transistors. The data lines DL2 and / DL are connected to the current detection type differential amplifier 401 through a selection transistor having a common word line DSL2. Here, the data lines DL1 and DL2 do not share the word lines of the select transistors in order to prevent generation of leakage current through the data lines DL2.

In this embodiment, the present invention is characterized in that adjacent memory cell arrays share a data line / DL. Thus, the data line is shared, providing the advantage that it is possible to reduce the array area even more.

<Thirteenth Example>

24 is an electrical equivalent circuit diagram of a magnetic memory cell array according to a thirteenth embodiment of the present invention. The same as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the drawing, the region enclosed by the dotted lines corresponds to the memory cell 201. The two TMR elements are each connected at one end thereof to the auxiliary data lines sDL and / sDL. The other end of each TMR element is connected to the same auxiliary bit line sBL through a cell select transistor. The separate word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively.

The auxiliary data lines sDL and / sDL and the auxiliary bit line sBL are connected to the data lines DL and / DL and the bit line BL, respectively, through select transistors having a common word line SASL. The data lines DL and / DL are connected to the current detection type differential amplifier 401 through a select transistor having a common word line DSL. The bit line BL is also connected to the bias voltage clamping circuit 420 through a select transistor having a word line BSL outside of the memory cell array region.

This embodiment is characterized in that the memory cell array is divided in the data line direction to form an auxiliary cell array. Employing such an arrangement makes it possible to reduce the number of memory cells in a cell array without significantly increasing the array area. In this way, a problem with the degradation of the output signal due to the increased number of memory cells can be avoided.

<Example 14>

25 is an electrical equivalent circuit diagram of a magnetic memory cell array according to a fourteenth exemplary embodiment of the present invention. The same as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the figure, the region enclosed by the dotted line corresponds to the memory cell 201, and two TMR elements are respectively connected at one end thereof to the auxiliary data lines sDL and / sDL. The other end of each TMR element is connected to the bit line BL through a cell select transistor, and to each of the separate bit lines BL1 to BL4 of each of the memory cells arranged in the data line direction.

The separate word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively. The auxiliary data lines sDL and / sDL are connected to the data lines DL and / DL through select transistors having a common word line SASL. The data lines DL and / DL are connected to the current detection type differential amplifier 401 through a select transistor having a common word line DSL.

In the present embodiment, the present invention is characterized in that the bit line BL intersects with the data lines DL and / DL, and the bit line BL is compatible with the write line.

<Example 15>

26 is an electrical equivalent circuit diagram of a magnetic memory cell array according to a fifteenth embodiment of the present invention. The same as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the drawing, the region enclosed by the dotted lines corresponds to the memory cell 201. In each memory cell, one end of one TMR element is connected to each data line DLR1 to DLR4, and one end of the other TMR element is connected to the same data line DLC. Also, the other end of each TMR element is connected to the same bit line BL through a cell select transistor. The separate word lines WL1 to WL4 are disposed in the cell select transistors 31 to 34, respectively. The bit line BL is connected to the bias voltage clamping circuit 420 through a select transistor having a word line BSL outside of the memory cell array region.

In the present embodiment, the present invention is characterized in that the data line pair DLR and DLC cross each other, and similarly, the BL crosses the WL. In addition, the bit lines are not shared in the word line direction. Thus, cell selection during readout can be uniquely performed by controlling the potentials of BL and WL, and a bias voltage is applied only to the selection cell. In addition, the data line pairs DLR and DLC cross each other and are therefore not shorted by unselected cells. Therefore, operation with high stability and high power consumption efficiency can be expected.

<Example 16>

27 is an electrical equivalent circuit diagram of a magnetic memory cell array according to a sixteenth embodiment of the present invention. The same as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

In the drawing, the region enclosed by the dotted lines corresponds to the memory cell 201. The two TMR elements each have one end connected to the data lines DL and / DL, and the other end thereof is connected to the same bit line BL through a cell select transistor. The separate word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively. The data lines DL and / DL are connected to the bias voltage clamping circuit 420 and the current detection differential amplifier 401 through a select transistor having a common word line DSL. In addition, the bit line BL is grounded.

In the present embodiment, the present invention is characterized in that the bit line BL has a low potential with respect to the data lines DL and / DL, and the current flows from the data lines DL and / DL through the selection transistors. In Fig. 29, the bit line potential is defined as the ground potential, but this potential may be set to any voltage within a range in which the bit line potential does not exceed the data line potential. In addition, in this embodiment, the potentials of the data lines DL and / DL are required to be exactly the same as each other. This can easily be accomplished by a bias voltage clamping circuit or a technique similar to that described.

<Example 17>

FIG. 28 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the seventeenth embodiment of the present invention. Elements such as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted here.

In the figure, the region enclosed by the dotted lines corresponds to the memory cell 201, and two TMR elements are connected to one end of the independent data lines DL and / DL, respectively. The other end of each of the TMR elements is connected to a bit line through a cell select transistor, and is connected to each of the independent bit lines BL1 to BL4 arranged in the data line direction. Independent word lines WL1 to WL4 are disposed in the select transistors 31 to 34, respectively. The data line DL is connected to the bias voltage clamping circuit 420 through a select transistor having a word line DSL, and the data line / DL is grounded. Bit lines BL1 through BL4 are each connected to their other differential sense amplifiers SA.

Next, the operation of this circuit will be described by illustrating the memory cell 201. Now, considering the case where the magnetization configurations of the recording layer and the fixing layer of the TMR element 11 are parallel to each other, these layers of the TMR element 21 are antiparallel to each other (recording information " 1 &quot;). In the initial state, the potentials of WL1 and DSL1 are zero. At that time, the potential of DSL1 is defined as VDD, and WL1 is defined as VDD while V _bias is applied to DL, thereby making the selection transistor 31 electrically conductive. When the resistance value of the TMR element 11 is defined as R (1-MR / 2) and the resistance value of the TMR element 12 is defined as R (1 + MR / 2), the voltage value to be induced in the BL is Obtained as follows.

On the other hand, when the recording information is "0", that is, when the magnetization configuration of the TMR element 11 enters the antiparallel state, and when the magnetization configuration of the TMR element 21 enters the parallel state, BL Induced voltage values are as follows.

Thus, for example, when the reference voltage of the differential sense amplifier is set to V _REF = V _bias / 2, the stored information can be determined by comparing the signal voltage of the BL with the reference voltage.

In this reading method, the ratio of the divided voltages due to the two TMR elements is detected, thus providing the following advantages.

(1) It is not dependent on the current value flowing through the TMR element. That is, even if the number of memory cells in the memory cell array changes and the impedance between data lines DL and / DL changes, the output is not affected.

(2) The bias voltage can be divided into two TMR elements, and the decrease in the magnetoresistance ratio which depends on the applied voltage can be reduced.

(3) Almost no current flows in the bit line, and variations in the characteristics of the selected semiconductor elements, in particular, variations in the source / drain resistance, can be ignored.

<Example 18>

29 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the eighteenth embodiment of the present invention. The same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the figure, the region enclosed by the dotted lines corresponds to the memory cell 201. Each of the two TMR elements has one end connected to each one of the data lines DL and DL /, and the other end connected to the same bit line BL through the cell select transistor 31. Independent word lines WL1 to WL4 are disposed in the select transistors 31 to 34. The data line DL is connected to the bias voltage clamping circuit 420 through select transistors each having a word line DSL, and the data line / DL is grounded. The bit line BL is connected to the differential sense amplifier SA through a select transistor connected to the word line BSL.

In the present invention, the bit line BL is shared by a plurality of memory cells, so that the array area can be reduced more sufficiently.

<19th Example>

30 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the nineteenth embodiment of the present invention. Elements such as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

This embodiment is basically the same as the seventeenth and eighteenth embodiments in the memory cell array structure. However, the bit line BL is divided into the auxiliary bit line sBL through the current converting circuit, and the variation of the sBL voltage generated by the read operation is passed through the bit line BL by the current converting circuit as the current difference to the main amplifier SA in the next step. Transferred. In this embodiment, the floating capacity and the wiring resistance can be reduced by reducing the length of the bit line BL, and high speed operation can be achieved by reducing the bit line delay.

<Example 20>

FIG. 31 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the twentieth embodiment of the present invention. Elements such as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the figure, the region enclosed by the dotted line corresponds to the memory cell 201, and two TMR elements have one end connected to each one of the data lines DL and / DL. The other end of each of the TMR elements is connected to the bit line BL through a cell select diode element 31 and to an independent one of each of the bit lines BL1 to BL4 through a memory cell arranged in the data line direction. The data line DL is connected to the bias voltage clamping circuit 420 through select transistors each having a word line DSL, and the data line / DL is grounded. The bit line BL is grounded through a select transistor connected to the load resistor and word line BSL.

In this embodiment, the forward threshold voltage of the diode is used for cell selection. That is, the threshold voltage value of the diode forward direction is defined as V _{To, To} is assumed to be V <V _0. Here, when the potential difference V is applied to specific data lines DL and / DL, the voltage of V ₀ -V _To or V ₁ -V _To is applied to the sense amplifier connected to the bit line group crossing the data lines DL and / DL. do. Thus, the stored information can be read by identifying its size.

As a diode element for cell selection in this embodiment, an n-type MOS transistor having a junction-type pn-diode, Schottky diode, or MIS diode, and a shorted drain / gate terminal as shown in FIG. 32 can be used. have. In general, in magnetic memory devices, MOS transistors are often used. Redundant device isolation regions are required to form the pn-diode in the semiconductor portion, which allows the cell area to be increased. Diodes using nMOS transistors do not cause such a problem and are therefore preferred embodiments.

<Example 21>

33 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the twenty-first embodiment of the present invention. Elements like those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the figure, the region enclosed by the dotted line corresponds to the memory cell 201, and two TMR elements have one end connected to each one of the data lines DL and / DL. Each other end of the TMR elements is connected to the bit line BL via a cell select diode element 31 and to an independent one of each of the bit lines BL1 to BL4 through a memory cell arranged in the data line direction. The data line DL is connected to the bias voltage clamping circuit 420 through select transistors each having a word line DSL, and the data line / DL is grounded. The bit line BL is connected to the offset voltage circuit 430 and the current sense amplifier 402.

In this embodiment according to FIG. 34, the current flowing through the bit line is measured as a function of the offset voltage V _off . Two curves represent the currents I ₀ and I ₁ corresponding to the stored information " 1 " and " 0 &quot;, respectively. Only the region where I ₀ is substantially equal to zero exists near V _off = 500 mV. In this area, the value of I ₁ / I ₂ is very large, which is very advantageous in practical terms.

The change in I ₀ and I ₁ according to such stored information can be obtained by combining the strong nonlinearity near the threshold voltage V _To of the diode with the voltage change according to the stored information. In general, the size of V _{To in} a diode is determined depending on the manufacturing method. Therefore, the method of applying the offset voltage as in this embodiment is a preferred embodiment.

<22th Example>

35 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the twenty-second embodiment of the present invention.

In the drawing, an area enclosed by a dotted line corresponds to one memory cell 201. In this memory cell 201, each of the TMR elements 11 and 21 has one end connected to an independent one of each of the data lines 41 and 42, and the other of each of the TMR elements 11 and 21. The end is commonly connected to the cell select transistor 32.

In addition, in each memory cell, independent word lines 301 to 304 are disposed in the cell select transistors 31 to 34, respectively. One end of each of the data lines 41 and 42 is connected to each one of a constant current source 401 and 402, and the other end is connected to a sense amplifier 404. The common word line 403 is disposed in the MOS transistors that make up the constant voltage sources 401 and 402. The sense amplifier 404 is a voltage latched flip-flop amplifier and has a common source terminal 405 and a data terminal 406.

Next, a method of reading information in the magnetic memory cell array according to the present invention will be described in detail.

36 shows the potential WL of the word line 302 of the cell select transistor 32, the potential DLW of the word line 403 connected to the constant current sources 401 and 402, and the data lines 41 and 42 (DL and / DL). The change in reading the potential SS of the common source terminal 405 of the sense amplifier 404 having the potential of and the time axis as the horizontal axis is shown.

Now consider the case where the magnetization of the recording layer of the TMR element 11 is antiparallel to that of the fixing layer (recording information " 1 "). In the initial state, the potential of the word line DLW and the word line WL of the cell select transistor 32 controlling the constant current sources 401 and 402 is defined as 0, and the potential of the common source terminal of the sense amplifier 404 is VD. Is defined as In this state, data lines 41 and 42 are at floating potentials and sense amplifier 404 is separated from data lines 41 and 42.

Next, the high potential V _s is applied to the DLW after WL is defined as the high potential V _cc , and the cell select transistor 32 is conductive. In this way, the sense current I _s is equal to the current flowing through the data lines 41 and 42 to the TMR elements 11 and 21. The voltage dropped in the cell select transistor 32 is defined as Vr, and the potentials of the data lines 41 and 42 are as follows.

In other words,

Is obtained as the differential voltage of the data lines 41 and 42.

In this state, a read pulse that changes from VD to zero is then applied to the common source terminal 405 of the sense amplifier 404 as shown. When the potential difference between DL and SS exceeds the threshold potential Vth of the transistor, the transistor connected to the data line 42 at a low potential starts to discharge. As a result, the data line 41 maintains the initial potential Vd and the other data line 42 is latched to 0V.

In the case of the write information "0 ", the magnetization of the recording layer of the TMR element 11 is parallel to that of the fixed layer, and the data line 11 is at a low potential while the sensing current is supplied. Therefore, the read pulse is When applied, data line 41 is latched to 0V. Thus, after a predetermined period of time, a pulse is applied to the common source terminal 405, and the voltage D of the data line 41 is obtained using the terminal 406 of the sense amplifier, so that reading is performed. After reading the data, the potential of each terminal is restored to the initial state as shown, so that the latch of the sense amplifier 404 is reset and the read operation is completed.

In the configuration of this embodiment, the magnitude ψ of the read pulse applied to the common source terminal 405 of the sense amplifier 404 is

VD'≤ψ≤VD

That is, the margin associated with the pulse size corresponds approximately to the differential voltage between the data lines during reading. In order to stabilize the operation of this part, (1) a voltage amplifying circuit at the front end of the sense amplifier; And (2) a circuit or the like for compensating for the deviation between VD and VD '. Although a flip-flop amplifier is used in this embodiment, other amplification circuits, for example, current mirror amplifiers, can be used for the sense amplifiers.

37 is a diagram schematically showing the overall configuration of the magnetic memory cell array according to the present embodiment. The memory cell array includes memory cells arranged in two dimensions; A data line group connected to these memory cells; Word line groups; And a write line group crossing adjacent to the memory cell. The pair of write lines RWL and CWL are connected to the column decoder and the row decoder to enable selective writing corresponding to the external address input.

On the other hand, the word line DWL for driving the data line pair DL and / DL and the word line WL for driving the cell select transistor orthogonal to these word lines are connected to the column decoder and the row decoder, respectively, to correspond to the external address input. Enable selective reading. A sense amplifier SA is provided for each pair of data lines and is driven by a common word line SS. Next, the read data is read through the common data line D.

In this manner, in this embodiment, one memory cell (e.g., 201) is manufactured by two TMR elements (e.g., 11 and 12), and the memory cell is formed of write lines (parallel to each other). Disposed at the intersection between each of 51a and 51b and the write line 52 orthogonal to these write lines. Therefore, current is supplied to the write lines 51a and 51b and the write line 52 so that data can be selectively written to any memory cell.

The directions of the currents flowing through the write lines 51a and 51b are opposite to each other, and the magnetization patterns of the recording regions 101 of the two TMR elements 11 and 12 constituting one memory cell 201 are antiparallel to each other. to be. Therefore, during the storage information reading operation, the difference between the outputs of the TMR elements 11 and 12 is obtained so that a differential signal larger than that of the prior art can be obtained. In addition, the TNR elements 11 and 12 share the same cell select transistor 32, so that it is possible to completely eliminate the offset of the output signal caused by the variation of the transistor characteristics.

Therefore, according to the present invention, the cell output signal during the read operation can be increased, and the signal-noise ratio can be improved without any increase in power consumption and stabilization time during reading. Therefore, low power consumption can be compatible with fast read characteristics.

As described in detail above, the magnetic memory cell array structure of the present invention can achieve significantly higher output and lower noise than using conventional techniques during information reading. Therefore, a solid magnetic memory device in which low power consumption and fast read characteristics are compatible can be provided.

Additional advantages and modifications will be readily apparent to those skilled in the art. Therefore, the invention in its broader scope is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the general inventive concept as defined in the appended claims and their equivalents.

Claims (33)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete In a magnetic memory device, The first anchoring layer 121 having a fixed magnetization direction, the first tunnel barrier 122 overlapping the first anchoring layer, and the magnetization direction are superimposed on the first tunnel barrier 122 and according to an external magnetic field. The first and second magnetic layers 123 that are changing, the second magnetic layers 125 whose magnetization directions change according to the external magnetic field, and the first and second states in which their magnetic moments are substantially antiparallel to each other. A laminate composed of a nonmagnetic conductive layer 124 inserted between magnetic layers, A second tunnel barrier 126 superimposed on the second magnetic layer 125, and Second fixing layer 127 overlying the second tunnel barrier 126. Tunnel junction comprising a; A semiconductor device 114 electrically connected to at least one of the first magnetic layer 123, the nonmagnetic conductive layer 124, and the second magnetic layer 125; And Current between the first tunnel current flowing through the first magnetic layer 123 and the first fixing layer 121 and the second tunnel current flowing through the second magnetic layer 125 and the second fixing layer 127. Detecting means 117 for detecting a difference or a load voltage difference in a differential manner Magnetic memory device comprising a. The method of claim 27, A bit line electrically connected to at least one of the first magnetic layer 123, the nonmagnetic conductive layer 124, and the second magnetic layer 125 through the semiconductor device 114; A first data line (113) electrically connected to the first fixing layer (121); And A second data line 112 electrically connected to the second fixing layer 127. Magnetic memory device further comprising. 29. The magnetic memory device of claim 27 or 28, wherein the semiconductor device comprises a transistor (114) or a diode. 29. A magnetic memory device according to claim 27 or 28, wherein the detection means comprises a sense amplifier (117) and a transistor (133) through which the sense amplifier is connected to the data line (113). 29. The magnetic memory device of claim 27 or 28, wherein the first and second magnetic layers (123, 125) are different in thickness from one another. 29. The magnetic memory device of claim 27 or 28, wherein the first and second magnetic layers (123, 125) are made of a magnetic material having a high magnetoresistance ratio. 29. The magnetic memory device of claim 27 or 28, wherein the first magnetic layer (123) is anti-ferromagnetically coupled to the second magnetic layer (125).