JP4481697B2 - Phase change memory device - Google Patents

Description

  The present invention relates to a phase-change random access memory (PRAM), and more particularly to a phase change memory device that can be selectively operated with a nonvolatile memory and a volatile memory, and a method of operating the phase change memory device.

  PRAM is a memory device using a material called chalcogenide whose electrical resistance changes depending on the crystalline state of the material. The state of chalcogenide changes between an amorphous state and a crystalline state. The difference in resistance value that appears due to the two states is used to distinguish the logic values of the memory cells. That is, the non-crystalline state shows a high resistance value, and the crystalline state shows a low resistance value.

  FIG. 1 is a diagram illustrating state transition between setting and resetting of a phase change memory cell.

  Referring to FIG. 1, the phase change memory cell includes an upper electrode 101 and a lower electrode 102, a resistance heater 103 such as BEC, and a phase change material 104 such as a chalcogenide alloy. The state of the phase change material 104 is determined by Joule heating corresponding to the amount of current passing through the resistance heater 103.

  When a high current pulse (reset pulse) is applied to the phase change film for a short time to raise the temperature of the phase change film to the melting temperature (about 610 ° C) and then rapidly cooled, the phase change film has an amorphous state with high resistance ( Reset state).

  On the other hand, when a low current pulse (set pulse) is applied to the phase change film and the phase change film is cooled at a crystallization temperature (about 450 ° C.) for several tens of ns, the phase change film has a crystalline state with low resistance ( Set state).

  FIG. 2 is a diagram showing the relationship between the state of the phase change memory and the temperature.

  Referring to FIG. 2, when the phase change material is heated to the melting temperature Tm or more and rapidly cooled in about several nanoseconds, the phase change material becomes an amorphous state. The crystalline state is created by heating the phase change material below the melting temperature Tm and above the crystallization temperature Tx for a long time (about 50 nanoseconds).

  FIG. 3 is a diagram for explaining voltage-current characteristics of a phase change memory cell.

  FIG. 3 illustrates the case of a phase change material made of a chalcogenide alloy. In FIG. 3, a set current between 1.0 mA and 1.5 mA is for bringing the phase change cell into a crystalline state, and a reset current between 1.5 mA and 2.5 mA brings the phase change cell into an amorphous state. Is to do.

  By applying a read voltage with a voltage lower than a predetermined threshold voltage Vt (a voltage lower than about 0.5 V) during the read operation, the difference in resistance between the amorphous state and the crystalline state can be distinguished. Here, the threshold voltage Vt is a voltage at which the current of the phase change material in the amorphous state and the crystalline state becomes the same.

  It is known that a PRAM using a phase change material is basically a nonvolatile memory. The non-volatile memory means a memory that does not require a refresh operation for holding data, such as a general DRAM.

  In order to improve the property as a nonvolatile memory, that is, data retention, the ratio of the resistance in the reset state and the resistance in the set state of the phase change material must be large. This resistance ratio varies depending on the specific PRAM cell structure, but is usually several tens to several hundred times.

  A large resistance ratio can widen the sensing margin and improve the data retention capability that needs to be possessed as a non-volatile memory. However, in order for the PRAM to have such a large resistance ratio, a large current of about several mA must be passed through the phase change film, and there is a problem that power consumption due to the large current increases.

  Instead of using both the existing nucleation mechanism and growth mechanism in the phase change process of chalcogenide materials, using only the nucleation mechanism gives a resistance ratio several times between the reset state and the set state. There is no problem in reading. At this time, the current flowing through the phase change film is only a few tens of uA, and power consumption can be greatly reduced.

  However, there is a problem in that the data holding capability is reduced, the nucleus is not grown by the current for reading data, and the read interference that decomposes the nucleus becomes intense. In addition, data may be erased by repeated data read operations.

  Therefore, if data is rewritten after data is read out as in the case of DRAM and periodically refreshed to the PRAM, the PRAM can be driven with a low current.

  The technical problem to be solved by the present invention is to provide a PRAM operating method capable of driving a PRAM device with a small current like a volatile memory.

  Another technical problem to be solved by the present invention is to provide a PRAM device that can be driven with a small current like a volatile memory.

  In order to achieve the above technical problem, a PRAM device according to a preferred embodiment of the present invention includes a PRAM cell, a write current source, and a recovery circuit.

The PRAM cell includes a phase change material that undergoes a state transition between an amorphous state and a crystalline state. The write current source selectively applies a first write current pulse for bringing the PRAM cell into an amorphous state and a second write current pulse for bringing the PRAM cell into a crystalline state. The recovery circuit selectively applies the first write current pulse to the PRAM cell to recover the PRAM cell to an amorphous state.
The PRAM cell operates in a volatile mode or a non-volatile mode. In the non-volatile mode, the recovery circuit is deactivated, and in the volatile mode, the recovery circuit is activated.

  In order to achieve the above technical problem, a PRAM device according to a preferred embodiment of the present invention includes a PRAM cell, a write current source, and a recovery circuit.

  The PRAM cell includes a phase change material that undergoes a state transition between an amorphous state and a crystalline state. The write current source selectively applies a first write current pulse for bringing the PRAM cell into an amorphous state and a second write current pulse for bringing the PRAM cell into a crystalline state in a low power mode, A third write current pulse for bringing the PRAM cell into an amorphous state and a fourth write current pulse for bringing the PRAM cell into a crystalline state are selectively applied in a high power mode.

  The recovery circuit selectively applies the first write current pulse to the PRAM cell in order to recover the PRAM cell to an amorphous state in the low power mode.

  A PRAM device according to a preferred embodiment of the present invention for achieving the technical problem includes a PRAM cell and a recovery circuit.

  The PRAM cell operates in a nonvolatile memory mode or a volatile memory mode, and includes a phase change material that changes state between an amorphous state and a crystalline state.

  A restoration circuit restores the PRAM cell to an amorphous state in the volatile memory mode.

  A PRAM device according to a preferred embodiment of the present invention for achieving the technical problem includes a data line, a plurality of input / output lines, a plurality of bit lines, a plurality of word lines, and the word lines and bit lines. And a plurality of PRAM cells, a write current source, a plurality of sense amplifier circuits, and a recovery circuit.

  Each PRAM cell includes a phase change material that undergoes a state transition between an amorphous state and a crystalline state.

  The write current source has a first write current pulse for bringing the PRAM cell into an amorphous state and a second write current pulse for bringing the PRAM cell into a crystalline state according to the voltage of the data line. Apply.

A plurality of sense amplifier circuits are connected to the bit line and the input / output line, respectively, and read the state of the PRAM cell. A recovery circuit is connected to the input / output line and the data line, and controls the voltage of the data line to recover the PRAM cell to an amorphous state.
The PRAM cell operates in a volatile mode or a non-volatile mode. In the non-volatile mode, the recovery circuit is deactivated, and in the volatile mode, the recovery circuit is activated.

  The PRAM operating method and PRAM device according to the present invention can reduce power consumption by operating a PRAM, which is a nonvolatile memory, like a volatile memory. Further, depending on the application field, the PRAM can be selected and used as either a volatile memory or a nonvolatile memory.

  For a full understanding of the invention and the operational advantages thereof and the objects achieved by the practice of the invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the invention and the contents described in the drawings. I have to.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers provided in each drawing indicate similar components.

  A conventional PRAM device is a nonvolatile device, and the phase change to an amorphous state includes a nucleation process and a nucleation growth process. On the other hand, the present invention is characterized in that the phase change to an amorphous state is operated in a volatile memory mode (or a low power mode) including only a nucleation process.

  Also, in the volatile mode, the write current for writing the amorphous state or writing the crystalline state into the PRAM device according to the preferred embodiment of the present invention is even smaller than in the conventional PRAM device. That is, power consumption is reduced.

  In addition, the resistance ratio between the non-crystalline state and the crystalline state is reduced, but the ratio is still sufficient for reading data.

  Table 1 is a table showing the write current when the phase change material is chalcogenide and the PRAM device according to the preferred embodiment of the present invention is in the nonvolatile mode and in the volatile mode.

As can be seen from Table 1, the current value of the write current in the volatile mode is smaller than the current value in the nonvolatile mode. In two modes, the current value of the amorphous (reset) write current pulse is larger than the current value of the crystal (set) write current pulse. The pulse width of the amorphous write current pulse is narrower than the pulse width of the crystal write current pulse.
However, the current value of the reset write current pulse need not exceed the current value of the set write current pulse in the volatile mode. For example, the current value of the reset write pulse and the current value of the set write pulse may be the same, or only the pulse width and the quenching time may be different.

  Here, the term “non-crystalline state” can have the following meaning. That is, it means that the portion of the phase change material is more amorphous than the portion of the crystalline state and that the phase change material has a higher degree of non-crystallinity than the crystalline state.

  Both are volatile modes, and the phase change material or most of the phase change material portion need not be in an amorphous state. The low write current in the volatile mode need only be sufficient to change the crystal structure in order to obtain a sufficient resistance ratio between the amorphous and crystalline states.

  In the conventional non-crystal writing operation, only the nucleation process is performed, so that the time for holding data is short. However, in the present invention, the short data retention time is compensated by periodically restoring the non-crystalline state of the precharge cell.

  FIG. 4 is a circuit diagram for explaining a write operation and a read operation of the PRAM device.

  In FIG. 4, one bit of the PRAM device is composed of a combination of two cells having opposite logic states.

  Using two cells for one bit broadens the operating area of the PRAM device and prevents operating errors caused by resistive distribution.

  The gate of the cell transistor PTRi1 is connected to the word line WLi, and the phase change cell PCELLi1 is connected between the drain of the cell transistor PTRi1 and the bit line BL. The gate of the cell transistor PTRi2 is connected to the word line WLi, and the phase change cell PCELLi2 is connected between the drain of the cell transistor PTRi2 and the inverted bit line / BL.

  In the same manner, the gate of the cell transistor PTRj1 is connected to the word line WLj, and the phase change cell PCELLj1 is connected between the drain of the cell transistor PTRj1 and the bit line BL. The gate of the cell transistor PTRj2 is connected to the word line WLj, and the phase change cell PCELLj2 is connected between the drain of the cell transistor PTRj2 and the inverted bit line / BL.

  The current source ISET1 and the current source ISET2 each apply a set current pulse to the bit line pair BL, / BL. The control transistors CTR and / CTR are connected to one end of the bit line pair and receive a reset current pulse from the current source IRESET.

  The clamp circuits 210 and 220 are respectively connected to one end of the bit line pair BL and / BL, and the other end is connected to the sense amplifier circuit S / A.

  A write operation for writing data to the PRAM device 200 will be described. Assume that a logical value “1” is written to PRAM cells PCELLi1 and PCELLi2. In this case, the word line WLi is set to the high level, and the data signal D and the inverted data signal / D become high and low, respectively.

  As a result, the transistors PTRi1, PTRi2, and CTR are turned on, and the transistor / CTR is turned off.

  Since the transistor / CTR is turned off, the set current pulse ISET2 flows through the phase change material PCELLi2 and the cell transistor PTRi2. The set current pulse ISET2 is a current that can change the phase change material to a low resistance crystalline state.

  The set current pulse ISET2 passes through the phase change material PCELLi2 and flows to the ground. The phase change material PCELLi2 is changed to a low resistance crystal state by the set current pulse ISET2. The crystalline state can be regarded as a logical “0”.

  Conversely, since the transistor CTR is turned on, the reset current pulse IRESET flows to the PRAM cell PCELLi1 and the transistor PTRi1. Although not shown in FIG. 4, the current pulse ISET1 is controlled and synchronized by the reset current pulse IRESET. Therefore, the pulse width and timing of the current pulse ISET1 are the same as the reset current pulse IRESET.

  The reset current pulse IRESET and the set current pulse ISET1 are combined to bring the PRAM cell PCELLi1 into the reset state. The reset state can be regarded as a logic “1” as a high resistance state.

  Hereinafter, a read operation for reading data written in PRAM device 200 will be described.

  The clamp circuits 210 and 220 limit the voltage of the bit line pair BL and / BL to be smaller than the threshold voltage in order to reduce noise between read operations. Assume that the word line WL1 is in the high state, the low resistance of the PRAM cell PCELLi2 lowers the current level of the inverted bit line / BL, and the high resistance of the PRAM cell PCELLi1 increases the current level of the bit line BL.

  Each current of the bit line pair BL, / BL is compared by the sense amplifier circuit S / A to distinguish the logical values of the PRAM cells PCELLi1, PCELLi2.

  Conventional PRAM devices are generally non-volatile memories. In other words, once data is written, it cannot be erased, so a refresh operation like DRAM is unnecessary. However, when data is written to the PRAM 200, power consumption is very large.

  Accordingly, the present invention provides a method and a PRAM device for driving PRAM with low power by rewriting data like DRAM and periodically refreshing at the time of data reading.

  FIG. 5 is a flowchart for explaining a PRAM operating method according to a preferred embodiment of the present invention.

  Referring to FIG. 5, the operation method 300 of the PRAM device according to the preferred embodiment of the present invention is performed in step 310 for reading data stored in a memory cell and transmitting the read data to the outside. In operation 320, the data is rewritten in the memory cell in which the data is originally stored.

  Taking the operation in 310 steps as an example, in the structure of FIG. 4, the currents of the bit line pair BL, / BL are compared in the sense amplifier circuit S / A to distinguish the logical values of the PRAM cells PCELLi1, PCELLi2. The Taking the operation in 320 steps as an example, the same read data is applied as the data signal D and the inverted data signal / D to the previously read cells PCELLi1 and PCELLi2 in the structure of FIG.

  The data recovery operation (step 320) may be performed for each phase change cell read operation. Alternatively, it is performed at regular time intervals, for example, about every hour.

  FIG. 6 is a circuit diagram showing a PRAM device according to a preferred embodiment of the present invention.

  Referring to FIG. 6, a PRAM device 400 according to a preferred embodiment of the present invention includes a memory array block 410, a data circuit 420, a read circuit 430, global input / output lines GIO, / GIO, local input / output lines LIO, / LIO and current source 440.

  The data circuit 420 includes a plurality of transistors CTR1, CTR2 to CTRm, / CTR1, and / CTR2 to / CTRm. The transistors CTR1, CTR2 to CTRm connect / disconnect the reset current IRESET and the bit lines BL1, BL2 to BLm. Transistors / CTR1, / CTR2 to / CTRm connect / disconnect the reset current IRESET and the inverted bit lines / BL1, / BL2 to / BLm.

  The data circuit 420 includes first and second rewrite control transistors RTR1 and RTR2.

  In response to the rewrite control signal RWCTRL, the first rewrite control transistor RTR1 connects the first global input / output line GIO among the global input / output lines and the gates of the transistors / CTR1, / CTR2 to / CTRm. Connect / disconnect.

  In response to the rewrite control signal RWCTRL, the second rewrite control transistor RTR2 connects / disconnects the second global input / output line / GIO and the gates of the transistors CTR1, CTR2 to CTRm among the global input / output lines. To do.

  Memory array block 410 includes a plurality of PRAM cells connected to word lines WL1, WL2 to WLn and bit line pairs BL1, / BL1, BL2, / BL2 to BLm, / BLm. Each PRAM cell is connected as shown in FIG.

  The readout circuit 430 includes a plurality of sensing circuits STM1, STM2 to STMm.

  The sensing circuits STM1, STM2 to STMm are connected to the corresponding bit lines BL1, BL2 to BLm and inverted bit lines / BL1, / BL2 to / BLm to receive and amplify the data stored in the PRAM cell, and to select the column selection signal In response to CD1, CD2 to CDm, the data is transmitted to the local input / output lines LIO, / LIO.

  Each of the sensing circuits STM1, STM2 to STMm includes sense amplifier circuits S / A1, S / A2 to S / Am, first transmission transistors TTR11, TTR21 to TTRm1, and second transmission transistors TTR12, TTR22 to TTRm2. The sense amplifier circuits S / A1, S / A2 to S / Am are connected to corresponding bit lines BL1, BL2 to BLm and inverted bit lines / BL1, / BL2 to / BLm.

  The first transmission transistors TTR11, TTR21 to TTRm1 receive the bit line information output from the sense amplifier circuits S / A1, S / A2 to S / Am in response to the corresponding column selection signals CD1, CD2 to CDm as local input / output lines. Is transmitted / blocked to the second local I / O line / LIO.

  The second transmission transistors TTR12, TTR22 to TTRm2 are inverted bit lines / BL1, / BL2 output from the sense amplifier circuits S / A1, S / A2 to S / Am in response to the corresponding column selection signals CD1, CD2 to CDm. ~ / BLm information is transmitted / blocked to the first local I / O line LIO among the local I / O lines.

  Although not shown in FIG. 6, the readout circuit 430 further includes a plurality of clamp circuits as shown in FIG.

  The sense amplifier circuit 450 and the transmission switch SWTR are connected in series between the local input / output lines LIO, / LIO and the global input / output lines GIO, / GIO.

  Hereinafter, the writing operation of the PRAM device of FIG. 6 will be described. It is assumed that logic “1” is written to the bit line pair BL1, / BL1 of the selected word line among the word lines WL1 to WLn. In this case, the selected word line is at a high level, and the data signals D and / D are at a high level and a low level, respectively.

  This turns on transistor CTR1 and turns off transistor / CTR1. Since the transistor / CTR1 is turned off, only the set current pulse ISET2 is applied to the PRAM cell of the selected word line through the inverted bit line / BL1. The set state is a low resistance state that is considered a logic “0”.

  Conversely, since the transistor CTR1 is turned on, the reset current pulse IRESET and the set current pulse ISET1 are applied to the selected PRAM cell of the word line through the bit line BL1.

  Although not shown in FIG. 6, the current pulse ISET1 is controlled and synchronized by the reset current pulse IRESET. Therefore, the pulse width and timing of the current pulse ISET1 are the same as the reset current pulse IRESET.

  The reset current pulse IRESET and the set current pulse ISET1 are combined to bring the PRAM cell PCELLi1 into the reset state. The reset state can be regarded as a logic “1” as a high resistance state.

  As shown in FIG. 7, the current source 440 includes a high current source 701 and a low current source 702. The high current source 701 outputs a reset current pulse IRESET, and the low current source 702 outputs set pulses ISET1 and ISET2.

  The current values and pulse widths of the reset current pulse IRESET, the set pulses ISET1, and ISET2 vary depending on whether the PRAM device operates in the nonvolatile mode or the volatile mode.

  Table 2 illustrates an example of using chalcogenides for PRAM cells.

The read operation of the circuit of FIG. 6 is performed in the same manner as the read operation of the circuit of FIG.
FIG. 8A shows the voltage-current characteristics of the PRAM cell in the nonvolatile mode, and FIG. 8B shows the voltage-current characteristics of the PRAM cell in the volatile mode. FIG. 8 illustrates a case where the phase change cell is a chalcogenide as an example.

  Referring to FIG. 8A, the resistance ratio between the set resistor Rset and the reset resistor Rreset is large when the read voltage is smaller than 0.5V. The set resistance Rset and the reset resistance Rreset become the same (Rdyn) at the threshold voltage Vt or higher.

  On the other hand, referring to FIG. 8B, the threshold voltage Vt level in the volatile mode is smaller than the threshold voltage Vt level in the nonvolatile mode. In the volatile mode, the resistance ratio between the set resistor Rset and the reset resistor Rreset is small. Nevertheless, this resistance ratio is still sufficient for sensing for the read operation, and in particular, a PRAM device having the structure of FIG. 4 is also sufficient.

  Referring to FIG. 6, data of selected memory cells of bit lines / BL1 to / BLm are transmitted to the local input / output line LIO in response to column selection signals CD1 to CDm. Further, the data of the selected memory cells of the bit lines BL1 to BLm are transmitted to the inverted local input / output line / LIO in response to the column selection signals CD1 to CDm.

  Data is transmitted to the global input / output line pair GIO, / GIO by the transmission switch SWTR controlled by the control signal BAS and the amplifier circuit 450.

  As described above, the characteristic of the volatile mode is that the time for storing data in the PRAM cell is short, particularly in the non-crystalline state. Accordingly, the embodiment of FIG. 6 includes circuitry for recovering data stored in volatile mode.

  That is, the global input / output lines are selectively connected to the data lines for transmitting the data signals D and / D by the first and second rewrite control transistors RTR1 and RTR2 controlled by the rewrite control signal RECTRL. The

  In this state, the read data appearing on the global input / output line pair GIO, / GIO is rewritten to the PRAM cell in the same manner as described for the normal data write operation.

  When the PRAM device 400 of FIG. 6 is in the non-volatile mode, the rewrite control signal RWCTRL is at a low level, so that the global input / output line pair GIO, / GIO is separated from the data line. When the PRAM device 400 of FIG. 6 is in the volatile mode, the rewrite control signal RWCTRL is at a high level, and thus the global input / output line pair GIO, / GIO is connected to the data line.

  Data is stored again in this manner in volatile mode. In volatile mode, the data lines are also coupled to local input / output line pairs (LIO, / LIO). As described above, the data recovery operation in the volatile mode is performed every time data stored in the PRAM array 410 is read.

  The data recovery operation is performed at regular time intervals, for example, the time interval can be one hour or more.

  As described above, the optimal embodiment has been disclosed in the drawings and specification. Although specific terms are used herein, they are merely used for the purpose of describing the present invention and limit its meaning or limit the scope of the present invention described in the claims. It was not used to do. Therefore, those skilled in the art can understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined based on the description of the claims.

  The present invention is used in the field of semiconductor memory devices, and is particularly applicable to the field of memory using PRAM cells.

6 is a diagram illustrating state transition between setting and resetting of a PRAM cell. It is drawing which shows the relationship between the state of PRAM, and temperature. 2 is a diagram illustrating voltage-current characteristics of a PRAM cell. It is a circuit diagram for explaining a write operation and a read operation of the PRAM device. 3 is a flowchart illustrating an operation method of a PRAM according to a preferred embodiment of the present invention. 1 is a circuit diagram illustrating a PRAM device according to a preferred embodiment of the present invention. FIG. 7 is a circuit diagram illustrating the current source of FIG. 3 is a diagram illustrating voltage-current characteristics of a PRAM cell when a PRAM device according to a preferred embodiment of the present invention is in a nonvolatile mode and in a volatile mode. 3 is a diagram illustrating voltage-current characteristics of a PRAM cell when a PRAM device according to a preferred embodiment of the present invention is in a nonvolatile mode and in a volatile mode.

Explanation of symbols

400 PRAM device 410 Memory array block 420 Data circuit 430 Read circuit
GIO, / GIO global I / O line
LIO, / LIO Local I / O line 440 Current source

Claims (35)

A phase change memory cell comprising a phase change material that transitions between an amorphous state and a crystalline state;
A write current source for selectively applying a first write current pulse for bringing the phase change memory cell into an amorphous state and a second write current pulse for bringing the phase change memory cell into a crystalline state;
A recovery circuit that selectively applies the first write current pulse to the phase change memory cell to restore the phase change memory cell to an amorphous state ;
The phase change memory cell operates in a volatile mode or a nonvolatile mode, the recovery circuit is deactivated in the nonvolatile mode, and the recovery circuit is activated in the volatile mode. Change memory device.   The phase change memory device according to claim 1, further comprising a read circuit that reads a state of the phase change memory cell, wherein the recovery circuit is controlled by an output of the read circuit. The recovery circuit is
3. The read circuit applies the first write current pulse to the phase change memory cell when the output of the read circuit indicates that the phase change memory cell is in an amorphous state. The phase change memory device according to 1.   4. The phase change memory device according to claim 3, wherein the output of the read circuit is a global input / output line of the phase change memory device.   4. The phase change memory device according to claim 3, wherein an output of the read circuit is a local input / output line of the phase change memory device. The phase change material is:
The phase change memory device according to claim 1, wherein the phase change memory device is a chalcogenide alloy. The first write current pulse is:
2. The phase according to claim 1, wherein the phase has a larger current value than the second write current pulse, and the pulse width of the first write current is narrower than the pulse width of the second write current pulse. Change memory device. The first write current pulse is:
The first write current pulse has the same current value, the pulse width of the first write current is different from the pulse width of the second write current pulse, and the kenching time of the first write current is The phase change memory device according to claim 1, wherein the phase change memory device is different from a quenching time of two write current pulses. A phase change memory cell comprising a phase change material that transitions between an amorphous state and a crystalline state;
Selectively applying a first write current pulse for bringing the phase change memory cell into an amorphous state and a second write current pulse for bringing the phase change memory cell into a crystalline state in a low power mode; A write current for selectively applying a third write current pulse for bringing the phase change memory cell into an amorphous state and a fourth write current pulse for bringing the phase change memory cell into a crystalline state in a power mode Source and
A recovery circuit that selectively applies the first write current pulse to the phase change memory cell to restore the phase change memory cell to an amorphous state in the low power mode;
A phase change memory device comprising: The low power mode is:
The phase change memory device of claim 9 , wherein the phase change memory device is a volatile mode, and the high power mode is a nonvolatile mode of the phase change memory device. The phase change memory device according to claim 9 , further comprising a read circuit that reads a state of the phase change memory cell, wherein the recovery circuit is controlled by an output of the read circuit. 12. The phase change memory device according to claim 11 , wherein the output of the read circuit is a global input / output line of the phase change memory device. 12. The phase change memory device according to claim 11 , wherein the output of the read circuit is a local input / output line of the phase change memory device. The recovery circuit is
If the output of the read circuit indicates that the phase change memory cell is in an amorphous state, the read circuit applies the first write current pulse to the phase change memory cell in the low power mode. The phase change memory device according to claim 11 . The phase change material is:
The phase change memory device according to claim 9 , wherein the phase change memory device is a chalcogenide alloy. The first write current pulse is:
The phase of claim 9 , wherein the phase has a larger current value than the second write current pulse, and the pulse width of the first write current is smaller than the pulse width of the second write current pulse. Change memory device. The first write current pulse is:
The first write current pulse has the same current value, the pulse width of the first write current is different from the pulse width of the second write current pulse, and the kenching time of the first write current is The phase change memory device according to claim 9 , wherein the phase change memory device is different from a quenching time of two write current pulses. 10. The phase change memory device of claim 9 , wherein current values of the third and fourth write current pulses are greater than current values of the first and second write current pulses. 11. A phase change memory cell comprising a phase change material that operates in a non-volatile memory mode or a volatile memory mode and transitions between an amorphous state and a crystalline state;
A recovery circuit for recovering the phase change memory cell to an amorphous state in the volatile memory mode;
A phase change memory device comprising: The phase change memory device of claim 19 , wherein the state of the phase change memory cell is not restored in the nonvolatile memory mode. When the phase change material is in an amorphous state, the non-crystalline portion of the phase change material in the volatile memory mode is the non-crystalline portion of the phase change material in the nonvolatile memory mode. 20. The phase change memory device of claim 19 , wherein there are fewer. When the phase change material is in a non-crystalline state, the degree of non-crystallinity of the non-crystalline state portion of the phase change material in the nonvolatile memory mode is the phase change material in the volatile memory mode. The phase change memory device according to claim 19 , wherein the phase change memory device has a degree of non-crystallinity greater than that of the non-crystalline portion. 20. The phase change memory device according to claim 19 , further comprising a read circuit for reading a state of the phase change memory cell, wherein the recovery circuit is controlled by an output of the read circuit. The recovery circuit is
24. The phase of claim 23 , wherein if the output of the read circuit indicates that the phase change memory cell is in an amorphous state, the recovery circuit restores the phase change memory cell to an amorphous state. Change memory device. The recovery circuit is
25. The phase change memory of claim 24 , wherein if the output of the read circuit indicates that the phase change memory cell is in a crystalline state, the restoration circuit restores the phase change memory cell to a crystalline state. apparatus. 24. The phase change memory device of claim 23 , wherein an output of the read circuit is a global input / output line of the phase change memory device. 24. The phase change memory device according to claim 23 , wherein an output of the read circuit is a local input / output line of the phase change memory device. The phase change material is:
The phase change memory device according to claim 19 , wherein the phase change memory device is a chalcogenide alloy. Data lines,
Multiple I / O lines;
Multiple bit lines,
Multiple word lines,
A plurality of phase change memory cells disposed at intersections of the word lines and the bit lines;
Each of the phase change memory cells includes a phase change material that undergoes a state transition between an amorphous state and a crystalline state;
A first write current pulse for bringing the phase change memory cell into an amorphous state and a second write current pulse for bringing the phase change memory cell into a crystalline state are applied to the bit line according to the voltage of the data line. Write current source to
A plurality of sense amplifier circuits connected to the bit lines and the input / output lines, respectively, for reading the state of the phase change memory cells;
A recovery circuit connected to the input / output line and the data line and controlling a voltage of the data line to recover the phase change memory cell to an amorphous state ;
The phase change memory cell operates in a volatile mode or a nonvolatile mode, the recovery circuit is deactivated in the nonvolatile mode, and the recovery circuit is activated in the volatile mode. Change memory device. The recovery circuit is
30. The phase change memory device of claim 29 , wherein a voltage of the data line is controlled to restore the phase change memory cell to a crystalline state. The write current source is
Claim 30, characterized in that said volatile mode to apply a first and second write current pulse to the bit line, applying a third and fourth write current pulse to the bit line in the non-volatile mode The phase change memory device according to 1. The first write current pulse is:
32. The phase of claim 31 , wherein the phase has a larger current value than the second write current pulse, and the pulse width of the first write current is smaller than the pulse width of the second write current pulse. Change memory device. The first write current pulse is:
The first write current pulse has the same current value, the pulse width of the first write current is different from the pulse width of the second write current pulse, and the kenching time of the first write current is 32. The phase change memory device according to claim 31 , wherein the phase change memory device is different from a quenching time of two write current pulses. 32. The phase change memory device of claim 31 , wherein current values of the third and fourth write current pulses are greater than current values of the first and second write current pulses. The phase change material is:
30. The phase change memory device according to claim 29 , wherein the phase change memory device is a chalcogenide alloy.

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