JP5259279B2 - Semiconductor device and control method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a volatile data storage element and a control method thereof.

  Data storage elements used in semiconductor devices include volatile storage elements such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and non-volatile storage such as flash memory and EEPROM (Erasable Programmable Read Only Memory). Memory elements. Volatile storage elements can write and read data at high speed, but have a characteristic of poor data retention. On the other hand, a non-volatile memory element is excellent in data retention, but has a characteristic that data writing / reading speed is slower than that of a volatile memory element.

  In recent years, data storage elements called phase-change random access memories have been developed. The phase change memory is a storage element that uses two different crystal states of the phase change material as storage information. By making the phase change material into an amorphous state which is a high resistance state and a crystalline state which is a low resistance state, data of logic “0” and “1” can be stored.

For example, Patent Document 1 discloses a technique for selectively operating a phase change memory as a volatile storage element and a nonvolatile storage element. For example, Patent Document 2 discloses a technique capable of performing multilevel storage by forming an intermediate state between an amorphous state and a crystalline state in a phase change memory. Patent Document 3 discloses a technique for selectively refreshing memory cells in a nonvolatile memory device.
JP 2004-296076 A JP 2003-100084 A JP 2004-355793 A

  When a data storage element that stores data using a resistance value of a variable resistor is used as a volatile storage element, it is required to perform refreshing at regular intervals to extend the data holding time.

  Therefore, the present invention provides a semiconductor device capable of refreshing and extending the data retention time when a data storage element using a variable resistor is used as a volatile storage element, and a control method thereof. Objective.

  According to the present invention, there is provided a data storage element having a first mode for storing data by changing a variable resistance to either a low resistance state or a high resistance state, and a data storage element for storing data in the first mode. Determine whether the resistance state or the high resistance state, and store data in the first voltage condition and the first mode for setting the data storage element storing data in the first mode to the low resistance state A refresh control circuit that refreshes the data storage element that stores data in the first mode according to any of the second voltage conditions for causing the data storage element to be in a high resistance state. Device. According to the present invention, the data storage element that stores data in the first mode can be refreshed, and the data retention time of the data storage element that stores data in the first mode can be extended. .

  In the above configuration, the data storage device includes a data line to which the data storage element is connected, and a global data line to which the plurality of data lines are connected, and the refresh control circuit includes the data line via the global data line. By supplying either the first voltage condition or the second voltage condition to the data line, the data storage element that stores data in the first mode connected to the data line can be refreshed. . According to this configuration, by providing one refresh control circuit, it is possible to perform refresh for a plurality of data storage elements.

  In the above configuration, a data line to which the data storage element is connected, a sense amplifier to which the data line is connected, and a global data line to which a plurality of the data lines are connected via the sense amplifier. The refresh control circuit may be connected between the sense amplifier and the global data line and perform the determination and the refresh for each of the plurality of data lines. According to this configuration, refresh can be performed simultaneously on a plurality of data storage elements in parallel. In addition, the refresh operation can be speeded up.

  In the above configuration, the refresh control circuit measures the number of refreshes performed on the data storage element that stores data in the first mode, and sets the first voltage condition and the second voltage condition according to the number of times. It is possible to change the data storage element that stores data in the first mode to perform a refresh. According to this configuration, the data storage element that stores data in the first mode can be refreshed under the optimum rewrite voltage condition corresponding to the state of the data storage element.

  In the above configuration, in addition to the first mode, the data storage element includes a high resistance state having a resistance value greater than a resistance value of the variable resistance in the high resistance state of the first mode and a low resistance state of the first mode. And a second mode for storing data by changing to any one of a low resistance state having a resistance value smaller than the resistance value of the variable resistor in the memory, wherein the refresh control circuit stores data in the second mode. The memory element can be configured not to be refreshed. According to this configuration, the refresh performed on the data storage element can be controlled in accordance with the storage mode of the data storage element.

  In the above configuration, the data storage element has a third mode in which data is stored according to the amount of electric charge stored in the electrode, and the refresh control circuit is provided for the data storage element that stores data in the third mode. Further, it is possible to adopt a configuration in which refresh is performed according to a third voltage condition for charging the electrode without performing the determination. According to this configuration, the refresh performed on the data storage element can be controlled in accordance with the storage mode of the data storage element.

  In the above configuration, the refresh control circuit stores data in the third mode without changing the third voltage condition depending on the number of refreshes for a data storage element that stores data in the third mode. The data storage element to be refreshed can be configured to be refreshed.

  In the above configuration, the refresh control circuit measures the number of refreshes performed on the data storage element that stores data in the first mode, and sets the first voltage condition and the second voltage condition according to the number of times. It is possible to change the data storage element that stores data in the first mode to perform a refresh. According to this configuration, the data storage element that stores data in the first mode can be refreshed under the optimum rewrite voltage condition corresponding to the state of the data storage element.

  In the above configuration, the refresh control circuit is a data storage element that stores data in the first mode by repeatedly rewriting the data storage element that stores data in the first mode a plurality of times. It can be configured to perform refresh. According to this configuration, stress applied to the variable resistance of the data storage element can be reduced.

  The present invention refreshes a data storage element having a first mode for storing data by changing a variable resistance to either a low resistance state or a high resistance state, and a data storage element for storing data in the first mode. A method for controlling a semiconductor device having a refresh control circuit, comprising: determining whether a data storage element that stores data in the first mode is in the low resistance state or the high resistance state; Either a first voltage condition for causing the data storage element that stores data in the first mode to be in a low resistance state or a second voltage condition for causing the data storage element that stores data in the first mode to be in a high resistance state And a step of refreshing a data storage element that stores data in the first mode. It is a control method. According to the present invention, the data storage element that stores data in the first mode can be refreshed, and the data retention time of the data storage element that stores data in the first mode can be extended. .

  According to the present invention, it is possible to perform refresh for a data storage element that stores data by changing the variable resistance to either the low resistance state or the high resistance state, and the data storage time of the data storage element can be reduced. Can be long.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram illustrating the configuration of the semiconductor device 100 according to the first embodiment. In FIG. 1, a memory cell array 10 has a plurality of memory cells MC including data storage elements (not shown). The memory cell array 10 is provided with a plurality of data lines DL and a plurality of word lines WL. The memory cell MC is provided in the intersection region between the data line DL and the word line WL, and is connected to the data line DL and the word line WL. Of the plurality of data lines DL, the first data line DLz and the second data line DLx, which are adjacent data lines DL, constitute a data line pair. Among the plurality of memory cells, the first memory cell MCz is connected to the first data line DLz, and the second memory cell MCx is connected to the second data line DLx. The first memory cells MCz and the second memory cells MCx are alternately provided every other word line WL.

  A row decoder 12 for selecting a row is connected to the word line WL, and a column decoder 14 for selecting a column is connected to the data line DL. A memory cell MC to be accessed is selected by a combination of a row selected by the row decoder 12 and a column selected by the column decoder 14. An address signal for selecting the memory cell MC is sent from the outside to the row decoder 12 and the column decoder 14 via the address buffer 16.

  The writing circuit 18 generates a high voltage for data writing applied to the memory cell MC when data is written. The reset circuit 20 supplies a reference voltage Vref applied to the data line DL when reading data. The clamp circuit 21 supplies a clamp voltage Vclmp applied to the data line DL when reading data. The sense amplifier 22 reads and amplifies a signal from the memory cell MC. The sense amplifier driver 24 drives the sense amplifier 22 when reading data. The input / output circuit 26 exchanges data between the memory cell array 10 and the outside.

  The selection register 28 stores information related to a storage mode when data is stored in the memory cell MC. The control unit 30 selects the storage mode of the memory cell MC based on the information regarding the storage mode stored in the selection register 28. In addition, the control unit 30 controls the write circuit 18, the reset circuit 20, the clamp circuit 21, and the input / output circuit 26 in accordance with an external command signal. Further, the control unit 30 controls the column decoder 14 to apply a voltage when writing and reading data from the data line pair including the first data line DLz and the second data line DLx. One data line DL is selected. The refresh control circuit 32 controls refresh for the data storage element 40 of the memory cell MC.

  2A to 2D are circuit diagrams showing the configuration of the memory cell MC in FIG. 2A and 2B, the memory cell MC includes a data storage element 40 and a selection transistor 41. A memory cell MC having a structure having the selection transistor 41 is referred to as a 1T1R type. The selection transistor 41 controls access to the data storage element 40. The selection transistor 41 has a gate connected to the word line WL, a drain connected to the data line DL, and a source connected to the data storage element 40. The data storage element 40 functions as either a capacitor or a variable resistor depending on the storage mode. One end of the data storage element 40 is connected to a source line (ground potential) (not shown) or an arbitrary voltage level (potential).

  2C and 2D, the memory cell MC includes a data storage element 40 and a selection diode 42. The memory cell MC having the structure having the selection diode 42 is referred to as a 1D1R type. The anode side of the data storage element 40 is connected to the word line WL, and the cathode side is connected to the data line DL. As shown in FIGS. 2A and 2B, since the selection transistor 41 is not provided, the potential of the data line DL is maintained higher than the potential of the word line WL when the data storage element 40 is not selected. As a result, it is possible to prevent a current from flowing through the data storage element 40 by the action of the selection diode 42. Conversely, the data storage element 40 can be selected by making the potential of the data line DL lower than the potential of the word line WL.

FIG. 3 is a cross-sectional view showing the configuration of the data storage element 40 in FIGS. 2 (a) to 2 (d). In FIG. 3, the data storage element 40 includes a variable resistor 43 and an electrode 44. Variable resistor 43, the magnitude of the resistance value used for storing data, comprising a material change in resistance value is large (e.g., 10 ^four times or more) when a current flows. Specific examples of the material include transition metal oxides including CuO. The electrode 44 stores data by storing electric charge as a capacitor, and is made of a highly conductive material such as Cu. The electrodes 44 are provided at both ends of the variable resistor 43. The variable resistor 43 is covered with an insulating portion 46.

Next, the storage mode when data is stored in the memory cell MC will be described using Table 1. In Table 1, there are three storage modes (NVM mode, MID mode, and RAM mode) for storing data in the memory cell MC. In the NVM mode and the MID mode, data is stored by changing the variable resistor 43 to either the high resistance state or the low resistance state. Here, the MID mode is the first mode, and the NVM mode is the second mode. In the NVM mode, the high resistance state is, for example, about 10 ⁸ Ω, and logic “0” is stored at this time. The low resistance state is, for example, about 10 ² Ω, and logic “1” is stored at this time. In the MID mode, the high resistance state is, for example, about 10 ⁷ Ω, and logic “0” is stored at this time. The low resistance state is, for example, about 10 ³ Ω, and logic “1” is stored at this time. Thus, the resistance value of the variable resistor 43 in the high resistance state of the NVM mode that is the second mode is larger than the resistance value of the variable resistor 43 in the high resistance state of the MID mode that is the first mode. The resistance value of the variable resistor 43 in the low resistance state of the NVM mode is smaller than the resistance value of the variable resistor 43 in the low resistance state of the MID mode. That is, the difference in resistance value between the high resistance state and the low resistance state of the variable resistor 43 is smaller in the MID mode than in the NVM mode.

In the RAM mode, which is the third mode, data is stored by the amount of charge stored in the electrode 44 that is a capacitor. When no charge is stored in the capacitor (when discharging), a logic “0” is stored, and when a charge is stored (when charging), a logic “1” is stored. As described above, as shown in FIGS. 2A and 2C, in the NVM mode and the MID mode, the data storage element 40 functions as a variable resistor, and FIGS. 2B and 2D. As described above, in the RAM mode, the data storage element 40 functions as a capacitor.

  Table 2 shows the characteristics of the data storage element 40 in each storage mode. The numbers in parentheses in Table 2 are examples. In Table 2, the NVM mode has a long data retention time (for example, 10 years) while the access speed is slow (for example, 300 ns). This shows a property close to that of a conventional nonvolatile memory element (flash memory or the like). In the MID mode, the data retention time is shorter than that of the NVM mode (for example, one day), and the access speed is higher than that of the NVM mode (for example, 70 ns). In the MID mode, in order to extend the data holding time, it is necessary to perform refreshing at regular intervals. In the RAM mode, the access speed is fast (for example, 50 ns), but the data retention time is short (for example, 1 second). This shows a property close to that of a conventional volatile memory element (DRAM or the like). In order to increase the data retention time, it is necessary to perform refresh. As described above, the MID mode has an intermediate property between the NVM mode and the RAM mode.

In addition, since data writing to the NVM mode and the MID mode is accompanied by a change in the state of the variable resistor 43 and damages the data storage element 40, the number of data rewrites is limited (for example, NVM mode is 10,000 times, MID mode Is 100,000 times). On the other hand, in the RAM mode, only charge is taken in and out of the electrode 44 and damage to the data storage element 40 is small, so that rewriting can be performed virtually infinitely.

The data storage element 40 can function data in three storage modes different from the NVM mode, the MID mode, and the RAM mode by controlling the magnitude of the flowing current and the time of the applied voltage. Here, data writing and reading operations in the case of the 1T1R type memory cell MC will be described. Table 3 is a table showing an example of the gate voltage Vg, the drain voltage Vd, and the voltage application time S of the selection transistor 41 corresponding to the data write and read operations in each storage mode of the 1T1R type memory cell MC. The voltage application time S can be controlled by changing the voltage condition applied to the data storage element 40, for example. The voltage condition refers to the magnitude of voltage applied to the memory cell MC and the application time.

  First, voltage conditions for data writing and reading in the NVM mode will be described. FIG. 4 is a graph showing voltage-current characteristics of the data storage element 40. In FIG. 4, (a) indicated by a solid line arrow shows a change in voltage-current characteristics when the variable resistor 43 in the data storage element 40 shifts from the low resistance state to the high resistance state. (B) indicated by an arrow shows a change in voltage-current characteristics when the variable resistor 43 shifts from the high resistance state to the low resistance state.

  The data storage element 40 has a threshold voltage Vth for changing the variable resistor 43 from the high resistance state to the low resistance state. When writing logic “0”, a voltage lower than the threshold voltage Vth is applied for a predetermined time. As a result, almost no current flows through the data storage element 40 after a predetermined time has elapsed, and the variable resistor 43 shifts from the low resistance state to the high resistance state. (See FIG. 4A). At this time, the gate voltage Vg is 2.5 V, the drain voltage Vd is 1.2 V, and the applied voltage time S is 250 ns (see Table 3). When writing logic “1”, a voltage higher than the threshold voltage Vth is applied. As a result, a current flows through the data storage element 40, and the variable resistor 43 changes from the high resistance state to the low resistance state (see FIG. 4B). At this time, the gate voltage Vg is 1.2 V, the drain voltage Vd is 4 V, and the applied voltage time S is 100 ns (see Table 3). In this way, data can be written in the NVM mode.

  In the NVM mode, when data is read, a voltage lower than the threshold voltage Vth and lower than the voltage for setting the variable resistor 43 to the high resistance state is applied to the data storage element 40. Thereby, when the variable resistor 43 is in the low resistance state, current flows, and when the variable resistance 43 is in the high resistance state, current does not flow, so that logic “0” and “1” can be determined. At this time, the gate voltage Vg is 1.0 V, and the drain voltage Vd is Vclmp.

  Next, voltage conditions for data writing and reading in the MID mode will be described. In Table 3, the magnitude of the gate voltage Vg and the drain voltage Vd of the selection transistor 41 when writing data in the MID mode is the same as in the NVM mode, and only the voltage application time S is different. The voltage application time S at the time of data writing in the MID mode is 50 ns. In the MID mode, the voltage condition for reading data is the same as in the NVM mode.

  Next, voltage conditions for data writing and reading in the RAM mode will be described. In Table 3, the gate voltage Vg of the selection transistor 41 when data is written in the RAM mode is always 2.5V. This is the same magnitude as the gate voltage when the variable resistor 43 is set to the high resistance state in the NVM mode and the MID mode. That is, in the RAM mode, the variable resistor 43 is maintained in a high resistance state. When writing logic “0” in the RAM mode, a low voltage (eg, ground potential Vss) is applied to the data storage element 40 to discharge the charge stored in the electrode 44. At this time, the drain voltage Vd is 0 V, and the applied voltage time S is 10 ns. When writing logic “1”, a high voltage is applied to the data storage element 40 to accumulate and charge the electrode 44. At this time, the drain voltage Vd is 1.2 V, and the voltage application time S is 10 ns. In the RAM mode, charges are only taken in and out of the electrode 44, and the state of the variable resistor 43 does not change. For this reason, the voltage application time S in the NVM mode and the MID mode is longer than the voltage application time S in the RAM mode. The voltage applied to the electrode 44 is smaller than the threshold voltage of the data storage element 40.

  In the RAM mode, when reading data, a reference voltage Vref for reading data is applied to the data storage element 40. At this time, the gate voltage Vg is 2.5 V, and the drain voltage Vd is Vref.

  Next, a specific circuit configuration and operation regarding data writing to the 1T1R type memory cell MC will be described. FIG. 5 is a circuit diagram showing a configuration of row decoder 12 in FIG. In FIG. 5, the hatched transistors 53 to 55 are pMOS transistors, and select voltages Vx1 to Vx3 applied to their source terminals according to inputs Axx to Cxx to their gate terminals. The drain terminals of the pMOS transistors 53 to 55 are connected to the gate terminal of the selection transistor 41 via the word line WL. Therefore, one voltage selected from the voltages Vx1 to Vx3 is applied as the gate voltage Vg of the selection transistor 41. Vx1 is 2.5V, Vx2 is 1.2V, and Vx3 is 1.0V. Therefore, according to Table 3, Vx1 is selected for writing logic “0” in the NVM mode and MID mode, and writing and reading in the RAM mode. Vx2 is selected for writing logic “1” in the NVM mode and the MID mode. Vx3 is selected for reading data in the NVM mode and the MID mode.

  The NAND gate 50 receives an address signal A # x / z for selecting a word line and a timing signal Timxpz for controlling the rise and fall of the gate voltage Vg of the selection transistor 41. When the address signal A # x / z is at the H (high) level, one of the voltages Vx1 to Vx3 is applied to the word line WL via the inverter 52 in accordance with the timing signal Timxpz.

  FIG. 6 is a circuit diagram showing a configuration of the column decoder 14 in FIG. In FIG. 6, an address signal A # x / z for selecting a data line and a timing signal Timepz for controlling the rise and fall of the drain voltage Vd of the selection transistor 41 are input to the NAND gate 56. Inverter 58 inverts the output of NAND gate 56. When the address signal A # x / z is at the H level, the control signal Timepzb is output to the write circuit 18 in accordance with the timing signal Timepz. Here, the column decoder 14 selects a data line pair including a data line to which the memory cell MC to be accessed is connected and a data line corresponding to the data line. Of the two data lines constituting the data line pair, the data line to which the drain voltage Vd is applied is selected by the data line selection unit 62 (see FIG. 8) described later.

  FIG. 7 is a circuit diagram showing a configuration of the write circuit 18 in FIG. In FIG. 7, the write circuit 18 includes a voltage selection unit 60 and a data line selection unit 62. In the pMOS transistors 66 to 68 in the voltage selection unit 60, Vy1, Vy2, and Vclmp are applied to the source terminals, respectively. The drain terminals of the pMOS transistors 66 to 68 are connected to the drain terminal of the selection transistor 41 via the data line selection unit 62 and the data line DL. As a result, a voltage selected from the voltages Vy1, Vy2, and Vclmp is applied as the drain voltage Vd of the selection transistor 41. Vy1 is 4V, Vy2 is 1.2V, and Vclmp is 0.8V. Therefore, according to Table 3, Vy1 is selected in writing logical “1” in the NVM mode and the MID mode. Vy2 is selected in writing of logic “0” in the NVM mode and MID mode and writing of logic “1” in the RAM mode. Vclmp is selected for reading data in the NVM mode and the MID mode.

  The NAND gate 64 receives the signal RAMz inverted by the inverter 63 and receives the signal DATAz corresponding to the logical value stored in the data storage element 40. That is, in the RAM mode, the signal RAMz is at the H level, and the output of the NAND gate 64 is always at the H level. The output of the NAND gate 64 is inverted by the inverter 65 and input to the gate terminal of the transistor 67. Thereby, the transistor 67 is turned on and the voltage Vy2 is selected. In the NVM mode and the MID mode, RAMz is at L level, and a voltage is selected according to the signal DATAz. That is, in the writing of logic “0” in the NVM mode and the MID mode, the signal DATAz becomes L level and the output of the NAND gate 64 becomes H level. As a result, the transistor 67 is turned on as in the RAM mode, and the voltage Vy2 is selected. In the logic “1” write in the NVM mode and the MID mode, the signal DATAz becomes H level, and the output of the NAND gate 64 becomes L level. Thereby, the transistor 66 is turned on and the voltage Vy1 is selected.

  The semiconductor device 100 according to the first embodiment includes a data line pair including a first data line DLz and a second data line DLx, and memory cells MC are alternately arranged on each data line DL. For this reason, the selection method of the data line to which the drain voltage Vd is applied differs between the NVM mode, the MID mode, and the RAM mode. This will be described below.

  FIG. 8 is a circuit diagram showing a configuration of the data line selection unit 62 in FIG. 7 and a part of the memory cell array 10 in FIG. FIG. 8A corresponds to the NVM mode and the MID mode, and FIG. 8B corresponds to the RAM mode. 8A and 8B, the data line selection unit 62 includes inverters 70 to 72, a NAND gate 73, and pass gates 74 and 75. The drain voltage Vd selected by the voltage selection unit 60 is applied to the inverters 70 and 71. The first data line DLz is connected to the pass gate 74, and the second data line DLx is connected to the pass gate 75, respectively. A first memory cell MCz having a first data storage element is connected to the first data line DLz, and a second memory cell MCx having a second data storage element is connected to the second data line DLx.

  In FIG. 8A, in the NVM mode and the MID mode, the signal NVMz input to the NAND gate 73 becomes H level, and the pass gates 74 and 75 are turned ON or OFF according to the timing signal Timepzb input from the column decoder 14. Switch to OFF. The signal Ya0z input to the inverter 70 is an address signal for selecting a data line to which a memory cell to which data is to be written is connected, among the data line pair composed of the first data line DLz and the second data line DLx. It is.

  In FIG. 8B, in the RAM mode, the signal RAMz input to the NAND gate 73 becomes H level, and the pass gates 74 and 75 are switched ON or OFF according to the timing signal Timepzb input from the column decoder 14. . The signal DATAz input to the inverter 70 is a logical value of data written in the memory cell MC. In the following, it is assumed that the logic H (high) corresponds to the logic “1” in Table 1, and the logic L (low) corresponds to the logic “0” in Table 1.

  Next, data writing to the first memory cell MCz and the second memory cell MCx in FIG. 1 will be described with reference to FIG. In FIG. 9, the control unit 30 selects a storage mode for storing data in the memory cell MC (step S10). In the case of the NVM mode and the MID mode, the process proceeds to step S11, and in the case of the RAM mode, the process proceeds to step S15.

  In the NVM mode and the MID mode, it is determined whether the memory cell MC having the data storage element 40 to be written is the first memory cell MCz or the second memory cell MCx (step S11). When writing to the first data storage element in the first memory cell MCz, the control unit 30 selects the first data line DLz. At this time, the signal Ya0z in FIG. 8A becomes the H level, the first data line DLz is set to the H level, and the second data line DLx is set to a voltage level lower than the H level (for example, half of the power supply voltage Vcc). (Step S12). When writing to the second data storage element in the second memory cell MCx, the control unit 30 selects the second data line DLx. At this time, the signal Ya0z in FIG. 8A becomes L level, the second data line DLx is set to H level, and the first data line DLz is set to voltage level lower than H level (step S13).

  Next, the control unit 30 controls the write circuit 18 to apply a write voltage to the data line set to H level in step S12 and step S13, thereby writing data (step S14). In FIG. 8A, the write voltage applied to the first data line DLz and the second data line DLx is the drain voltage Vd selected by the voltage selection unit 60 (see FIG. 7), and the data storage element 40 This is for changing the variable resistor 43 in either the high resistance state or the low resistance state.

  Returning to FIG. 9, when it is determined in step S10 that the RAM mode is selected, the data line to which the write voltage is to be applied is selected according to the logical value stored in the data storage element 40 in the memory cell MC. First, the control unit 30 determines the logical value of data written to the memory cell MC (step S15). When writing logic “1” (logic H), the control unit 30 selects the first data line DLz. At this time, the signal DATAz in FIG. 8B becomes H level, the first data line DLz is set to H level, and the second data line DLx is set to L level (step S16). When writing logic “0” (logic L), the control unit 30 selects the second data line DLx. At this time, the signal DATAz in FIG. 8B becomes L level, the first data line DLz is set to L level, and the second data line DLx is set to H level (step S17).

  Next, a voltage for charging the electrode 44 in the data storage element 40 with respect to the data line set to H level in Step S16 and Step S17 by the control unit 30 controlling the writing circuit 18. Is applied to write data (step S18). In FIG. 8B, the write voltage applied to the data line set to the H level is the drain voltage Vd selected by the voltage selection unit 60 (see FIG. 7). At the same time, the control unit 30 applies a voltage (for example, ground potential Vss) for discharging charges from the electrode 44 in the data storage element 40 to the data line set to the L level. Thus, the writing of data to the data storage element 40 is completed.

  In the RAM mode, the drain voltage depends on the logical value stored in the memory cell MC regardless of whether the memory cell MC to be written is connected to the first data line DLz or the second data line DLx. A data line to which Vd is to be applied is selected. For this reason, a logical value (hereinafter, external logic) stored in the memory cell MC and a logical value (hereinafter, internal logic) indicating the state of the data storage element 40 in the memory cell MC do not necessarily match. This will be described below.

  For example, when logic “1” is stored in the first memory cell MCz (external logic is 1), the signal DATAz in FIG. 8B becomes H level, and the first data line DLz is set to H level. For this reason, the first memory cell MCz is charged (the internal logic is 1). When logic “0” is stored in the first memory cell MCz (external logic is 0), the signal DATAz in FIG. 8B becomes L level, and the first data line DLz is set at L level. One memory cell MCz is discharged (internal logic is 0). Thus, in the first memory cell MCz, the external logic and the internal logic are the same.

  On the other hand, when logic “1” is stored in the second memory cell MCx (external logic is 1), the signal DATAz in FIG. 8B becomes H level, and the first data line DLz is set to H level. At this time, since the second data line DLx is set to the L level, the second memory cell MCx connected to the second data line DLx is discharged (internal logic is 0). When logic “0” is stored in the second memory cell MCx (external logic is 0), the signal DATAz in FIG. 8B becomes L level, and the first data line DLz is set to L level. At this time, since the second data line DLx is set to the H level, the second memory cell MCx connected to the second data line DLx is charged (internal logic is 1). Thus, in the second memory cell MCx, the external logic and the internal logic are opposite. However, as will be described later, when data is read from the second memory cell MCx, data is read with the logical value reversed, so that data can be read correctly from each memory cell MC.

  In the NVM mode and the MID mode, data is stored based on the resistance value of the variable resistor 43. Therefore, a common circuit (FIGS. 6 to 8) can be used for writing data. The control unit 30 controls the voltage application time to the memory cell by controlling the timing signals Timxpz and Timepz that control the gate voltage Vg and the drain voltage Vd of the selection transistor 41, and the NVM mode, the MID mode, and the RAM mode Can be switched.

  Next, a specific circuit configuration and operation regarding data writing to the 1D1R type memory cell MC will be described. Since the 1D1R type memory cell MC does not have the selection transistor 41 for selecting the cell as described above, the voltage condition is set in order to change the resistance value of the variable resistor 43 of the data storage element 40. It is necessary to send the generated pulse to the data storage element 40 through the global data line GDL and the data line DL. Here, Table 4 shows an example of a voltage condition applied to the memory cell MC.

  In Table 4, in the NVM mode, a pulse having a small amplitude (for example, 1.2 V) is applied for a long time (for example, 250 ns) in order to set the variable resistance 43 of the data storage element 40 to a high resistance state. Further, in order to put the variable resistor 43 of the data storage element 40 in a low resistance state, a pulse with a large amplitude (for example, 4.0 V) is applied for a short time (for example, 100 ns).

Next, in the MID mode, as shown in Table 4, the magnitude of the voltage to be applied is the same as in the NVM mode, only the voltage application time S is different, and half the time of the NVM mode is applied. In the RAM mode, a pulse with a small amplitude (for example, 0 V) is applied for a short time (for example, 10 ns) in order to put the electrode 44 of the data storage element 40 into a discharged state. Further, in order to put the electrode 44 in a charged state, a pulse with a large amplitude (for example, 1.2 V) is applied for a short time (for example, 10 ns).

  FIG. 10A to FIG. 10D are circuit diagrams showing the configuration of the peripheral circuit in FIG. Data writing in the NVM mode and the MID mode will be described with reference to FIGS. In FIG. 10A, the input / output circuit 26 outputs a data signal Dataz that is data to be written in the memory cell MC in accordance with an externally input signal I / Oz.

  10B, a word line driving circuit WDr (not shown in FIG. 1) as a selection circuit includes a write signal WRz and an address signal Add. Accordingly, a selection signal for selecting the memory cell MC is supplied to the word line WL. Write signal WRz and address signal Add. Is input to the NAND gate 134, and only when both inputs are "H", the selection signal having the potential Vdd1 is output to the word line WL via the inverter 136. Vdd1 is, for example, 4.0V.

  When the memory cell MC is not selected, the word line WL side is set to a low potential and the data line DL side is set to a high potential. Due to the selection signal supplied from the word line driving circuit WDr, the potential of the word line WL rises and becomes equal to the potential of the data line DL. At this stage, no current flows through the memory cell MC.

  In FIG. 10C, the write control circuit 130 (not shown in FIG. 1) outputs the first pulse generation signal WRHz and the second pulse generation signal WRLz according to the write signal WRz and the timing signal Timepz. The write control circuit 130 includes two NAND gates 138 and 140 and a delay circuit 142 connected to each NAND gate. The number of inverters of the delay circuit 142 connected to the NAND gate 138 is larger than the number of inverters connected to the NAND gate 140. Therefore, the pulse width of the first pulse generation signal WRHz is shorter than the pulse width of the second pulse generation signal WRLz.

  10D, the data line driving circuit DDr (not shown in FIG. 1) receives the first pulse from the first pulse generation signal WRHz in accordance with the data signal Dataz supplied from the input / output circuit 26. Second pulses are respectively generated from the pulse generation signal WRLz. The data line driving circuit DDr supplies a write pulse, which is one of the generated first pulse and second pulse, to the data line DL.

  As shown in FIG. 10D, the data signal Dataz controls ON / OFF of the pass gates 150 and 152 and the N-type transistors 154 and 156 via the inverters 146 and 148. The first pulse generation signal WRHz is input to the gates of the P-type transistor 160 and the N-type transistor 162. The second pulse generation signal WRLz is input to the gates of the P-type transistor 158 and the N-type transistor 164. When data is not written, since the first pulse generation signal WRHz and the second pulse generation signal WRLz are both “L”, the P-type transistors 158 and 160 are turned on, and the N-type transistors 162 and 164 are turned off. Set to As a result, the voltage Vdd1 is output via the P-type transistors 158 and 160, and the potential of the data line DL is maintained at Vdd1.

  When the data signal Dataz is “H”, the pass gate 152 is turned on and the first pulse generation signal WRHz is input to the circuit. Further, the N-type transistor 154 is set to ON and the N-type transistor 156 is set to OFF. Since the N-type transistor 156 is set to OFF, “H” of the first pulse generation signal WRHz is input to the gate of the P-type transistor 160 and set to OFF. Similarly, “H” is input to the gate of the N-type transistor 162, which is set to ON. As a result, the voltage Vss is output to the data line DL. Vss is a ground potential, for example.

  When the potential of the word line WL is set to Vdd1 by the selection signal, the potential difference between the two becomes Vdd1 by setting the potential of the data line DL to Vss as described above. Flowing. By maintaining this state for the application time in the case of the low resistance “1” in Table 4, the variable resistance 43 of the memory cell MC becomes the low resistance state, and the logic “1” is written. As described above, the data line driving circuit DDr causes the first pulse to change the variable resistor 43 to the low resistance state according to the first pulse generation signal WRHz while the selection signal is applied to the memory cell MC. Is supplied to the data line DL.

  When the data signal Dataz is “L”, the pass gate 150 is turned on and the second pulse generation signal WRLz is input to the circuit. Further, the N-type transistor 154 is set to OFF and the N-type transistor 156 is set to ON. Since the N-type transistor 154 is set to OFF, “H” of the second pulse generation signal WRLz is input to the gate of the P-type transistor 158 and set to OFF. Similarly, “H” is input to the gate of the N-type transistor 164, which is set to ON. As a result, voltages Vdd1-Vdd0 are output to the data line DL. Vdd0 is, for example, 1.2V.

  When the potential of the word line WL is set to Vdd1 by the selection signal, the potential difference between the two becomes Vdd0 by setting the potential of the data line DL to Vdd1-Vdd0 as described above. Current flows. By maintaining this state for the application time in the case of the high resistance “0” in Table 4, the variable resistance 43 of the memory cell MC becomes the high resistance state, and logic “0” is written. As described above, the data line driving circuit DDr causes the second pulse to change the variable resistor 43 to the high resistance state according to the second pulse generation signal WRLz while the selection signal is applied to the memory cell MC. Is supplied to the data line DL.

  FIG. 11 is a flowchart showing an operation at the time of data writing. Referring to FIGS. 10 and 11, at the start of data writing, the potential of word line WL is set to Vss, and the potential of data line DL is set to Vdd1. A reverse bias is applied to the memory cell MC, and no current flows. First, the control unit 30 selects a storage mode for data storage performed in the memory cell MC (step S20). If it is the NVM mode or the MID mode, the process proceeds to step S22. In the case of the RAM mode, the process proceeds to step S26.

  In the NVM mode and the MID mode, the word line driving circuit WDr, which is a selection circuit, supplies a selection signal to the word line WL (step S22). As a result, the potential of the word line WL rises to Vdd1. Next, when data of logic “1” is written, the data line driving circuit DDr supplies the first pulse with the voltage condition set to the data line DL (step S24). As a result, the potential of the data line becomes Vss, a current flows through the memory cell MC, and the variable resistor 43 in the data storage element 40 is in a low resistance state. When writing data of logic “0”, the data line driving circuit DDr, which is a writing circuit, supplies the second pulse with the voltage condition set to the data line DL (step S22). As a result, the potential of the data line DL becomes Vdd1-Vdd0, a current flows through the memory cell MC, and the variable resistor 43 in the data storage element 40 enters a high resistance state. Through the above steps, data writing to the memory cell MC in the NVM mode and the MID mode is completed.

  Even in the RAM mode, the word line driving circuit WDr, which is a selection circuit, supplies a selection signal to the word line WL (step S26). Next, when writing data of logic “1”, the data line driving circuit DDr, which is a writing circuit, supplies a third pulse with a voltage condition set to the data line DL (step S28). As a result, a current flows through the memory cell MC, and charges can be stored in the electrode 44 of the data storage element 40. At this time, as shown in Table 4, since the voltage application time in the RAM mode is short, the variable resistor 43 maintains a high resistance state. When data of logic “0” is written, the data drive circuit DDr applies (supplies) a breakdown voltage (breakdown voltage) to the data line DL (step S28). Thereby, the electric charge stored in the electrode 44 of the data storage element 40 can be extracted (discharged), and data of logic “0” can be written. Through the above steps, data writing to the memory cell MC in the RAM mode is completed.

  Next, a specific circuit configuration and operation regarding reading of data from the memory cell MC will be described. FIG. 12 is a circuit diagram showing the configuration of the memory cell array 10, the reset circuit 20, and the sense amplifier 22 as a detection circuit in FIG. In FIG. 12, the first memory cell MCz is connected to the first data line DLz, and the second memory cell MCx is connected to the second data line DLx. Therefore, data stored in the first memory cell MCz is read from the first data line DLz, and data stored in the second memory cell MCx is read from the second data line DLx.

  The reset circuit 20 is provided between the first data line DLz and the second data line DLx. That is, the reset circuit 20 is provided for the data line pair. The reset circuit 20 includes transistors 84, 86, and 88. The transistor 84 short-circuits the first data line DLz and the second data line DLx according to the reset signal BRSz. The transistors 86 and 88 supply the reference voltage Vref to the first data line DLz and the second data line DLx in response to the reset signal BRSz.

  The sense amplifier 22 is provided corresponding to the reset circuit 20 between the first data line DLz and the second data line DLx, and is configured of an inverter pair including inverters 80 and 82. The inverters 80 and 82 are supplied with the power supply voltage Vcc and the ground voltage Vss from the sense amplifier driver 24. The sense amplifier 22 amplifies a potential difference between both data lines in accordance with a latch signal LEz (not shown). Here, the reference voltage Vref is preferably about half the power supply voltage Vcc. The power supply voltage Vcc is, for example, 1.2V, and the reference voltage Vref is, for example, 0.6V.

  FIG. 13 is a circuit diagram showing a configuration of the clamp circuit 21 in FIG. In FIG. 13, the clamp circuit 21 includes NAND gates 90 and 91, inverters 92 and 93, and pMOS transistors 94 and 95. The source terminals of the pMOS transistors 94 and 95 are connected to the output terminal Vd of the voltage selection unit 60 in FIG. In FIG. 7, when the data stored in the NVM mode and the MID mode is read from the memory cell MC, the clamp voltage Vclmp is supplied to the output terminal Vd. The clamp voltage Vclmp is set to be higher than the reference voltage Vref. Vclmp is, for example, 0.8V.

  The clamp signal clmpz input to the NAND gates 90 and 91 is a signal for operating the clamp circuit 21. When reading data stored in the NVM mode and the MID mode, the clamp signal clmpz is set to the H level. The address signal Ya0z input to the inverter 92 is a signal for selecting a data line to which the clamp voltage Vclmp is to be applied. When the clamp signal clmpz is at the H level, the data line to which the clamp voltage Vclmp is applied is selected according to the address signal Ya0z. That is, when data is read from the first memory cell MCz storing data in the NVM mode and the MID mode, the signal Ya0z becomes H level and the pMOS transistor 94 is turned on. As a result, the clamp voltage Vclmp is applied to the first data line DLz. When data is read from the second memory cell MCx storing data in the NVM mode and the MID mode, the signal Ya0z is at L level and the pMOS transistor 95 is turned on. As a result, the clamp voltage Vclmp is applied to the second data line DLx.

  FIG. 14 is a circuit diagram showing a configuration of sense amplifier driver 24 in FIG. In FIG. 14, the sense amplifier driver 24 includes an inverter 96, a pMOS transistor 97, and an nMOS transistor 98. A power supply voltage Vcc is applied to the source terminal of the pMOS transistor 97, and a ground voltage Vss is applied to the source terminal of the nMOS transistor 98. The drain terminal PSA of the pMOS transistor 97 is connected to the P channel side of the sense amplifier 22, and the drain terminal NSA of the nMOS transistor 98 is connected to the N channel side of the sense amplifier 22. The inverter 96 inverts and inputs the latch signal LEz to the gate terminal of the pMOS transistor 97. When the latch signal LEz is set to the H level, the pMOS transistor 97 and the nMOS transistor 98 are turned on. Therefore, the power supply voltage Vcc is supplied to the drain terminal PSA of the pMOS transistor 97, and the ground voltage Vss is supplied to the drain terminal NSA of the nMOS transistor 98.

  FIG. 15 is a flowchart showing control in reading data from the memory cell MC. In FIG. 15, first, the control unit 30 applies the reference voltage Vref to the first data line DLz and the second data line DLx to which the first memory cell MCz or the second memory cell MCx that is a data read target is connected, respectively. Apply (step S30). At this time, in FIG. 12, the reset signal BRSz is supplied to the reset circuit 20 and the transistor 84 is turned ON, whereby the first data line DLz and the second data line DLx are short-circuited. As will be described later, after the data reading is completed, the power supply voltage Vcc is applied to one of the first data line DLz and the second data line DLx, and the ground voltage Vss is applied to the other. For this reason, it is possible to control the voltage of the data line near the reference voltage Vref (= Vcc / 2) by short-circuiting them. Thereby, the power consumption of the circuit can be suppressed. Further, since the transistors 86 and 88 are turned on by the reset signal BRSz, the reference voltage Vref is supplied to the first data line DLz and the second data line DLx. Thereby, the first data line DLz and the second data line DLx are accurately set to the reference voltage Vref.

  Next, the control unit 30 determines the storage mode of the memory cell MC to be read (step S32). If the storage mode is either the NVM mode or the MID mode, the process proceeds to step S34. If the storage mode is the RAM mode, the process proceeds to step S50.

  When the storage mode is either the NVM mode or the MID mode, the control unit 30 specifies the memory cell MC that is a read target (step S34). When the memory cell MC to be read is the first memory cell MCz having the first data storage element, the control unit 30 selects the first data line DLz (step S36). When the memory cell MC to be read is the second memory cell MCx having the second data storage element, the control unit 30 selects the second data line DLx (step S38). Then, the clamp voltage Vclmp is applied to the selected data line (step S40). The clamp voltage Vclmp is supplied by the clamp circuit 21 shown in FIG. As a result, the voltage of the data line DL to which the memory cell MC to be read is connected rises to a clamp voltage Vclmp that is higher than the reference voltage Vref. On the other hand, the voltage of the data line DL to which the memory cell MC to be read is not connected is maintained at the reference voltage Vref.

  Next, the control unit 30 makes the data storage element 40 in the memory cell MC and the data line DL conductive (step S42).

  When the variable resistor 43 in the data storage element 40 is in a high resistance state, no current flows through the memory cell MC, so the voltage of the data line DL remains Vclmp. Therefore, the voltage of the data line DL (one of the first data line DLz and the second data line DLx) to which the memory cell MC to be read is connected is equal to the data line DL (first data line DL to which the memory cell to be read is not connected). The voltage is higher than the voltage of the other one of the first data line DLz and the second data line DLx.

  When the variable resistor 43 in the data storage element 40 is in a low resistance state, a current flows through the memory cell MC, so that the voltage of the data line DL connected to the memory cell MC to be read drops from Vclmp. Accordingly, the voltage of the data line DL to which the memory cell MC to be read is connected is lower than the voltage of the data line DL to which the memory cell MC to be read is not connected. In this manner, the control unit 30 reads data from the memory cell MC by comparing the voltages of the first data line DLz and the second data line DLx (step S44).

  Here, FIG. 16 shows a timing chart showing an operation at the time of data reading in the NVM mode and the MID mode. In FIG. 16, the data line voltage is maintained at Vref by the reset signal BRSz supplied from the control unit 30. At the time of data reading, the control unit 30 sets the reset signal BRSz to L level and stops supplying the reset voltage Vref (A). Next, the control unit 30 sets the clamp signal clmpz to the H level (B) and raises the data line voltage to Vclmp (C). Thereafter, the clamp signal clmpz is set to the L level again (D), and the supply of the clamp voltage Vclmp is stopped.

  Next, the control unit 30 increases the voltage of the word line WL (the gate voltage Vg of the selection transistor 41) (E), and makes the data storage element 40 and the data line DL conductive. When logic “0” is stored in the data storage element 40, the data line voltage does not change (F) because the variable resistor 43 is in a high resistance state. When the logic “1” is stored in the data storage element 40, the variable resistance 43 is in a low resistance state, so that the data line voltage decreases and falls below the reference voltage Vref (G). Next, when the control unit 30 sets the latch signal LEz to the H level (H), when the data line voltage is higher than Vref, it rises to the power supply voltage Vcc (I), and when the data line voltage is lower than Vref. The voltage drops to the ground voltage Vss (J). Thereby, the signal read from the data storage element 40 is amplified and taken out to the outside.

  Returning to FIG. 15, when the storage mode is the RAM mode, the control unit 30 makes the data storage element 40 in the memory cell MC and the data line DL conductive (step S50). In the RAM mode, the clamp voltage Vclmp is not supplied to the data line DL.

  When the data storage element 40 is in a charged state, the charge stored in the electrode 44 is released to the data line DL. As a result, the voltage of the data line DL (one of the first data line DLz and the second data line DLx) to which the memory cell MC to be read is connected rises, and the data line to which the memory cell to be read is not connected. It becomes higher than the voltage Vref of DL (the other of the first data line DLz and the second data line DLx).

  When the data storage element 40 is in a discharged state, the electrode 44 is charged, and the voltage of the data line DL to which the memory cell MC to be read is connected drops. Therefore, the voltage of the data line DL connected to the memory cell MC to be read is lower than the voltage Vref of the data line DL to which the memory cell MC to be read is not connected.

  The controller 30 compares the voltage of the first data line DLz and the voltage of the second data line DLx (step S52), and reads the logic “1” when the voltage of the first data line DLz is large (step S54). ) When the voltage of the second data line DLx is large, the logic “0” is read (step S56).

  Thus, in reading data from the memory cell MC stored in the RAM mode, the control unit 30 reads data based on the voltage level of the first data line DLz. That is, when the first data line DLz is at the H level, logic “1” is read, and when the first data line DLz is at the L level, logic “0” is read. As a result, when the memory cell MC to be read is the first memory cell MCz, the state (internal logic) of the first data storage element in the first memory cell MCz and the logical value of the read data (external logic) ) Is the same. On the other hand, when the memory cell MC to be read is the second memory cell MCx, the state (internal logic) of the second data storage element in the second memory cell MCx and the logical value (external logic) of the read data Is the opposite.

  For example, when the second data storage element is in a discharged state (internal logic is “0”), the first data line DLz is at H level and the second data line DLx is at L level when data is read. 1 "is read (external logic is" 1 "). When the second data storage element is in a charged state (internal logic is “1”), the first data line DLz is at L level and the second data line DLx is at H level when data is read. Is read (external logic is “0”). As described above, when data is stored in the second memory cell MCx in the RAM mode, the internal logic indicating the state of the second data storage element and the external logic indicating the data stored in the second memory cell MCx are: It was the opposite. For this reason, when data is read from the second memory cell MCx, the data can be read accurately by reversing the internal logic and the external logic.

  Here, FIG. 17 shows a timing chart showing an operation at the time of data reading in the RAM mode. In FIG. 17, first, the data line voltage is maintained at Vref by the reset signal BRSz supplied from the control unit 30. At the time of data reading, the control unit 30 sets the reset signal BRSz to L level (A) and stops supplying the reset voltage Vref. Next, the control unit 30 increases the voltage of the word line WL (the gate voltage Vg of the selection transistor) (B), and makes the data storage element and the data line conductive. When logic “0” is stored in the data storage element 40, the electrode 44 is in a discharged state, so the data line voltage decreases (C). When logic “1” is stored in the data storage element 40, the electrode 44 is in a charged state, and the data line voltage increases (D).

  Next, when the control unit 30 sets the latch signal LEz to the H level (E), when the data line voltage is higher than Vref, it rises to the power supply voltage Vcc (F), and when the data line voltage is lower than Vref. Then, the voltage drops to the ground voltage Vss (G). Thereby, the signal read from the data storage element 40 is amplified and taken out to the outside.

  Next, refresh performed on the data storage element 40 will be described. As shown in Table 2, the data storage element 40 that stores data in the MID mode and the RAM mode has a short data holding time, but the data holding time can be extended by performing refresh. FIG. 18 is a block diagram showing the configuration of the refresh control circuit 32 in FIG. In FIG. 18, the refresh control circuit 32 includes a refresh circuit 34 and a timer 36. The refresh circuit 34 is connected to the global data line GDL. The global data line GDL is connected to a plurality of data lines DL.

  The timer 36 is preset with a time corresponding to a refresh interval performed for the data storage element 40 that stores data in the MID mode. The timer 36 receives a signal Mode related to the storage mode of the data storage element 40 from the control unit 30. When the timer 36 determines that the signal Mode input from the control unit 30 is in the MID mode, the timer 36 starts the timer. The timer 36 outputs a signal timer to the refresh circuit 34 when the set time is reached after the timer is started.

  A signal Mode relating to the storage mode of the data storage element 40 is input from the control unit 30 to the refresh circuit 34. When the refresh circuit 34 determines that the signal Mode input from the control unit 30 is in the MID mode, the refresh circuit 34 waits until the signal timer is input from the timer 36. After the signal timer is input from the timer 36, the refresh circuit 34 refreshes the data storage element 40 that stores data in the MID mode. Further, when it is determined that the signal Mode input from the control unit 30 is in the RAM mode, the refresh circuit 34 immediately performs a refresh on the data storage element 40 that stores data in the RAM mode. Furthermore, when the refresh circuit 34 determines that the signal Mode input from the control unit 30 is in the NVM mode, the refresh circuit 34 does not perform refresh on the data storage element 40 that stores data in the NVM mode.

  FIG. 19 is a flowchart showing refresh control performed on the data storage element 40. In FIG. 19, the refresh control circuit 32 determines the storage mode of the data storage element 40 in the memory cell MC based on the signal Mode input from the control unit 30 (step S60). The signal Mode is input from the control unit 30 when data is written or refreshed to the memory cell MC. When the refresh control circuit 32 determines that the storage mode of the data storage element 40 is the MID mode based on the signal Mode input from the controller 30, the refresh control circuit 32 starts the built-in timer 36 (step S62). As described above, the timer 36 is set in advance with a time corresponding to a refresh interval performed for the data storage element 40 that stores data in the MID mode.

  After reaching the time set in the timer 36, the refresh control circuit 32 instructs the control unit 30 to read data from the memory cell MC (step S64). As a method for reading data at this time, the method for reading data from the memory cell MC described above can be used. Data read from the memory cell MC is input to the refresh control circuit 32 via the data line DL and the global data line GDL. The refresh control circuit 32 determines whether the data read from the memory cell MC is logic “1” or logic “0” (step S66).

  When the refresh control circuit 32 determines that the data read from the memory cell MC is logic “1” (the variable resistor 43 of the data storage element 40 is in the low resistance state), the refresh control circuit 32 sends the logic “1” to the control unit 30. The determination result to the effect is output.

  When the memory cell MC is a 1T1R type, the refresh control circuit 32 can change the data storage element 40 in accordance with the write signal WRz and the timing signal Timepz based on the determination result of logic “1” input from the control unit 30. A first voltage condition for setting the resistor 43 to a low resistance state is set. The memory cell MC to be refreshed is selected by the row decoder 12 and the column decoder 14, and the write circuit 18 performs a refresh that causes the variable resistor 43 to be in a low resistance state based on the first voltage condition set by the refresh control circuit 32. Is executed (step S68).

  When the memory cell MC is of the 1D1R type, the refresh control circuit 32 can change the data storage element 40 according to the write signal WRz and the timing signal Timepz based on the determination result of logic “1” input from the control unit 30. A first pulse in which a first voltage condition for setting the resistor 43 to a low resistance state is set is generated. The refresh control circuit 32 supplies the generated first pulse to the data line DL via the global data line GDL, and performs a refresh that causes the variable resistor 43 to be in a low resistance state (step S68).

  Next, when the refresh control circuit 32 determines that the data read from the memory cell MC is logic “0” (the variable resistor 43 of the data storage element 40 is in the high resistance state), The determination result indicating that it is “0” is output.

  When the memory cell MC is a 1T1R type, the refresh control circuit 32 can change the data storage element 40 according to the write signal WRz and the timing signal Timepz based on the determination result of logic “0” input from the control unit 30. A second voltage condition for setting the resistor 43 to a high resistance state is set. The memory cell MC to be refreshed is selected by the row decoder 12 and the column decoder 14, and the write circuit 18 refreshes the variable resistor 43 in a high resistance state based on the second voltage condition set by the refresh control circuit 32. Is executed (step S70).

  When the memory cell MC is a 1D1R type, the refresh control circuit 32 can change the data storage element 40 according to the write signal WRz and the timing signal Timepz based on the determination result of logic “0” input from the control unit 30. A second pulse in which a second voltage condition for setting the resistor 43 to a high resistance state is set is generated. The refresh control circuit 32 supplies the generated second pulse to the data line DL via the global data line GDL, and performs a refresh that causes the variable resistor 43 to be in a high resistance state (step S70).

  Next, when the refresh control circuit 32 determines that the storage mode of the data storage element 40 in the memory cell MC is the RAM mode based on the signal Mode input from the control unit 30 (step S60), the process proceeds to step S72. move on. The refresh control circuit 32 instructs the control unit 30 to read data from the memory cell MC without starting the built-in timer 36 (step S72). Data read from the memory cell MC is input to the refresh control circuit 32 via the data line DL and the global data line GDL. When the refresh control circuit 32 determines that the data read from the memory cell MC is logic “1” (the electrode 44 of the data storage element 40 is in a charged state), the refresh control circuit 32 determines whether the data is “1”. Output the result.

  When the memory cell MC is of the 1T1R type, the refresh control circuit 32 determines the electrode of the data storage element 40 according to the write signal WRz and the timing signal Timepz based on the determination result of logic “1” input from the control unit 30. 44, a third voltage condition for charging the electric charge is set. The memory cell MC to be refreshed is selected by the row decoder 12 and the column decoder 14, and the refresh for causing the electrode 44 to be in a charged state is executed by the write circuit 18 based on the third voltage condition set by the refresh control circuit 32. (Step S74).

  When the memory cell MC is of the 1D1R type, the refresh control circuit 32 receives the electrode of the data storage element 40 according to the write signal WRz and the timing signal Timepz based on the determination result of logic “1” input from the control unit 30. A third pulse in which a third voltage condition for charging the electric charge is set is generated. The refresh control circuit 32 supplies the generated third pulse to the data line DL via the global data line GDL, and performs refreshing for bringing the electrode 44 into a charged state (step S74).

  Next, when the refresh control circuit 32 determines that the storage mode of the data storage element 40 in the memory cell MC is the NVM mode based on the signal Mode input from the control unit 30 (step S60), the refresh control circuit No. 32 does not perform refresh for the memory cell MC storing data in the NVM mode. This is because the data storage element 40 that stores data in the NVM mode has a long data retention time, so that data is not lost even if refreshing is not performed.

  Here, FIG. 20 shows a timing chart showing rewriting (refreshing) to the data storage element 40 storing data in the MID mode in the case of the 1T1R type memory cell MC. FIG. 20A shows a timing chart of the refresh operation performed on the data storage element 40 in the memory cell MC in the logic “1” state, and FIG. 20B shows the logic “0”. 6 shows a timing chart of a refresh operation performed on the data storage element 40 in the memory cell MC in a state.

  In FIG. 20A, the refresh control circuit 32 determines that the memory cell MC is logic “1”, outputs the determination result to the control unit 30, and then the timing signal Timxpz supplied from the control unit 30 rises. (A). Accordingly, the word line WL rises and a gate voltage (Vg = 1.2 V) is applied to the gate of the memory cell MC to be refreshed (B). Subsequently, the timing signal Timepz supplied from the control unit 30 rises (C). Accordingly, the data line DL also rises, and a drain voltage (Vd = 4.0 V) is applied to the drain of the memory cell MC to be refreshed for a time (t = 50 ns) (D). Through the above process, the data storage element 40 in the memory cell MC can be refreshed.

  Similarly, in FIG. 20B, the refresh control circuit 32 determines that the memory cell MC is logic “0”, outputs the determination result to the control unit 30, and then supplies a timing signal supplied from the control unit 30. Timxpz rises (A). Accordingly, the word line WL rises and a gate voltage (Vg = 2.5 V) is applied to the gate of the memory cell MC to be refreshed (B). Subsequently, the timing signal Timepz supplied from the control unit 30 rises (C). Accordingly, the data line DL also rises, and a drain voltage (Vd = 1.2 V) is applied to the drain of the memory cell MC to be refreshed for a time (t = 50 ns) (D). Through the above process, the data storage element 40 in the memory cell MC can be refreshed.

  Next, FIG. 21 shows a timing chart showing rewrite (refresh) to the data storage element 40 for storing data in the MID mode in the case of the 1D1R type memory cell MC. FIG. 21A shows a timing chart of the refresh operation performed on the data storage element 40 in the memory cell MC in the logic “1” state, and FIG. 21B shows the logic “0”. 6 shows a timing chart of a refresh operation performed on the data storage element 40 in the memory cell MC in a state.

  In FIG. 21A, the refresh control circuit 32 determines that the memory cell MC is logic “1”, outputs the determination result to the control unit 30, and then the timing signal Timepz supplied from the control unit 30 rises. (A). Subsequently, the write signal WRHz rises (B), and the refresh control circuit 32 generates a first pulse corresponding to the time (t = 50 ns) and the write voltage (V = 4.0 V) according to the write signal WRHz. Then, the first pulse is supplied to the global data line GDL. The first pulse is also supplied to the data line DL connected to the global data line GDL (C), and the first pulse is applied to a desired memory cell MC. Through the above process, the data storage element in the memory cell MC can be refreshed. Here, the first pulse is a pulse that causes the variable resistor 43 of the data storage element to be in a low resistance state, and a pulse with a high voltage and a short time can be used.

  Similarly in FIG. 21B, the refresh control circuit 32 determines that the memory cell MC is logic “0”, outputs the determination result to the control unit 30, and then supplies the timing signal supplied from the control unit 30. Timepz rises (A). Subsequently, the write signal WRLz rises (B), and the refresh control circuit 32 generates a second pulse corresponding to the time (t = 125 ns) and the write voltage (V = 1.2 V) according to the write signal WRLz. The second pulse is supplied to the global data line GDL. The second pulse is also supplied to the data line DL connected to the global data line GDL (C), and the second pulse is applied to a desired memory cell. Through the above process, the data storage element in the memory cell MC can be refreshed. Here, the second pulse is a pulse that causes the variable resistor 43 of the data storage element to be in a high resistance state, and a low-voltage and long-time pulse can be used.

  The semiconductor device 100 according to the first embodiment includes a data storage element 40 including a variable resistor 43 and an electrode 44. The data storage element 40 has an MID mode (first mode) and an NVM mode (second mode) for storing data by changing the variable resistor 43 to either the low resistance state or the high resistance state. In addition, a RAM mode (third mode) in which data is stored according to the charge amount of the electrode 44 is provided. Further, the semiconductor device 100 has a refresh control circuit 32. The refresh control circuit 32 determines whether the variable resistance 43 of the data storage element 40 that stores data in the MID mode is in a low resistance state or a high resistance state. Then, the refresh control circuit 32 is either a first voltage condition for setting the variable resistor 43 of the data storage element 40 that stores data in the MID mode to a low resistance state or a second voltage condition for setting the variable resistance 43 to a high resistance state. Is used to refresh the data storage element 40 that stores data in the MID mode. By providing such a refresh control circuit 32, it is possible to perform refresh on a data storage element that stores data in the MID mode. For this reason, the data retention time of the memory cell MC that stores data in the MID mode can be extended, and for example, it can be used as a substantially nonvolatile storage element.

  Further, the high resistance state in the NVM mode of the data storage element 40 has a resistance value larger than the resistance value of the variable resistor 43 in the high resistance state in the MID mode, and the low resistance state in the NVM mode is the low resistance state in the MID mode. The resistance value is smaller than the resistance value of the variable resistor 43 in FIG. As described above, in the NVM mode, the resistance value of the variable resistor 43 in the high resistance state is increased, and the resistance value of the variable resistor 43 in the low resistance state is further decreased, whereby the memory cell MC that stores data in the NVM mode. Can be used as a nonvolatile memory element. For this reason, as shown in Table 2, the data retention time of the memory cell MC storing data in the NVM mode becomes long. Therefore, the refresh control circuit 32 does not perform refresh on the data storage element that stores data in the NVM mode.

  Further, in the RAM mode of the data storage element 40, data is stored by the amount of charge stored in the electrode 44. Thus, the memory cell MC that stores data in the RAM mode functions as a volatile storage element, and the data retention time is shortened as shown in Table 2. Therefore, refreshing is required to extend the data retention time. Therefore, the refresh control circuit 32 performs a refresh on the data storage element 40 that stores data in the RAM mode according to the third voltage condition for charging the electrode 44 with charges.

  As described above, the refresh control circuit 32 can control the refresh performed on the data storage element 40 in accordance with the storage mode of the data storage element 40. In other words, the refresh control circuit 32 can perform a refresh on the data storage element 40 by changing the voltage condition for data rewriting according to the storage mode of the data storage element 40.

  As described with reference to FIG. 21, in the 1D1R type memory cell MC, the refresh control circuit 32 supplies either the first pulse or the second pulse to the data line DL via the global data line GDL. The data storage element 40 in the memory cell MC connected to the data line DL is refreshed. Since a plurality of data lines DL are connected to the global data line GDL, by providing one refresh control circuit 32, it is possible to perform a refresh on the plurality of data storage elements 40.

  In the refresh performed on the data storage element 40 that stores data in the MID mode, the variable resistance 43 of the data storage element 40 before the refresh is already in a low resistance state or a high resistance state to some extent. Therefore, refresh can be performed using a voltage and a voltage application time that are lower than the voltage and the voltage application time at the time of writing shown in Tables 3 and 4. Thereby, power consumption can be reduced. Further, the refresh may be executed by rewriting the data a plurality of times using a lower voltage and a shorter voltage application time. Thereby, the stress applied to the variable resistor 43 of the data storage element 40 can be reduced.

  Further, as shown in FIG. 18, the refresh control circuit 32 includes a timer 36. The timer 36 is set in advance with a time corresponding to the refresh interval performed for the data storage element 40 stored in the MID mode. The set time can be arbitrarily changed, and it is preferable to set a time shorter than the data holding time of the data storage element 40 stored in the MID mode. Then, the refresh control circuit 32 determines whether the variable resistor 43 of the data storage element 40 to be refreshed is in a low resistance state or a high resistance state according to the set time, and sets the variable resistor 43 in the low resistance state. The data storage element 40 is refreshed in accordance with either the first voltage condition for causing the low resistance state or the second voltage condition for causing the high resistance state. Thereby, for example, even when the data retention time of the data storage element 40 is one day or one year, it is possible to flexibly cope with the refresh performed on the data storage element 40.

  In the first embodiment, the case where the data storage element 40 has three storage modes of the NVM mode, the MID mode, and the RAM mode has been described as an example. However, the present invention is not limited to this case. It is only necessary to change the variable resistance to either the low resistance state or the high resistance state, as in the MID mode, and to have a volatile memory mode.

  In the first embodiment, as shown in FIG. 18, the refresh control circuit 32 includes the refresh circuit 34 and the timer 36. However, the refresh control circuit 32 may further include a counter 38. . FIG. 22 shows a block diagram of the refresh control circuit 32 further provided with a counter 38. In FIG. 22, a counter 38 is provided between the timer 36 and the refresh circuit 34. The counter 38 counts the address and the like of the memory cell MC that performs the refresh according to the signal timer output from the timer 36 to the refresh circuit 34. That is, for example, when the third refresh is performed on the data storage element of the memory cell MC that stores data in the MID mode, the counter 38 counts the number of refreshes as 3 for the memory cell MC.

  When refresh is repeatedly performed on the data storage element 40 that stores data in the MID mode, the data storage element 40 approaches a non-volatile property. FIG. 23 (a) to FIG. 23 (d) show the relationship between the number of refreshes performed, the magnitude of the voltage required for rewriting for refresh, and the voltage application time in the MID mode and the RAM mode. Yes. 23A shows the gate voltage of the 1T1R type memory cell, FIG. 23B shows the voltage application time applied to the 1T1R type memory cell, FIG. 23C shows the drain (cathode) voltage of the memory cell, and FIG. Indicates the voltage application time applied to the 1D1R type memory cell.

  In FIG. 23A and FIG. 23C, the horizontal axis indicates the number of times refresh is executed, and the vertical axis indicates the magnitude of the voltage necessary for rewriting for refresh. A solid line in the graph indicates a magnitude of a voltage necessary for setting the variable resistor 43 of the data storage element 40 to a high resistance state (logic “0”) by refresh in the MID mode, and a one-dot chain line indicates the variable resistor 43. Indicates the magnitude of the voltage required to bring the signal to the low resistance state (logic “1”). A two-dot chain line indicates the magnitude of a voltage necessary for accumulating charges in the electrode 44 of the data storage element 40 by refresh in the RAM mode. In FIG. 23B and FIG. 23D, the horizontal axis indicates the number of times refresh is executed, and the vertical axis indicates the voltage application time required for rewriting for refresh. A solid line in the graph indicates refresh in the MID mode, and a two-dot chain line indicates refresh in the RAM mode.

  According to FIGS. 23A and 23C, in the case of refresh in the MID mode, it can be seen that the voltage necessary for rewriting for refresh decreases as the number of refreshes increases. On the other hand, in the case of refresh in the RAM mode, it can be seen that the voltage required for rewriting for refresh is constant regardless of the number of refreshes. According to FIGS. 23B and 23D, in the case of refresh in the MID mode, it can be seen that as the number of refreshes increases, the voltage application time necessary for rewriting for refreshing becomes shorter. On the other hand, in the case of refresh in the RAM mode, it can be seen that the voltage application time required for rewriting for refresh is constant regardless of the number of refreshes.

  Therefore, when the refresh is performed on the data storage element 40 that stores data in the MID mode, the number of refreshes in the MID mode performed on the data storage element 40 is measured. It is preferable to perform refresh by changing the first voltage condition and the second voltage condition. In this way, by performing refresh under the optimum rewrite voltage condition corresponding to the state of the data storage element 40, it is possible to prevent the data storage element 40 from becoming non-volatile and increase the number of rewrites. In addition, the refresh performed on the data storage element 40 that stores data in the RAM mode is refreshed without changing the third voltage condition regardless of the number of refreshes performed on the data storage element 40 in the RAM mode. Is preferably performed.

  FIG. 24 is a block diagram of a part of the semiconductor device 100 according to the second embodiment. Other parts have the same configuration as that of the first embodiment. In FIG. 24, the refresh control circuit 32 is provided between the sense amplifier 22 and the global data line GDL. A data line DL is connected to the sense amplifier 22. A refresh selection circuit 35 is provided corresponding to the refresh control circuit 32. As in the first embodiment, the refresh control circuit 32 determines the storage mode of the data storage element 40 in the memory cell MC. If the refresh control circuit 32 determines that the storage mode of the data storage element 40 is the MID mode, whether the data read from the memory cell MC is logic “1” or logic “0”. judge. Then, based on the determination result, a switching signal SWz for selecting Timeyhpz, Timeylpz is output to the refresh selection circuit 35.

  The refresh selection circuit 35 selects one of the timing signals Timeyphz and Timepyz output from the control unit 30 based on the switching signal SWz input from the refresh control circuit 32 and inputs the selected timing signal to the refresh control circuit 32. In this case, the timing signals Timeyphz and Timep1z act as write signals.

  The refresh control circuit 32 generates a rewrite pulse for refresh in response to the timing (write) signal Timeyphz or Timepyz input from the refresh selection circuit 35. The refresh control circuit 32 performs refresh on the data storage element 40 in the memory cell MC by supplying the generated rewrite pulse to the data line DL.

  Here, FIG. 25 shows a timing chart showing rewrite (refresh) to the data storage element 40 storing data in the MID mode in the case of the 1D1R type memory cell MC. FIG. 25A shows a timing chart of the refresh operation performed on the data storage element in the memory cell MC in the logic “1” state, and FIG. 25B shows the logic “0” state. 2 is a timing chart of a refresh operation performed on the data storage element in the memory cell MC.

  In FIG. 25A, the refresh control circuit 32 determines that the memory cell MC is logic “1”, and the switching signal SWz corresponding to the determination result becomes H level (A). Based on the switching signal SWz, the refresh selection circuit 35 selects a timing signal Timeyphz that causes the variable resistor 43 of the data storage element to be in a low resistance state among the timing signals Timepz output from the control unit 30.

  The timing signal Timeyphz supplied from the refresh selection circuit 35 rises (B), and the refresh control circuit 32 determines the time (t = 50 ns) and the write voltage (V = 4.0 V) according to the timing (write) signal Timeyphz. A first pulse corresponding to is generated, and this first pulse is applied to a desired memory cell MC via the data line DL (C). Through the above process, the data storage element in the memory cell MC can be refreshed to a low resistance state.

  Similarly in FIG. 25B, the refresh control circuit 32 determines that the memory cell MC is logic “0”, and the switching signal SWz becomes L level according to the determination result (A). Based on the switching signal SWz, the refresh selection circuit 35 selects a timing signal Timep1z that causes the variable resistor 43 of the data storage element to be in a high resistance state among the timing signals Timepz output from the control unit 30.

  The timing signal Timep1z supplied from the refresh selection circuit 35 rises (B), and the refresh control circuit 32 determines the time (t = 125 ns) and the write voltage (V = 1.2 V) according to the timing (write) signal Timep1z. A second pulse corresponding to is generated, and this second pulse is applied to the desired memory cell MC via the data line DL (C). Through the above process, the resistance element 43 of the data storage element in the memory cell MC can be refreshed to a high resistance state.

  In the semiconductor device 100 according to the second embodiment, as shown in FIG. 24, the refresh control circuit 32 is provided between the sense amplifier 22 and the global data line GDL. A refresh selection circuit 35 is provided corresponding to the refresh control circuit 32. A data line DL is connected to the sense amplifier 22. Thereby, the refresh performed on the data storage element 40 can be controlled in units of data lines DL. That is, the determination and refresh of the logic state of the data storage element 40 can be executed for each of the plurality of data lines DL. For this reason, it becomes possible to perform the refresh simultaneously on the data storage elements 40 respectively connected to the plurality of data lines DL. Further, unlike the first embodiment, it is not necessary to output the data of the memory cell MC to the global data line GDL. Therefore, the refresh operation can be speeded up as compared with the first embodiment.

  In the second embodiment, when the refresh interval performed for the data storage elements 40 that store data in the MID mode is the same for all the data storage elements 40, each refresh control circuit 32 is set as shown in FIG. There may be a case where one timer 36 is provided for all the refresh control circuits 32 without providing the timer 36.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

FIG. 1 is a block diagram illustrating the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a diagram showing the configuration of the memory cell. FIG. 3 is a diagram showing the configuration of the data storage element. FIG. 4 is a diagram showing voltage-current characteristics of the data storage element. FIG. 5 shows the configuration of the row decoder. FIG. 6 shows the configuration of the column decoder. FIG. 7 is a diagram showing the configuration of the write circuit. FIG. 8 is a diagram illustrating a partial configuration of the data line selection unit and the memory cell array. FIG. 9 is a flowchart showing an operation at the time of data writing in the 1T1R type memory cell MC. FIG. 10 is a diagram showing the configuration of the peripheral circuit in FIG. FIG. 11 is a flowchart showing an operation at the time of data writing in the 1D1R type memory cell MC. FIG. 12 is a diagram showing the configuration of the reset circuit and the sense amplifier. FIG. 13 is a diagram showing the configuration of the clamp circuit. FIG. 14 is a diagram showing the configuration of the sense amplifier driver. FIG. 15 is a flowchart showing an operation at the time of data reading. FIG. 16 is a timing chart at the time of data reading in the NVM mode and the MID mode. FIG. 17 is a timing chart when reading data in the RAM mode. FIG. 18 is a block diagram showing the configuration of the refresh control circuit. FIG. 19 is a flowchart showing the operation during refresh. FIG. 20 is a timing chart of the refresh operation in the MID mode in the case of the 1T1R type memory cell MC. FIG. 21 is a timing chart of the refresh operation in the MID mode in the case of the 1D1R type memory cell MC. FIG. 22 is a block diagram showing a configuration of a refresh control circuit including a counter. FIG. 23 is a diagram showing the relationship between the number of refreshes, the applied voltage, and the voltage application time. FIG. 24 is a block diagram illustrating a part of the configuration of the semiconductor device according to the second embodiment. FIG. 25 is a timing chart of the refresh operation in the MID mode in the case of the 1D1R type memory cell MC. FIG. 26 is a block diagram showing a configuration when one timer is provided for a plurality of refresh control circuits.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory cell array 12 Row decoder 14 Column decoder 16 Address buffer 18 Write circuit 20 Reset circuit 21 Clamp circuit 22 Sense amplifier 24 Sense amplifier driver 26 Input / output circuit 28 Selection register 30 Control part 32 Refresh control circuit 34 Refresh circuit 35 Refresh selection circuit 36 Timer 38 Counter 40 Data storage element 41 Selection transistor 42 Selection diode 43 Variable resistance 44 Electrode 46 Insulation part 60 Voltage selection part 62 Data line selection part 100 Semiconductor device

Claims (9)

A data storage element having a variable resistor and storing data in a storage mode for storing data according to a resistance value of the variable resistor, wherein the variable resistor is changed to a low resistance state when a first voltage condition is supplied. A data storage element for storing data by changing the variable resistance to a high resistance state when the second voltage condition is supplied ;
The variable resistor is determined whether the low resistance state and any state of the high-resistance state, anda refresh control circuit for refreshing the data storage element,
The refresh control circuit measures the number of refreshes performed on the data storage element, and refreshes the data storage element in accordance with the number of refreshes . A data line to which the data storage element is connected;
A global data line to which a plurality of the data lines are connected, and
Said refresh control circuit, wherein by supplying either the first voltage condition and said second voltage condition to said data lines via the global data lines, refresh in the data storage element connected to the data line The semiconductor device according to claim 1, wherein: A data line to which the data storage element is connected;
A sense amplifier connected to the data line;
A global data line to which a plurality of the data lines are connected via the sense amplifier;
2. The semiconductor device according to claim 1, wherein the refresh control circuit is connected between the sense amplifier and the global data line and performs the determination and the refresh for each of the plurality of data lines. The data storage element has a resistance value larger than the resistance value of the variable resistor in a high resistance state in a storage mode in which data is stored by the resistance value of the variable resistor in addition to a storage mode in which data is stored by the resistance value of the variable resistor. Data is stored by changing to a low resistance state consisting of a resistance value smaller than the resistance value of the variable resistance in a high resistance state consisting of and a low resistance state of the storage mode for storing data according to the resistance value of the variable resistance. Another storage mode for storing data according to the resistance value of the variable resistor ;
Said refresh control circuit, a semiconductor device of any one of claims 1 to 3, characterized in that does not perform a refresh for data storage element that stores data in the other storage modes. The data storage element has a storage mode for storing data according to the amount of charge stored in a capacitance generated in electrodes provided at both ends of the variable resistor ,
The refresh control circuit refreshes a data storage element that stores data in a storage mode for storing data according to the charge amount , under a third voltage condition for charging the electrode with charge. the semiconductor device of any one of claims 1 to 4. The refresh control circuit is configured to store data according to the charge amount without changing the third voltage condition depending on the number of refreshes for a data storage element that stores data in a storage mode for storing data according to the charge amount. 6. The semiconductor device according to claim 5 , wherein refresh is performed on a data storage element that stores data in a storage mode for storing. The refresh control circuit measures the number of refreshes performed on a data storage element that stores data in a storage mode in which data is stored according to a resistance value of the variable resistor, and according to the number of times, the first voltage condition and the The semiconductor device according to claim 6 , wherein the second voltage condition is changed, and the data storage element that stores data is refreshed in a storage mode in which data is stored according to the resistance value of the variable resistor . The refresh control circuit performs data rewrite for a data storage element that stores data in a storage mode for storing data according to a resistance value of the variable resistor, by repeating rewriting a plurality of times, thereby obtaining data according to the resistance value of the variable resistor. the semiconductor device of any one of claims 1 to 7, characterized in that the refresh data storage device that stores data in storage mode for storing. And a refresh control circuit for refreshing the data storage elements for storing data in the storage mode and the data storage element having a variable resistance is changed to either a low resistance state and high resistance state storage mode for storing data A method for controlling a semiconductor device, comprising:
Determining whether the variable resistance of the data storage element that stores data in the storage mode is in the low resistance state or the high resistance state;
The for causing the variable resistance of the data storage element that stores data at a first voltage condition and the storage mode for causing the variable resistance of the data storage elements for storing data in the storage mode to the low resistance state to the high resistance state by either of the two voltage conditions, have a, and performing refresh the data storage elements for storing data in the storage mode,
In the refreshing step, the number of refreshes performed on the data storage element is measured, and the data storage element is refreshed according to the number of times .

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