KR100871880B1 - Method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and the phase change memory device - Google Patents

Abstract

A method of reducing reset current of a memory cell of a phase change memory device is provided. The method comprises converting at least a portion of the phase change material comprising the first crystalline phase into one of the second crystalline phase and the amorphous phase. The second crystal phase transitions to the amorphous phase more easily than the first crystal phase. For example, the first crystal phase may have a hexagonal dense structure, and the second crystal phase may have a face-centered cubic structure.

Phase change, crystalline phase, amorphous phase, hexagonal density, face center cubic

Description

METHODE FOR REDUCING A RESET CURRENT FOR RESETTING A PORTION OF A PHASE CHANGE MATERIAL IN A MEMORY CELL OF A PHASE CHANGE MEMORY DEVICE AND THE PHASE CHANGE MEMORY DEVICE}

1 shows the structure of a phase change memory device of the prior art.

2A illustrates a set and reset pulse applied to programming the memory cell of FIG. 1.

FIG. 2B shows the resistance state of the memory cell as a result of the pulses applied to FIG. 2A.

3 illustrates a programmable volume of the phase change material in the memory cell of FIG. 1.

4 is a diagram showing the distribution of set resistance of phase change material before firing.

5 is a diagram showing the distribution of set resistance of phase change material after firing.

6 is a flowchart illustrating a firing method according to an embodiment of the present invention.

7 is a block diagram illustrating a phase change memory device according to the present invention.

8 is a schematic diagram illustrating the drive unit of FIG. 7.

FIG. 9 is a timing diagram illustrating an operation of the phase change memory device of FIG. 7.

10A and 10B show embodiments of the firing current applied to the phase change material according to the present invention.

11 shows the change ratio of the reset current to the change ratio of the firing current.

12 shows the effect of the number of firing operations on the reset current.

13 illustrates the effect of the firing operation on the resistance difference between the set and reset states.

14A and 14B show specific examples of the impact firing for the reset current.

15 shows another embodiment of firing according to the present invention.

16 illustrates another embodiment of a firing operation in accordance with the present invention.

The present invention relates to a method and method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device.

1 shows the structure of a phase change memory cell of the prior art. As shown, a lower insulating layer 102 is formed over the substrate 100. The first contact hole 105 is formed in the lower insulating layer 102, and the lower electrode 113 (sometimes a heater) is formed in the first contact hole 105. Typically, the lower electrode 113 is made of TiAlN, TiN and the like. A phase change material 115 is formed on the lower insulating layer 102 on the lower electrode 113. Typically, the phase change material is a chalcogenide such as Ge ₂ Sb ₂ Te ₅ or the like. An upper electrode 119 is formed on the phase change material 115. The upper electrode 119 may be formed of TiN, TaN, WN, or the like. An upper insulating layer 122 is formed on the substrate 100. The second contact hole 125 is formed in the upper insulating layer 122 to expose a portion of the upper electrode 119. The conductive plug 127 is formed in the second contact hole 125. The conductive plug 127 may be formed of W, Al, Cu, or the like. A metal pattern 129 (eg, conductive line) may then be formed over the upper insulating layer 122 in contact with the plug 127. The metal pattern may be formed of the same material as the plug 127. Typically, the metal pattern 129 is a bit line of the phase change memory device of the phase change memory cell of FIG. 1.

The memory cell of FIG. 1 is programmable by applying heat to the phase change material 115. The application of heat may be performed by passing a current through the phase change material 115 (eg, by applying a current to the upper electrode 119). 2A shows the current reset pulse and a current set pulse for programming the phase change material 115. As shown in Fig. 2A, the reset pulse is a high current supplied for a short period, while the set pulse is a low current supplied for a long time. As shown in FIG. 2B, the reset pulse has the effect of increasing the resistance of the phase change material 115, while the set pulse has the effect of lowering the resistance of the phase change material 115. The change in resistance occurs approximately as the state change of the phase change material 115. The reset pulse causes the programmable volume of the phase change material to be amorphous as shown in FIG. 3. In contrast, the set pulse causes the programmable volume of the phase change material 115 to be crystalline. The higher resistance amorphous state generally corresponds to the storage of logic "1", and the lower resistance crystalline state corresponds to the storage of logic "0".

In order to maintain low power consumption, it is desirable to make both the reset current and the set current relatively low. However, it is also desirable for the resistance of the phase change material as a result of the reset operation to have as much difference as possible with respect to the resistance of the phase change material after the set operation. In general, as the reset current decreases, the resistance difference between the reset and set states is reduced. Thus, while undesired compromises exist between attempts to achieve low set and reset currents, they also maintain desirable differences in the set and reset resistances.

US 2005/0029502 A1 provides a method that can speed up the set program operation to change a phase change material to a crystalline state.

An object of the present invention is to provide a method capable of reducing the reset current of a phase change memory cell.

Another object of the present invention is to provide a phase change memory device suitable for reducing a reset current of a phase change memory cell.

The present invention provides a method and phase change memory device for reducing a reset current for resetting a portion of phase change material in a memory cell of a phase change memory device. The method includes converting at least a portion of the phase change material comprising the first crystalline phase into one of the second crystalline phase and the amorphous phase. The second crystal phase transitions to the amorphous phase more easily than the first crystal phase. For example, the first crystal phase may have a hexagonal dense structure, and the second crystal phase may have a face-centered cubic structure.

In one embodiment, the conversion is performed via heat treatment. For example, a Rapid Thermal Annealing (RTA) process at a temperature above the melting point of the phase change material may be performed to convert the first crystalline phase into the amorphous phase.

According to another embodiment, the heat treatment may include baking the phase change memory device at a temperature lower than the melting point of the phase change material for a predetermined period to convert the first crystal phase into the second crystal phase.

In another embodiment of the present invention, the converting step is accomplished by applying a current to the phase change material. For example, if the conversion step is not performed, the applied current is greater than the reset current. As a more detailed example, when the conversion step is not performed, the applied current may be 1.1 times the reset current. In another embodiment of the present invention, the application of the current is performed after baking of the phase change memory device as described above.

In another embodiment of the present invention, the reduction of the reset current is obtained by converting at least a portion of the phase change material in a mixed phase state into a single phase state. For example, at least a portion of the phase change material in the mixed crystalline state changes to a single phase state. The phase state may be a microcrystalline phase or a single crystalline phase.

The invention also relates to a phase change memory device.

In example embodiments, the phase change memory device may include an upper electrode, a lower electrode, and a phase change material disposed between the upper and lower electrodes. The phase change material may be a whole single phase, and the single phase may be one of an amorphous phase and a face-centered cubic phase.

In one embodiment, the phase change material includes a bottom in contact with the bottom electrode, and a remaining portion. The lower portion may be one of a first crystalline phase and an amorphous phase. The remaining portion comprises at least a second crystalline phase. The first crystal phase transitions to the amorphous phase more easily than the second crystal phase.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

Before the operation of the phase change memory device employing the phase change memory cells as shown in FIG. 1, a firing operation may be performed. The firing operation is a task that generates heat in at least a portion of the phase change material so that improved results can be obtained during subsequent operations involving the phase change material. One refinement example according to the invention is a reduced reset current.

4 is a view for explaining the distribution of the set resistance of the phase change material before the initial firing. Referring to FIG. 4, in the region i, the set resistance values are widely distributed, and the average set resistance value is high. Thus, in the reading operation, defects may occur, and thus the yield may be reduced.

5 is a diagram illustrating a set resistance distribution of a phase change material after the initial firing. Referring to FIG. 5, in region (ii), the set resistance values are uniformly distributed in a narrow width, and the average set resistance value is lower than that of the phase change material before the initial firing. The initial firing operation is performed to provide a more stable read operation of the phase change memory device.

For illustrative purposes, the embodiment of the present invention will be described assuming that the phase change memory cells have the structure shown in FIG. However, it will be apparent to one skilled in the art that other phase change memory cell structures may be used as embodiments of the present invention.

6 is a flowchart illustrating an initial firing method according to an embodiment of the present invention. Referring to FIG. 6, in the initial firing method 300 of the phase change memory device having the phase change material according to an embodiment of the present invention, selecting one of a plurality of memory array blocks (310), the selected Sequentially enabling 320 word lines of the memory array block, and applying 330 a firing current to the bit lines of the selected memory cell array block. The firing current is greater than the reset current, which causes the phase change material to be in a reset state.

7 is a block diagram illustrating an embodiment of the phase change memory device 400 according to the present invention. Referring to FIG. 7, the phase change memory device 400 includes a plurality of memory cell array blocks BLK1 and BLK2 to BLKi, a counter clock generator 410, a decoder 420, and a driver 440. do. Each memory cell array block BLK1, BLK2 to BLKi includes phase change memory cells as shown in FIG. 1. The counter clock generator 410 outputs first to third counter clock signals CCLK1, CCLK2, and CCLK3 in response to an external clock signal EXCLK and a firing mode signal XWIF. The third counter clock signals CCLK1, CCLK2, and CCLK3 have different periods.

The decoding unit 420 selects one of the plurality of memory cell array blocks BLK1, BLK2 to BLKi in response to the first to third counter clock signals CCLK1, CCLK2, and CCLK3. Outputs an address BLKADD, a word line address WLADD that enables word lines of the selected memory cell array block, and a redundant word line address REDADD that enables redundant word lines of the selected memory cell array block. .

The driver 440 applies a firing current IFC to the memory cell array blocks BLK1 and BLK2 to BLKi in response to the firing mode signal XWIF.

The phase change memory device and the initial firing method according to an embodiment of the present invention will be described with reference to FIGS. 6 and 7. The memory cell array blocks BLK1 and BLK2 to BLKi in the phase change memory device 400 may include a plurality of phase change memory cells (not shown). The counter clock generator 410 outputs the first to third counter clock signals CCLK1, CCLK2, and CCLK3 in response to the external clock signal EXCLK and the firing mode signal XWIF. The first to third counter clock signals CCLK1, CCLK2, and CCLK3 have different periods.

The external clock signal EXCLK having a clock signal period is input from the outside and is activated only in the initial firing mode when the initial firing operation is performed. The firing mode signal XWIF is generated when the pulse change memory device 400 is in the starting firing mode.

The counter clock generator 410 includes a plurality of counters. The output of the counters is decoded to sequentially select the memory cell array blocks BLK1, BLK2 to BLKi so that the initial firing operation can be performed.

The counter clock generator 410 may include the first to nth row counters RC1 and RC2 to RCn, the redundant counter RDDC, and the first to mth column counters CC1 and CC2 to CCm. It includes.

The first to nth low counters RC1 to RCN are turned on or off in response to the firing mode signal XWIF, and the first to nth low counters in response to the external clock signal EXCLK. The clock signals RCCLK1 and RCCLK2 to RCCLKn are generated, but the first to Nth low counter clock signals RCCLK1 and RCCLK2 to RCCLKn constitute the first counter clock signal CCLK1.

The redundant counter RDDC is turned on or off in response to the firing mode signal XWIF and generates the second counter clock signal CCLK2 in response to the external clock signal EXCLK. The first to m th column counters CC1, CC2 to CCm are turned on or off in response to the firing mode signal XWIF, and the first to m th column counters in response to the external clock signal EXCLK. The clock signals CCCLK1 and CCCLK2 to CCCLKm are generated, but the first to m th column counter clock signals CCCLK1 and CCCLK2 to CCCLKm constitute the third counter clock signal CCLK3.

The second to nth row counters RC2 to RCn are sequentially operated in response to the carry C output from the previous low counter. The redundant counter RDDC is operated in response to the carry C output from the nth low counter RCn. The first column counter CC1 is operated in response to the carry C output from the redundant counter RDDC. The second to mth column counters CC2 to CCm are sequentially operated in response to the carry C outputted from the previous column counter.

The operation of the counter clock generator 410 will be described in detail with reference to the timing diagram of FIG. 9. FIG. 9 is a timing diagram illustrating an operation of the phase change memory device of FIG. 7.

The first to nth row counters RC1 and RC2 to RCN, the redundant counter RDDC, and the first to mth column counters CC1 and CC2 to CCm are connected to the external clock signal EXCLK and They perform their own count operation in response to the firing mode signal XWIF. When the firing mode signal XWIF is disabled, the counters of the counter clock generator 410 are also turned off. In addition, the second row counter RC2 is operated in response to the carry C generated by the first row counter RC1. The third row counter RC3 is operated in response to the carry C generated by the second row counter RC2. The redundant counter RDDC is operated in response to the carry C generated by the n row counter RCn. The first column counter CC1 is operated in response to the carry C generated by the redundant counter RDDC. Similarly, the m-th column counter CCm is operated in response to the carry C generated by the m-1 column counter (not shown). In this manner, the counters of the counter clock generator 410 are sequentially operated.

As shown in FIG. 9, the periods of the signals generated from the counters of the counter clock generator 410 are sequentially doubled. That is, the first to nth low counter clock signals RCCLK1 and RCCLK2 to RCCLKn output from the first to nth low counters RC1 to RCn are sequentially sequentially doubled. The period of the second counter clock signal CCLK2 output from the redundant counter RDDC is twice the period of the nth low counter clock signal RCCLKn output from the nth low counter RCn. The period of the first column counter clock signal CCCLK1 output from the first column counter CC1 is twice the period of the second counter clock signal CCLK2 output from the redundant counter RDDC. Similarly, the periods of the second to m th counter clock signals CCCLK2 to CCCLKm are sequentially doubled. Accordingly, the first to third counter clock signals CCLK1, CCLK2, and CCLK3 are sequentially generated. The first to third counter clock signals CCLK1, CCLK2, and CCLK3 are input to the decoding unit 420.

The decoding unit 420 selects one of the plurality of memory cell array blocks BLK1, BLK2, BLKi in response to the first to third counter clock signals CCLK1, CCLK2, and CCLK3. A block address BLKADD, the word line addresses WLADD for enabling the word lines of the selected memory cell array block, and the redundant word line address for enabling the redundant word line of the selected memory cell array block. ) The decoding unit 420 includes a row decoder 425, a redundant decoder 430, and a column decoder 435. The row decoder 425 outputs the word line addresses WLADD, which are sequentially enabled in response to the first counter clock signal CCLK1. That is, the row decoder 425 receives and decodes the first to nth row counter clock signals RCCLK1 and RCCLK2 to RCCLKn having different periods, and outputs a decoding result as a word line address WLADD. The word line addresses WLADD sequentially enable word lines of the selected memory cell array block from most significant bit to least significant bit.

The redundant decoder 425 outputs the redundant word line address REDADD in response to a second counter clock signal CCLK2. The column decoder 435 outputs the block address BLKADD, which selects one of the plurality of memory cell array blocks BLK1, BLK2 to BLKi in response to the third counter clock signal CCLK3. . The column counter 435 receives and decodes the first to m th column counter clock signals CCCLK1 and CCCLK2 to CCCLKm having different periods, and then outputs the decoding result as the block address BLKADD. The block address BLKADD enables all bit lines of the selected memory cell array block. The structure of the decoding unit 420 for receiving and decoding the clock signals output from the counter clock generator 410 may vary.

The driver 440 applies a firing current IFC to the memory cell array blocks BLK1 and BLK2 to BLKi in response to a firing mode signal XWIF. The operation of the driving unit 440 is described with reference to FIG. 8. 8 is a view for explaining the driving unit 440 of FIG. 7. Referring to FIG. 8, the driver 440 has a first end connected to a firing voltage VPP, a second end connected to bit lines BL0 to BLp of the memory cell array block, and a gate to a gate. A plurality of transistors TR1 to TRl are connected to the firing mode signal XWIF. The transistors TR1 to TRl have a size suitable for applying the firing current IFC to the bit lines BL0 and BL1 to BLp.

FIG. 8 illustrates only the first memory cell array block BLK1 having k + 1 word lines, p + 1 bit lines, and one redundant word line WLred.

The block address BLKADD automatically selects the first memory cell array block BLK1 at the beginning of the firing operation. The row decoder 425, which receives the first counter clock signal CCLK1, outputs the word line address WLADD to output the word line address WLADD to the word lines WL0 to WLk of the first memory cell array block BLK1. ) Enable sequentially. That is, first of all, the first word line WL0 is enabled. The driver 440 applies a firing current IFC to the bit lines BL0 to BLp of the first memory cell array block BLK1. Then, an initial firing operation is performed on the phase change materials of the memory cell array connected to the first word line WL0.

Next, the first word line WL0 is disabled and the second word line WL1 is enabled. Then, an initial firing operation is performed on the phase change materials of the memory cell array connected to the second word line WL1. In this manner, an initial firing operation is performed on the phase change materials of the memory cell array connected to the k-th word line WLk and the redundant word line WLred. Then, the initial firing operation of the first memory cell array block BLK1 is completed. The first to nth low counters RC1, RC2 to RCn and the redundant counter RDDC of the counter clock generator 410 are sequentially operated to sequentially operate the first to nth low counter clocks RCCLK1. Since RCCLK2 and RCCLKn and the second counter clock CCLK2 are output, the first to k th word lines WL0 and WL1 to WLk and the redundant word line WLred are sequentially enabled.

When the redundant word line WLred is disabled, the column decoder 435 outputs the block address BLKADD by the operations of the first to m th column counters CC1, CC2 to CCm. The block address BLKADD selects the second memory cell array block BLK2. This can be seen from the timing diagram of FIG. When the second memory cell array block BLK2 is selected, the first to nth word lines (not shown) and redundant word lines (not shown) are sequentially enabled, and a firing operation is performed.

The firing voltage VPP has a voltage level equal to or greater than the power supply voltage level. In addition, the voltage level may be increased or decreased in consideration of the number of memory cell arrays connected thereto. The firing voltage VPP will be described in more detail in other embodiments of the present invention. The firing current IFC is a larger current than the reset current and will be described in more detail in other embodiments of the present invention.

The driving unit 440 selects the firing current IFC only as bit lines of the phase change memory cell array selected by the block address BLKADD in response to the block address BLKADD and the firing mode signal XWIF. It may further include a control unit 510 to control to apply. That is, the firing current IFC can be applied only to the selected memory cell array block, thereby making the firing operation more accurate.

Can be performed. The controller 510 may be a NAND gate. That is, only when both the block address BLKADD and the firing mode signal XWIF are enabled at the high level, the output of the NAND gate is at the low level to turn on the transistors TR1 to TRl. The transistors TR1 to TRl are shown as PMOS transistors, but are not limited thereto.

The phase change memory device 400 according to an exemplary embodiment of the present invention converts an externally input signal into an external clock signal EXCLK, a firing mode signal XWIF, a firing voltage VPP, a power supply voltage and a ground voltage. By minimizing, many chips can be tested at one time on one wafer.

The inventors of the present application have found that in the crystalline state, the phase change material is a mixture of hexagonal dense (HCP) crystal structures and face centered cubic (FCC) crystal structures. The FCC crystal structure provides a resistance that is about on the order of magnitude larger than the HCP crystal structure. However, the inventors have found that more energy is needed to convert the HCP crystal structure to the amorphous phase than the energy required to convert the FCC crystal structure to the amorphous phase. In another manner described above, the FCC state is more desirable for crystal-amorphous transitions than the HCP because the FCC state transitions more easily from a crystalline state to an amorphous state.

The inventors have also found that by applying a sufficiently high firing current or temperature, the phase change material or portion thereof (eg, programmable volume) can change to an amorphous or FCC crystalline phase. In addition, the inventors have discovered that, after this firing, at three time points, the programmable volume of the phase change material will achieve the FCC crystalline state. As a result, the inventors have found that by appropriately selecting the firing currents, they can reduce the reset currents necessary to achieve the reset state. Such firing also reduces the resistance of the set state, but provides a margin between the set and reset resistors that is greater than that present prior to firing.

10A illustrates one embodiment of a firing current applied in accordance with the present invention. The application of the firing current may be performed in the same manner as in the above-described embodiment. As shown, by applying a relatively high current pulse, the phase change material is converted to an amorphous phase after firing. As shown in FIG. 10A, this results in requiring a lower reset current during subsequent operation.

Figure 10b shows another embodiment of the present invention. In this embodiment, the same high firing current is applied, and then gradually lower current is applied. As a result of this firing operation, the phase change material is converted into the high resistance FCC crystal state. However, the same effect is obtained. That is, the same low reset current and low set resistance state are obtained.

11 shows the effect of firing current on the reset current. In particular, this shows a decrease in the ratio of the reset current to an increase in the ratio of the firing current to the initial pre-firing reset current. Here, the width of the reset pulse is set at 500 nanoseconds, which is consistent with the embodiment of FIG. 10A. In other words, the firing allows the phase change material to acquire an amorphous phase. As shown, as the reset current increases above the initial pre-firing reset current, the post-firing reset current decreases. In particular, when the firing current increases to 10% to 20% (eg, 1.1 to 1.2 times the initial reset current) or more of the initial reset current, the reset current is substantially reduced.

12 shows the effect of the number of firings on the reset current. For a firing current 20% greater than the initial pre-firing reset current (e.g., 1.2 times the initial reset current) and a pulse width of 500 nanoseconds (acquiring an amorphous phase after firing), FIG. The change of the reset current according to the number of such firings is shown. As shown, this figure shows that the reset current is not very affected by the energization of multiple firings.

Figure 13 shows the effect of firing according to the invention on the resistance margin between the reset and set states. The left side of FIG. 13 shows the resistance distribution of the reset and set states before firing. 13 shows the distribution of the resistance in the reset and set states after firing. As shown in Figure 13, prior to firing, the set and reset distributions almost overlap. As a result, memory defects may occur. In contrast, after firing, a much larger margin exists between the set and reset distributions, which significantly reduces the number of memory defects.

14A and 14B show two improvements due to the firing process according to the present invention. FIG. 14A shows a case in which the firing acquires an amorphous phase, and FIG. 14B shows a case in which the firing acquires an FCC crystal phase. As shown, in the above-described embodiment, a firing current 20% larger than the initial reset current (for example, 1.2 times the initial reset current) was selected as the example of FIGS. 14A and 14B. These figures also show that the reduction of the reset current is 20% greater as expected from the example of FIG. 11.

15 shows another embodiment of the present invention. As shown, in step S1510, the semiconductor memory device is baked at a predetermined temperature for a predetermined time so that the phase change material has an HCP crystal state. For example, the temperature is below the melting point of the phase change material. In this embodiment, the programmable volume and residual portion of the phase change material have the HCP crystal structure. Next, in step S1512, the firing current is applied according to the embodiment shown in FIG. 10B such that the programmable volume has the FCC determined state. The remaining portion of the phase change material remains in the HCP crystal state.

Figure 16 shows another embodiment of the present invention. The above-described embodiment achieves the firing operation by applying a current to the phase change material. As described above, when the current is applied, heat is generated. Instead of using a current to heat the phase change material, heat may be applied more directly. For example, FIG. 16 shows that in step S1610, a rapid heat treatment process is performed for the semiconductor device including the phase change memory cells. The rapid heat treatment is performed at a sufficient temperature for a sufficient time to change the phase change material to an amorphous state. For example, the temperature is higher than the melting point of the phase change material.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the present invention provides a method for significantly reducing the reset current of a phase change memory cell. In addition, there is an advantage in that the resistance difference between the set and reset states of the phase change memory cell can be increased.

Claims (30)

A method of reducing a reset current that resets a portion of a phase change material in a memory cell of a phase change memory device: Converting at least a portion of the phase change material comprising a first crystalline phase into one of a second crystalline phase and an amorphous phase, wherein the second crystalline phase transitions to an amorphous phase more easily than the first crystalline phase. A method for reducing the reset current of a phase change memory device. The method of claim 1, wherein the first crystalline phase has a hexagonal dense structure. 3. The method of claim 2, wherein said second crystalline phase has a face centered cubic structure. The method of claim 1, wherein the second crystalline phase has a face centered cubic structure. 2. The method of claim 1, wherein said converting step performs a heat treatment to convert said first crystalline phase into one of said second crystalline phase and an amorphous phase. 6. The method of claim 5, wherein the heat treatment is a rapid heat treatment at a temperature above the melting point of the phase change material to convert the first crystalline phase to an amorphous phase. 6. The method of claim 5, further comprising, after the converting step, converting at least a portion of the phase change material into the second crystalline phase. 8. The method of claim 7, wherein said converting step bakes said phase change material at a temperature below the melting point of said phase change material for a period of time. The method of claim 1, wherein said converting step applies a current to said phase change material. 10. The method of claim 9, wherein the applied current is higher than a reset current when the conversion step is not performed. 11. The method of claim 10, wherein the applied current is up to 1.1 times higher than the reset current when the conversion step is not performed. 11. The method of claim 10, wherein as the applied current increases, the reset current after the converting step decreases. 11. The method of claim 10 wherein said converting step applies a current such that said reset current after said converting step is at least 20% less than said reset current before said converting step. 11. The method of claim 10, wherein said converting step applies a current having a pulse width that converts said first crystalline phase to an amorphous phase. 11. The method of claim 10, wherein said converting step applies a current having a pulse width that converts said first crystal phase into a second crystal phase. 10. The method of claim 9, further comprising, prior to the converting step, changing portions of the phase change material that are not the first crystalline phase to the first crystalline phase. 17. The method of claim 16, wherein said changing step bakes said phase change memory device for a period of time at a temperature below the melting point of said phase change material. 17. The method of claim 16, wherein the converting step converts only a portion of the phase change material such that the remainder of the phase change material remains as the first crystalline phase. The method of claim 1, wherein the first crystal phase has a lower resistance than the second crystal phase. A method of reducing a reset current that resets a portion of a phase change material in a memory cell of a phase change memory device to an amorphous phase: Converting at least a portion of said phase change material in a mixed phase state to a single phase state. 21. The method of claim 20, wherein said converting converts at least a portion of said phase change material in a mixed crystalline state into a single phase state. 22. The method of claim 21, wherein said single phase state is amorphous. 22. The method of claim 21, wherein said single phase state is a single crystalline phase. A method of reducing a reset current that resets a portion of a phase change material in a memory cell of a phase change memory device to an amorphous phase: And applying a current to the phase change material, wherein the reset current of the phase change material after the applying step is lower than the reset current before the applying step. How to reduce. 25. The method of claim 24, wherein the applying step applies a current, wherein the set resistance of the portion of the phase change material before the applying step is lower than the set resistance of the portion of the phase change material after the applying step. How to. 25. The method of claim 24 wherein the applying step applies a current such that the margin between the set resistor and the reset resistor increases, wherein the set resistor is a resistance of a portion of the phase change material when set to a crystalline phase, A resistance of a portion of said phase change material when it is set to an amorphous phase. A method of reducing a reset current that resets a portion of a phase change material in a memory cell of a phase change memory device to an amorphous phase: And a method of performing heat treatment on the phase change memory device, wherein the reset current of the phase change material after the performing step is lower than the reset current before the performing step. How to let. delete Upper electrode; Lower electrode; And A phase change material disposed between the upper electrode and the lower electrode, the phase change material including a lower portion and a remaining portion in contact with the lower electrode, the remaining portion including at least a first crystal phase and the lower portion Has a second crystalline phase or an amorphous phase, and the second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. A method of enhancing the operation of a phase change memory device comprising at least one memory cell having a phase change material: Converting the portion of the phase change material to a face-centered cubic phase such that the energy required to change the portion of the phase change material from crystalline to amorphous is reduced.

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