CN101106174B - Method for reducing a reset current of phase change memory device - Google Patents
Method for reducing a reset current of phase change memory device Download PDFInfo
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- CN101106174B CN101106174B CN2007101041742A CN200710104174A CN101106174B CN 101106174 B CN101106174 B CN 101106174B CN 2007101041742 A CN2007101041742 A CN 2007101041742A CN 200710104174 A CN200710104174 A CN 200710104174A CN 101106174 B CN101106174 B CN 101106174B
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- G—PHYSICS
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
Abstract
The invention relates to a method for reducing a reset current for presetting a portion of a phase change material in a memort cell of a phase change memory device and the phase change memory device. At least part of the phase change material containing a first crystal phase is changed into one of crystal phase and amorphous phase. Compared with the first crystal phase, the second crystal phase is changed into amorphous phase more easily. Such as, the first crystal phase may be of hexagon closed packed structure and the first crystal phase may be of face centered cubic structure.
Description
Technical field
The present invention relates to the method and the phase change memory device of the reset current that a kind of partial phase change material of memory cell of the phase change memory device that is used for reducing resetting uses.
Background technology
Fig. 1 illustrates the prior art structure of phase-change memory cell.As shown in the figure, insulating barrier 102 under forming above the substrate 100.Form first contact hole 105 in the insulating barrier 102 down, and in first contact hole 105, forming bottom electrode 113 (being sometimes referred to as heater).Typically, bottom electrode 113 is formed by TiAlN, TiN etc.On the following insulating barrier 102 above the bottom electrode 113, form phase-change material 115.Typically, this phase-change material is such as Ge
2Sb
2Te
5Deng sulfide material.On phase-change material 115, form top electrode 119.Top electrode 119 can be formed by TiN, TaN, WN etc.Forming insulating barrier 122 above the substrate 100.In last insulating barrier 122, form second contact hole 125, with exposed portions serve top electrode 119.In second contact hole 125, form conductive plug 127.Conductive plug 127 can be formed by W, Al, Cu etc.Above last insulating barrier 122, can form the metallic pattern 129 (for example, conductor wire) that contacts with embolism 127 then.This metallic pattern can be by forming with embolism 127 identical materials.Typically, metallic pattern 129 is the bit lines of phase change memory device that comprise the phase-change memory cell of Fig. 1.
The memory cell of Fig. 1 can be programmed based on the heat that is applied to phase-change material 115.Applying of heat can be carried out through phase-change material 115 (for example, by applying electrical current to top electrode 119) by making electric current.Fig. 2 A illustrates the electric current replacement pulse and the electric current that are used for program phase-change material 115 pulse is set.Shown in Fig. 2 A, the replacement pulse is the heavy current that short cycle provides, and is the reduced-current that provides in cycle long period and pulse is set.Shown in Fig. 2 B, the replacement pulse has the effect of the resistance that increases phase-change material 115, and the effect that pulse has the resistance that reduces phase-change material 115 is set.By changing the state of phase-change material 115, cause resistance to change.It is noncrystal that the replacement pulse makes that the programmable volume (volume) of phase-change material 115 becomes, as shown in Figure 3.On the contrary, pulse being set makes the programmable volume of phase material 115 become crystal.The amorphous state of high electrical resistance is usually corresponding to the storage of logical one, and more low-resistance crystalline state is corresponding to the storage of logical zero.
In order to keep low-power consumption, wish reset current and electric current be set all lower.But, wish that also the gained resistance of the phase-change material that coming from resets operates has big as far as possible difference with respect to the phase-change material resistance after the setting operation.Usually, when reset current is reduced, reset and the resistivity difference that is provided with between the state reduces.Therefore, reach out for low be provided with and reset current between exist opposite compromise, and be provided with and replacement resistance in also keep the difference of wishing.
Summary of the invention
The invention provides the method for the reset current that a kind of partial phase change material of memory cell of the phase change memory device that is used for reducing resetting uses.
According to an embodiment, comprise that the material of partial phase change at least of first crystalline phase is changed into one of crystalline phase and amorphous phase.Compare the easier amorphous phase that changes into of second crystalline phase with first crystalline phase.For example, first crystalline phase can be hexagonal close close packed structure (hexagonal closed packedstructure), and second crystalline phase can be face-centred cubic structure (face centered cubicstructure).
In one embodiment, carry out this transformation by heat treatment.For example, can under temperature, carry out rapid thermal annealing, being amorphous phase with first crystal transition greater than the fusion temperature of phase-change material.
According to another embodiment, this heat treatment can be included under the temperature of the fusion temperature that is lower than phase-change material and cure this phase change memory device a period of time, so that be second crystalline phase with first crystal transition.
In another embodiment of the present invention, realize this conversion step by applying electrical current to phase-change material.For example, if do not carry out this conversion step, apply electric current so greater than reset current.As example more specifically,, apply electric current so and can be 1.1 times of reset current if do not carry out conversion step.In another embodiment of the present invention, after curing phase change memory device as mentioned above, carry out applying of electric current.
In another embodiment of the present invention, be single-phase state by being in the material transition of partial phase change at least of mixing phase, realize reducing of reset current.For example, the material of partial phase change at least that is in the mix-crystal phase is changed into single-phase attitude.This phase can be an amorphous phase, maybe can be the monocrystalline phase.
The invention still further relates to a kind of phase change memory device.
In one embodiment, this phase change memory device comprises top electrode, bottom electrode and the phase-change material of arranging between upper/lower electrode.This phase-change material can be single-phase fully, and this single-phase can be amorphous phase with face-centered cubic one of mutually.
In another embodiment, this phase-change material comprises bottom and the remainder that contacts with bottom electrode.This bottom can be one of first crystalline phase and amorphous phase.This remainder comprises second crystalline phase at least.Compare the easier amorphous phase that changes into of first crystalline phase with second crystalline phase.
Description of drawings
To understand the present invention more completely by detailed description given below with as just the accompanying drawing that illustration provides, wherein same reference numbers refers to the appropriate section in each accompanying drawing, and wherein:
Fig. 1 illustrates the structure of prior art phase-change memory cell.
Fig. 2 A illustrates setting and the replacement pulse that applies in the memory cell of programming Fig. 1.
Fig. 2 B illustrates owing to the pulse that applies among Fig. 2 A, the Resistance states of memory cell.
Fig. 3 illustrates the programmable volume of the phase-change material in the memory cell of Fig. 1.
What Fig. 4 illustrated before phase-change material stands sintering operation this phase-change material is provided with distribution of resistance figure.
What Fig. 5 illustrated after phase-change material stands sintering operation this phase-change material is provided with distribution of resistance figure.
Fig. 6 illustrates the flow chart of sintering method according to an embodiment of the invention.
Fig. 7 illustrates the block diagram according to phase change memory device of the present invention.
Fig. 8 illustrates the schematic diagram of the driver element of Fig. 7.
Fig. 9 illustrates the time sequential routine figure of the phase change memory device of Fig. 7.
Figure 10 A and 10B illustrate sintering current and are applied to embodiment according to phase-change material of the present invention.
The percentage that Figure 11 illustrates with respect to the reset current of the percentage variation of sintering current changes.
Figure 12 illustrates the influence of the number of sintering operation to reset current.
Figure 13 illustrates the influence of sintering operation to the resistance difference between setting and the Reset Status.
Figure 14 A and 14B illustrate and impact the object lesson of sintering to the influence of reset current.
Figure 15 diagram is according to another exemplary embodiments of sintering of the present invention.
Figure 16 illustrates the exemplary embodiments again according to sintering operation of the present invention.
Embodiment
Before the operation of the phase change memory device that adopts phase-change memory cell as shown in Figure 1, can carry out sintering operation.Sintering operation is the operation that produces heat in partial phase change material at least, so as comprise phase-change material after improve the result in the operating process.It is to reduce reset current that an example according to the present invention improves.
Fig. 4 illustrates the view of its initial setting up distribution of resistance before phase-change material stands initial sintering operation.With reference to figure 4, in scope (i), resistance value is set is distributed widely, and resistance value on average is set is high.Therefore, when read operation, defective may take place, and therefore, may reduce rate of finished products.
Fig. 5 illustrates that it is provided with the view of distribution of resistance after phase-change material stands initial sintering operation.With reference to figure 5, scope (ii) in, resistance value is set straitly and is equably distributed, and resistance value on average is set is lower than phase-change material and stands resistance value on average to be set before the initial sintering operation.For the more stable read operation of phase change memory device is provided, carry out initial sintering operation.
Just to the purpose of example, suppose that phase-change memory cell has structrual description embodiments of the invention shown in Figure 1.But, be to be understood that embodiments of the invention can use any phase-change memory cell structure.
Fig. 6 shows the flow chart of initial sintering method according to an embodiment of the invention.With reference to figure 6, according to embodiments of the invention, the initial sintering method 300 with phase change memory device of phase-change material comprises: the step 310 of selecting one of a plurality of memory array block; Enable the step 320 of the word line of selected memory cell array block continuously; And apply the step 330 of sintering current to the bit line of selected memory cell array block.Sintering current is greater than reset current, and this allows phase-change material to become Reset Status.
Fig. 7 illustrates the block diagram according to an embodiment of phase change memory device 400 of the present invention.With reference to figure 7, phase change memory device 400 comprises a plurality of memory cell array block BLK1 and BLK2 to BLKi, counter clock generation unit 410, decoding unit 420 and driver element 440.Each memory cell array block BLK1 and BLK2 to BLKi comprise phase-change memory cell as shown in Figure 1.Counter clock generation unit 410 is in response to external timing signal EXCLK and sintering mode signal XWIF, output first to the 3rd counter clock signal CCLK1, CCLK2 and CCLK3, wherein first to the 3rd counter clock signal CCLK1, CCLK2 have the different cycles with CCLK3.
Below with reference to Fig. 6 and 7 phase change memory device and initial sintering method according to the embodiment of the invention are described.Memory cell array block BLK1 in the phase change memory device 400 and BLK2 to BLKi comprise a plurality of phase-change memory cell (not shown).Counter clock generation unit 410 is in response to external timing signal EXCLK and sintering mode signal XWIF, output first to the 3rd counter clock signal CCLK1, CCLK2 and CCLK3, wherein first to the 3rd counter clock signal CCLK1, CCLK2 have the different cycles with CCLK3.
When carrying out initial sintering operation, import external timing signal EXCLK from the outside, have the clock signal of one-period, and only under initial sintering pattern, activating.When phase change memory device 400 is in initial sintering pattern, produce sintering mode signal XWIF.
Counter clock generation unit 410 comprises a plurality of counters.The output of counter is decoded, with select storage unit array block BLK1 and BLK2 to BLKi continuously, so that can carry out initial sintering operation.
Counter clock generation unit 410 comprises first to n linage-counter RC1 and RC2 to RCn, redundant counter RDDC and first to m counter CC1 and CC2 to CCm.
First to n linage-counter RC1 and RC2 to RCn are switched in response to sintering mode signal XWIF or end, and in response to external timing signal EXCLK, produce first to n linage-counter clock signal RCCLK1 and RCCLK2 to RCCLKn, wherein first to n linage-counter clock signal RCCLK1 and RCCLK2 to RCCLKn constitute the first counter clock signal CCLK1.
Redundant counter RDDC is switched in response to sintering mode signal XWIF or ends, and produces the second counter clock signal CCLK2 in response to external timing signal EXCLK.First to m column counter CC1 and CC2 to CCm are switched in response to sintering mode signal XWIF or end, and in response to external timing signal EXCLK, produce first to m column counter clock signal C CCLK1 and CCCLK2 to CCCLKm, wherein first to m column counter clock signal C CCLK1 and CCCLK2 to CCCLKm constitute the 3rd counter clock signal CCLK3.
Second to n linage-counter RC2 to RCn operated continuously in response to the carry instruction C from the output of previous row counter.Redundant counter RDCC operates in response to the carry instruction C that exports from n linage-counter RCn.The first column counter CC1 operates in response to the carry instruction C that exports from redundant counter RDDC.Second to n column counter CC2 to CCm operated continuously in response to the carry instruction C from last column counter output.
Below with reference to the sequential chart of Fig. 9, describe the operation of counter clock generation unit 410 in detail.Fig. 9 illustrates the time sequential routine figure of the phase change memory device of Fig. 7.
First to n linage-counter RC1 and RC2 to RCn, redundant counter RDDC and first to m column counter CC1 and CC2 to CCm carry out their counting operation in response to external timing signal EXCLK and sintering mode signal XWIF.If sintering mode signal XWIF is under an embargo, the counter of counter clock generation unit 410 also is cut off so.In addition, the second linage-counter RC2 operates in response to the carry instruction C that is produced by the first linage-counter RC1.The third line counter RC3 operates in response to the carry instruction C that is produced by the second linage-counter RC2.Redundant counter RDDC operates in response to the carry instruction C that is produced by n linage-counter RCn.The first column counter CC1 operates in response to the carry instruction C that is produced by redundant counter RDDC.Similarly, m column counter CCm operates in response to the carry instruction C that is produced by (m-1) individual column counter (not shown).In this way, the counter of counter clock generation unit 410 is operated continuously.
As shown in Figure 9, doubled continuously from the signal period that the counter of counter clock generation unit 410 produces.That is, doubled continuously from first to n linage-counter clock signal RCCLK1 of first to n linage-counter RC1 and RC2 to RCn output and the cycle of RCCLK2 to RCCLKn.Reach the twice of exporting n linage-counter clock signal RCCLKn from n linage-counter RCn from the cycle of the second counter clock signal CCLK2 of redundant counter RDDC output.Reach from the twice of the second counter clock signal CCLK2 of redundant counter RDDC output from the cycle of the first column counter clock signal C CCLK1 of first column counter CC1 output.Similarly, the cycle of second to m counter clock signal CCCLK2 to CCCLKm is doubled continuously.Thus, produce first to the 3rd counter clock signal CCLK1, CCLK2 and CCLK3 continuously.First to the 3rd counter clock signal CCLK1, CCLK2 and CCLK3 are imported into decoding unit 420.
Decoding unit 420, in response to first to the 3rd counter clock signal CCLK1, CCLK2 and CCLK3, the block address BLKADD of one of a plurality of memory cell array block BLK1 and BLK2 to BLKi, the wordline address WLADD of word line that enables selected memory cell array block and the redundant word line address REDADD that enables the redundant word line of selected memory cell array block are selected in output.Decoding unit 420 comprises row decoder 425, redundant decoder 430 and column decoder 435.Row decoder 425 output wordline address WLADD, wordline address WLADD is enabled continuously in response to the first counter clock signal.That is, row decoder 425 receptions and first to n linage-counter clock signal RCCLK1 and the RCCLK2 to RCCLKn that decode with different cycles, and export this decoded result as wordline address WLADD.Wordline address WLADD enables the word line of selected memory cell array block continuously from least significant bit to highest significant position.
Fig. 8 only illustrates the first memory cell array block BLK1 with (k+1) word line, (p+1) bit line and a redundant word line WLred.
When initial sintering operation, the first memory cell array block BLK1 is automatically selected by block address BLKADD.The row decoder 425 output wordline address WLADD of receive clock signal CCLK1 are to enable word line WL0 and the WL1 to WLk of the first memory cell array block BLK1 continuously.That is, the first word line WL0 is at first enabled.Driver element 440 applies bit line BL0 and the BL1 to BLp of sintering current IFC to the first memory cell array block BLK1.On the phase-change material of the memory cell that is connected to the first word line WL0, carry out initial sintering operation then.
Next, the first word line WL0 is under an embargo and the second word line WL1 is activated.On the phase-change material of the memory cell that is connected to the second word line WL0, carry out initial sintering operation then.Similarly, on the phase-change material of the memory cell that is connected to k word line WLk and redundant word line WLred, carry out initial sintering operation.As a result, finish initial sintering operation on first memory cell array block.Because first to n linage-counter RC1 of counter clock generation unit 410 and RC2 to RCn and redundant counter RDDC are operated continuously, exporting first to n linage-counter clock signal RCCLK1 and RCCLK2 to RCCLKn and the second counter clock signal CCLK2 continuously, first to k word line WL0 and WL1 to WLk and redundant word line WLred are enabled continuously.
If redundant word line WLred is under an embargo, column decoder 435 passes through the operation of first to m column counter CC1 and CC2 to CCm so, IOB address BLKADD, and block address BLKADD selects the second memory cell array block BLK2.These can be seen in the sequential chart of Fig. 9.If the second memory cell array block BLK2 is selected, first to n word line (not shown) and redundant word line (not shown) are enabled continuously so, and carry out sintering operation.
Sintering voltage VPP can be equal to or higher than supply voltage.Consider the number of the memory cell array of connection, voltage level can be increased or reduce.Below will be with respect to the more detailed argumentation sintering of further embodiment of the present invention voltage VPP.Also will discuss sintering current IFC in more detail below with respect to further embodiment of the present invention greater than reset current.
In phase change memory device 400 according to the present invention, because external input signal is reduced to external timing signal EXCLK, sintering mode signal XWIF, sintering voltage VPP, supply voltage and ground voltage, therefore can test a large amount of chips on the wafer simultaneously.
The present inventor finds that phase-change material is the mixture of intensive (HCP) crystal structure of hexagonal close and face-centered cubic (FCC) crystal structure when being in crystalline state.The FCC crystal structure is compared with the HCP crystal structure, and the high electrical resistance of high approximately two orders of magnitude is provided.But this inventor finds, is amorphous phase and the FCC crystal structure transition is compared for the amorphous phase energy needed with the HCP crystal structure transition, needs bigger energy.In other words, compare with HCP, the FCC state is a better crystalline state-to the transition state of-amorphous, change amorphous state because the FCC state is easier into from crystalline state.
The inventor finds that further by applying sufficiently high sintering current or temperature, phase-change material or its part (for example, programmable volume) can be changed into amorphous phase or FCC crystalline phase.In addition, the inventor finds that after this sintering, when being provided with, the programmable volume of phase-change material will obtain the FCC crystalline state.As a result, the inventor finds that further by correctly selecting sintering current, they can reduce to obtain the reset current that Reset Status needs.This sintering also reduces the resistance of the state that is provided with, and still with comparing that sintering exists before, provides bigger surplus between setting and replacement resistance.
Figure 10 A illustrates an embodiment of the sintering current that applies according to the present invention.Applying of sintering current can be carried out as above-mentioned embodiment.As shown in the figure, after sintering, by applying higher current impulse, phase-change material becomes amorphous phase.Shown in Figure 10 A was further, these caused required reset current more much lower in the operating process in future.
Figure 10 B illustrates another embodiment of the present invention.In this embodiment, apply same high sintering current, then along with the time progressively reduces.Because this sintering operation, phase-change material becomes the FCC crystalline state of high resistant.But, obtain same effect, that is, obtain same low reset current and the low resistance states that is provided with.
Figure 11 further illustrates the influence of sintering current to reset current.More specifically, with respect to initial presintering reset current, the figure shows the percentage increase of the percentage minimizing of reset current with respect to sintering current.Here, the replacement pulse duration was set as for 500 nanoseconds, and is consistent with the embodiment of Figure 10 A.That is sintering makes phase-change material obtain amorphous phase.As shown in the figure, be higher than initial presintering reset current because reset current increases to, back sintering reset current reduces.More specifically, be added to 10% to 20% times of initial reset current (for example, initial reset current 1.1 to 1.2 times) or when above, the reset current of acquisition significantly reduces when sintering current.
Figure 12 illustrates the influence of sintering number to reset current.For sintering current greater than initial presintering reset current 20% (for example, the 1.2. of initial reset current is doubly), and the pulse duration of 500 nanoseconds (after sintering, obtaining amorphous phase), Figure 12 diagram is for the variation of the reset current of a large amount of this sintering.As shown in the figure, this figure illustrates a plurality of sintering that reset current do not carried out widely influences.
Figure 13 diagram sintering according to the present invention is to the influence of the resistance surplus between setting and the Reset Status.The left side of Figure 13 illustrates the distribution of resistance that is used for the replacement before the sintering and state is set.The right diagram of Figure 13 be used for the replacement after the sintering and the distribution of resistance of state be set.As shown in figure 13, before sintering, the setting and the distribution of resetting are overlapping basically.As a result, blemish may take place.On the contrary, after sintering, between setting and replacement distribution, have much bigger surplus, so that the number of blemish reduces significantly.
Figure 14 A and 14B illustrate improved two the example situations that come from according to sintering circuit of the present invention.Figure 14 A illustrates the situation of the sintering that obtains amorphous phase, and Figure 14 A illustrates the situation of the sintering that obtains the FCC crystalline state.As shown in the figure, in this exemplary embodiments, be selected for the example of Figure 14 A and 14B greater than the sintering current of initial reset current 20% (for example, 1.2 times of initial reset currents).These figure further show, by checking that Figure 11 will anticipate reducing greater than 20% of reset current.
Figure 15 diagram according to another embodiment of the present invention.As shown in the figure, in step S1510, under a temperature, cure semiconductor memory a period of time, so that phase-change material obtains the HCP crystalline state.For example, this temperature is lower than the fusion temperature of phase-change material.In this embodiment, the programmable volume of phase-change material and remainder obtain the HCP crystalline state.Next, in step S1512, apply sintering current, so that programmable volume obtains the FCC crystalline state according to the embodiment shown in Figure 10 B.The remainder that should be appreciated that phase-change material keeps the HCP crystalline state.
Figure 16 illustrates another embodiment of the present invention.Last embodiment obtains sintering operation by applying electrical current to phase-change material.As discussed previously, applying of electric current obtains applying of heat.Replace using electric current, apply heat to phase-change material, heat can more directly be applied.For example, Figure 16 shows, in step S1610, carries out the rapid thermal annealing operation on the semiconductor device of phase-change memory cell comprising.This rapid thermal annealing carries out under enough temperature, and carries out time enough, so that phase-change material is changed into amorphous state.For example, this temperature is greater than the fusion temperature of phase-change material.
As mentioned above, the invention provides a kind of method for reducing significantly the reset current that phase-change memory cell uses. In addition, the invention provides a kind of setting of phase-change memory cell and attendant advantages of the resistance difference between the Reset Status of increasing.
Describe the present invention at this, obviously can change the present invention with various ways. These changes do not allow to be considered to deviate from the present invention, and all these improvement are confirmed as comprising within the scope of the invention.
Claims (25)
1. method that is used to reduce reset current, the partial phase change material in the memory cell of this reset current replacement phase change memory device, this method comprises:
Carrying out sintering operation, is one of second crystalline phase and amorphous phase with the material transition of partial phase change at least that will comprise first crystalline phase, compares the easier amorphous phase that changes into of second crystalline phase with first crystalline phase; And
Apply reset current, this reset current is used for the partial phase change material of resetting after the step of carrying out sintering operation.
2. according to the process of claim 1 wherein that first crystalline phase has the hexagonal close close packed structure.
3. according to the method for claim 2, wherein second crystalline phase has face-centred cubic structure.
4. according to the process of claim 1 wherein that second crystalline phase has face-centred cubic structure.
5. according to the process of claim 1 wherein that this sintering operation carries out heat treatment, being one of second crystalline phase and amorphous phase with first crystal transition.
6. according to the method for claim 5, wherein this heat treatment is greater than the rapid thermal annealing under the temperature of the fusion temperature of phase-change material, being amorphous phase with first crystal transition.
7. according to the method for claim 5, wherein, before this sintering operation, this method comprises:
Near small part phase-change material changes first crystalline phase into.
8. according to the method for claim 7, this step that wherein near small part phase-change material changes first crystalline phase into is cured this phase change memory device a period of time under the temperature of the fusion temperature that is lower than phase-change material.
9. according to the process of claim 1 wherein that this sintering operation applies electrical current to phase-change material.
10. according to the method for claim 9, the initial reset current that the electric current that wherein applies applies when also not carrying out this sintering operation.
11. the method for claim 10, the electric current that wherein applies is more than or equal to 1.1 times of reset current when also not carrying out sintering operation.
12. according to the method for claim 10, wherein when the electric current that applies increased, the reset current after this sintering operation reduced.
13. according to the method for claim 10, wherein this sintering operation applies electric current, so that the reset current after this conversion step is less than the reset current at least 20% before this conversion step.
14. according to the method for claim 10, wherein this sintering operation applies the electric current with a pulse duration, so that first crystal transition is an amorphous phase.
15. according to the method for claim 10, wherein this sintering operation applies the electric current with a pulse duration, so that first crystal transition is second crystalline phase.
16. according to the method for claim 9, before this sintering operation, wherein, this phase-change material is first crystalline phase.
17. according to the method for claim 16, wherein before this sintering operation, this method comprises:
Under the temperature of the fusion temperature that is lower than phase-change material, cure this phase change memory device a period of time.
18. according to the method for claim 16, wherein this sintering operation only changes the partial phase change material, so that the remainder of phase-change material keeps first crystalline phase.
19. according to the process of claim 1 wherein that first crystalline phase has the resistance that is lower than second crystalline phase.
20. a method that is used to reduce reset current, the partial phase change material in the memory cell of this reset current replacement phase change memory device, this method comprises:
Carrying out sintering operation, is single-phase state will be in the material transition of partial phase change at least of mixing phase; And
Apply reset current, this reset current is used for the partial phase change material of resetting after the step of carrying out sintering operation.
21. according to the method for claim 20, wherein this single-phase attitude is an amorphous phase.
22. according to the method for claim 20, wherein this single-phase attitude is the monocrystalline phase.
The partial phase change material of the memory cell of phase change memory device is an amorphous phase 23. a method that reduces reset current, this reset current are used for resetting, and this method comprises:
Apply sintering current to phase-change material; And
Apply reset current, this reset current is used for the partial phase change material of resetting after applying the step of sintering current,
Wherein, at the reset current that applies phase-change material after the sintering current step less than the reset current before applying the sintering current step.
The partial phase change material of the memory cell of phase change memory device is an amorphous phase 24. a method that reduces reset current, this reset current are used for resetting, and comprising:
On phase change memory device, carry out heat treatment;
Apply reset current, this reset current is used for the partial phase change material of resetting after carrying out heat treated step,
Wherein, after carrying out heat treatment step the reset current of phase-change material less than the reset current before the execution in step heat treatment.
25. a method that improves the operation phase change memory device, this phase change memory device comprises a memory cell with phase-change material at least, and this method comprises:
Phase-change material is carried out sintering operation, is the energy that amorphous phase needs so that reduce the partial phase change material from crystal transition;
Apply reset current, this reset current is used for the partial phase change material of resetting after this sintering operation.
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| JP2010020811A (en) * | 2008-07-08 | 2010-01-28 | Toshiba Corp | Semiconductor memory device |
| JP4846813B2 (en) | 2009-03-12 | 2011-12-28 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| CN105869671B (en) * | 2016-03-25 | 2018-09-25 | 中国科学院上海微系统与信息技术研究所 | Phase-changing memory unit write initial method and its array write initial method |
| CN110797064A (en) * | 2019-10-31 | 2020-02-14 | 重庆邮电大学 | Low-power-consumption phase change memory initialization operation method |
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| CN1670979A (en) * | 2004-03-18 | 2005-09-21 | 国际商业机器公司 | Phase change memory cell on silicon-on insulator substrate |
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| US5414271A (en) * | 1991-01-18 | 1995-05-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements having improved set resistance stability |
| US5596522A (en) * | 1991-01-18 | 1997-01-21 | Energy Conversion Devices, Inc. | Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements |
| CN1670979A (en) * | 2004-03-18 | 2005-09-21 | 国际商业机器公司 | Phase change memory cell on silicon-on insulator substrate |
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