JP2007323800A - Method for reducing reset current for resetting a portion of phase transition material in memory cell of phase transition memory device, and phase transition memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for reducing a reset current of a memory cell of a phase transition memory device. <P>SOLUTION: This method comprises that at least a portion of the phase transition material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase easier than the first crystalline phase. For example, the first crystalline phase can be formed to a hexagonal closed packed structure, and the second crystalline phase can be formed to a face-centered cubic structure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for reducing a reset current for resetting a part of a phase change material in a memory cell of a phase change memory device, and a phase change memory device. MATERIAL IN A MEMORY CELL OF A PHASE CHANGE MEMORY DEVICE AND THE THE PHASE CHANGE MEMORY DEVICE).

FIG. 1 is a diagram illustrating a structure of a conventional phase change memory cell. As illustrated, a lower insulating layer 102 is formed on the substrate 100. The first contact hole 105 is formed in the lower insulating layer 102, and the lower electrode 113 (which may be a heater) is formed in the first contact hole 105. Usually, the lower electrode 113 is made of TiAlN, TiN or the like. The phase change material 115 is formed on the lower insulating layer 102 on the lower electrode 113. Usually, the phase change material is a chalcogenide such as Ge ₂ Sb ₂ Te ₅ . An upper electrode 119 is formed on the phase change material 115. The upper electrode 119 can be formed from TiN, TaN, WN, or the like. An upper insulating layer 122 is formed on the substrate 100. The second contact hole 125 is formed in the upper insulating layer 122 to expose a part of the upper electrode 119. The conductive plug 127 is formed in the second contact hole 125. The conductive plug 127 can be formed of W, Al, Cu or the like. A metal pattern 129 (eg, a conductive line) may be formed on the upper insulating layer 122 that is then in contact with the plug 127. The metal pattern can be formed of the same material as the plug 127. Typically, the metal pattern 129 is a bit line of a phase change memory device having the phase change memory cell of FIG.

  The memory cell of FIG. 1 can be programmed by applying heat to the phase change material 115. The application of heat can be performed by passing a current through phase change material 115 (eg, by applying a current to top electrode 119). FIG. 2A is a diagram illustrating a current reset pulse and a current set pulse for programming the phase change material 115. As shown in FIG. 2A, the reset pulse is a high current supplied for a short time, while the set pulse is a low current supplied for a long time. As shown in FIG. 2B, the reset pulse has the effect of increasing the resistance of the phase change material 115, while the set pulse has the effect of reducing the resistance of the phase change material 115. The change in resistance is caused only by a change in the state of the phase change material 115. The reset pulse causes the programmable volume of the phase change material to become amorphous as shown in FIG. In contrast, the set pulse causes the programmable volume of phase change material 115 to become crystalline. The higher resistance amorphous state generally corresponds to storage of logic “1”, and the lower resistance crystalline state corresponds to storage of logic “0”.

  In order to maintain low power consumption, it is preferable to relatively reduce both the reset current and the set current. However, it is preferable that the resistance of the phase change material as a result of the reset operation has as large a difference as possible with respect to the resistance of the phase change material after the setting operation. Generally, as the reset current is reduced, the resistance difference between the reset and set states is reduced. Thus, a good difference in set and reset resistance will be maintained at the expense of obtaining a low set and reset current.

Patent Document 1 discloses a method capable of improving the speed of a set program operation for changing a phase change material to a crystalline state.
US Patent Application Publication No. 2005/0029502

  A technical problem to be solved by the present invention is to provide a method for reducing a reset current of a phase change memory cell.

  Another technical problem to be solved by the present invention is to provide a phase change memory device suitable for reducing a reset current of a phase change memory cell.

  The present invention provides a method and a phase change memory device for reducing a reset current for resetting a part of a phase change material in a memory cell of a phase change memory device. The method includes converting at least a portion of a phase change material including a first crystalline phase into one of a second crystalline phase and an amorphous phase. The second crystal phase transitions to the amorphous phase more easily than the first crystal phase. For example, the first crystal phase can have a hexagonal close-packed structure, and the second crystal phase can have a face-centered cubic structure.

  In one embodiment, the conversion is performed via a heat treatment. For example, rapid thermal annealing (RTA) at a temperature higher than the melting point of the phase change material can be performed to convert the first crystalline phase into an amorphous phase.

  According to another embodiment, the heat treatment can include baking the phase change memory device for a predetermined period of time at a temperature below the melting point of the phase change material to convert the first crystalline phase to the second crystalline phase.

  In other embodiments of the invention, the conversion step can be accomplished by applying a current to the phase change material. For example, if the conversion stage is not performed, the applied current is greater than the reset current. As a more detailed example, if the conversion step is not performed, the applied current can be 1.1 times the reset current. In other embodiments of the invention, the application of current is performed after baking of the phase change memory device as described above.

  In another embodiment of the present invention, the reset current reduction is obtained by converting at least a portion of the mixed phase state phase change material to a single phase state. For example, at least a portion of the mixed crystalline phase state phase change material is changed to a single phase state. The phase state can be an amorphous phase and can be a single crystal phase.

  The invention further relates to a phase change memory device.

  In one embodiment, the phase change memory device includes a phase change material disposed between an upper electrode, a lower electrode, and an upper / lower electrode. The phase change material can generally be a single phase, and the single phase can be one of an amorphous phase and a face centered cubic structure phase.

  In one embodiment, the phase change material includes a lower portion in contact with the lower electrode and a remaining portion. The lower part may be one of a first crystalline phase and an amorphous phase. The remaining portion includes at least the second crystal phase. The first crystal phase transitions to the amorphous phase more easily than the second crystal phase.

  The present invention provides a method for significantly reducing the reset current of a phase change memory cell. Further, there is an advantage that the resistance difference between the set state and the reset state of the phase change memory cell can be increased.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. Rather, the embodiments introduced herein are provided to demonstrate that the disclosed invention has been completed and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification.

  Before the operation of the phase change memory device employing the phase change memory cell as shown in FIG. 1, a firing operation can be performed. The firing operation is an operation that generates heat in at least a portion of the phase change material so that improved results are obtained in subsequent operations involving the phase change material. One improvement in the present invention is reduced reset current.

  FIG. 4 is a diagram for explaining the set resistance distribution of the phase change material before the initial firing. Referring to FIG. 4, in the region i, the set resistance values are widely distributed and the average set resistance value is high. Therefore, errors may occur during the interpretation work, thereby reducing efficiency.

  FIG. 5 is a diagram for explaining the set resistance distribution of the phase change material after the initial firing. Referring to FIG. 5, in the region ii, the set resistance values are uniformly distributed over a narrow width, and the average set resistance value is lower than that of the phase change material before the initial firing is performed. The initial firing operation is performed to provide a more stable reading operation for the phase change memory device.

  For purposes of illustration, embodiments of the present invention will be described assuming that the phase change memory cell has the structure shown in FIG. However, one skilled in the art will appreciate that other phase change memory cell structures may be used as embodiments of the present invention.

  FIG. 6 is a flowchart illustrating an initial firing method according to an embodiment of the present invention. Referring to FIG. 6, an initial firing method 300 of a phase change memory device having a phase change material according to an embodiment of the present invention includes a step 310 of selecting one of a plurality of memory array blocks, a selected memory array. Sequentially enabling 320 the word lines of the block and applying a firing current 330 to the bit lines of the selected memory cell array block. The firing current is greater than the reset current so that the phase change material is in a reset state.

  FIG. 7 is a block diagram illustrating one embodiment of a phase change memory device 400 according to the present invention. Referring to FIG. 7, the phase change memory device 400 includes a plurality of memory cell array blocks BLK1, BLK2-BLKi, a counter clock generator 410, a decoding unit 420, and a driving unit 440. Each memory cell array block BLK1, BLK2-BLKi includes phase change memory cells as shown in FIG. The counter clock generator 410 outputs first to third counter clock signals CCLK1, CCLK2, and CCLK3 in response to the external clock signal EXCLK and the firing mode signal XWIF. The first to third counter clock signals CCLK1, CCLK2, and CCLK3 have different periods.

  The decoding unit 420 is responsive to the first to third counter clock signals CCLK1, CCLK2, and CCLK3 to select one of the plurality of memory cell array blocks BLK1, BLK2 to BLKi, the block address BLKADD, and the selected memory cell array. A word line address WLADD for enabling the word line of the block and a redundant word line address REDADD for enabling the redundant word line of the selected memory cell array block are output.

  The driving unit 440 applies a firing current IFC to the memory cell array blocks BLK1, BLK2 to BLKi in response to the firing mode signal XWIF.

  A phase change memory device and an initial firing method according to an embodiment of the present invention can be described with reference to FIGS. Memory cell array blocks BLK1, BLK2-BLKi in phase change memory device 400 include a plurality of phase change memory cells (not shown). The counter clock generator 410 outputs first to third counter clock signals CCLK1, CCLK2, and CCLK3 in response to the external clock signal EXCLK and the firing mode signal XWIF. The first to third counter clock signals CCLK1, CCLK2, and CCLK3 have different periods.

  The external clock signal EXCLK having a clock signal period is input from the outside and activated only in the initial firing mode when the initial firing operation is executed. The firing mode signal XWIF is generated when the phase change memory device 400 is in the initial firing mode.

  The counter clock generation unit 410 includes a plurality of counters. The output of the counter is decoded so as to sequentially select the memory cell array blocks BLK1, BLK2 to BLKi so that an initial firing operation can be performed.

  The counter clock generator 410 includes first to n-th row counters RC1, RC2-RCn, a redundant counter RDDC, and first to m-th column counters CC1, CC2-CCm.

  The first through n-th row counters RC1, RC2-RCn are turned on or off in response to the firing mode signal XWIF, and the first through n-th row counter clock signals RCCLK1, RCCLK2- in response to the external clock signal EXCLK. Generate RCCLKn. The first through Nth row counter clock signals RCCLK1 and RCCLK2 to RCCLKn constitute a first counter clock signal CCLK1.

  The redundant counter RDDC is turned on or off in response to the firing mode signal XWIF, and generates the second counter clock signal CCLK2 in response to the external clock signal EXCLK. The first through m-th column counters CC1, CC2-CCm are turned on or off in response to the firing mode signal XWIF, and the first through m-th column counter clock signals CCCLK1, CCCLK2-CCCLKm in response to the external clock signal EXCLK. The first to m-th column counter clock signals CCCLK1, CCCLK2 to CCCLKm constitute a third counter clock signal CCLK3.

  The second to n-th row counters RC2 to RCn sequentially operate in response to the carry C output from the previous row counter. The redundant counter RDDC operates in response to the carry C output from the nth row counter RCn. The first column counter CC1 operates in response to the carry C output from the redundant counter RDDC. The second to m-th column counters CC2 to CCm are sequentially operated in response to the carry C output from the previous column counter.

  The operation of the counter clock generation unit 410 will be described in detail with reference to the timing chart of FIG. FIG. 9 is a timing diagram illustrating the operation of the phase change memory device of FIG.

  The first to n-th row counters RC1, RC2-RCn, the redundant counter RDDC, and the first to m-th column counters CC1, CC2-CCm are self-counting in response to the external clock signal EXCLK and the firing mode signal XWIF. Execute. When the firing mode signal XWIF is disabled, the counter of the counter clock generator 410 is also turned off. The second row counter RC2 operates in response to the carry C generated by the first row counter RC1. The third row counter RC3 operates in response to the carry C generated by the second row counter RC2. The redundant counter RDDC operates in response to the carry C generated by the n row counter RCn. The first column counter CC1 is operated in response to the carry C generated by the redundant counter RDDC. Similarly, the m-th column counter CCm operates in response to a carry C generated by an m-1 column counter (not shown). With this method, the counter of the counter clock generator 410 operates sequentially.

  As shown in FIG. 9, the cycle of the signal generated from the counter of the counter clock generator 410 sequentially increases by a factor of two. That is, the first to n-th row counter clock signals RCCLK1 and RCCLK2 to RCCLKn output from the first to n-th row counters RC1 and RC2 to RCn sequentially increase by a factor of two. The cycle of the second counter clock signal CCLK2 output from the redundant counter RDDC is twice the cycle of the nth row counter clock signal RCCLKn output from the nth row counter RCn. The cycle of the first column counter clock signal CCCLK1 output from the first column counter CC1 is twice the cycle of the second counter clock signal CCLK2 output from the redundant counter RDDC. Similarly, the period of the second to m-th counter clock signals CCCLK2 to CCCLKm sequentially increases by a factor of two. Accordingly, the first to third counter clock signals CCLK1, CCLK2, and CCLK3 are sequentially generated. The first to third counter clock signals CCLK1, CCLK2, and CCLK3 are input to the decoding unit 420.

  The decoding unit 420 is responsive to the first to third counter clock signals CCLK1, CCLK2, and CCLK3 to select one of the plurality of memory cell array blocks BLK1, BLK2 to BLKi, the block address BLKADD, and the selected memory cell array. A word line address WLADD for enabling the word line of the block and a redundant word line address REDADD for enabling the redundant word line of the selected memory cell array block are output. The decoding unit 420 includes a row decoder 425, a redundant decoder 430, and a column decoder 435. The row decoder 425 outputs the word line address WLADD, which are sequentially enabled in response to the first counter clock signal CCLK1. That is, the row decoder 425 receives and decodes the first to n-th row counter clock signals RCCLK1 and RCCLK2 to RCCLKn having different periods, and then outputs the decoding result as the word line address WLADD. The word line address WLADD enables the word lines of the selected memory cell array block sequentially from the most significant bit to the least significant bit.

  The redundant decoder 425 outputs a redundant word line address REDADD in response to the second counter clock signal CCLK2. The column decoder 435 outputs a block address BLKADD, which selects one of the plurality of memory cell array blocks BLK1, BLK2 to BLKi in response to the third counter clock signal CCLK3. The column counter 435 receives and decodes the first to m-th column counter clock signals CCCLK1 and CCCLK2 to CCCLKm having different periods, and then outputs a decoding result as a block address BLKADD. The block address BLKADD enables all the bit lines of the selected memory cell array block. There are various structures of the decoding unit 420 that receives and decodes the clock signal output from the counter clock generation unit 410.

  The driving unit 440 applies a firing current IFC to the memory cell array blocks BLK1, BLK2 to BLKi in response to the firing mode signal XWIF. The operation of the drive unit 440 will be described with reference to FIG. FIG. 8 is a diagram illustrating the drive unit 440 of FIG. Referring to FIG. 8, the driving unit 440 has a first terminal connected to the firing voltage VPP, a second terminal connected to the bit lines BL0 and BL1 to BLp of the memory cell array block, and a gate connected to the firing mode signal XWIF. A plurality of transistors TR1 to TRl. The transistors TR1 to TRl have an appropriate size capable of applying a firing current IFC to the bit lines BL0 and BL1 to BLp.

  FIG. 8 is a diagram illustrating only the first memory cell array block BLK1 including k + 1 word lines, p + 1 bit lines, and one redundant word line WLred.

  The block address BLKADD automatically selects the first memory cell array block BLK1 at the beginning of the firing operation. Then, the row decoder 425 receiving the first counter clock signal CCLK1 outputs the word line address WLADD to sequentially enable the word lines WL0, WL1 to WLk of the first memory cell array block BLK1. That is, the first word line WL0 is first enabled. The driving unit 440 applies a firing current IFC to the bit lines BL0 and BL1 to BLp of the first memory cell array block BLK1. Thereafter, an initial firing operation is performed on the phase change material of the memory cell array connected to the first word line WL0.

  Next, the first word line WL0 is disabled and the second word line WL1 is enabled. Thereafter, an initial firing operation is performed on the phase change material of the memory cell array connected to the second word line WL1. In this manner, the initial firing operation is performed on the phase change material of the memory cell array connected to the kth word line WLk and the redundant word line WLred. Then, the initial firing operation of the first memory cell array block BLK1 is completed. The first through n-th row counters RC1, RC2-RCn and the redundant counter RDDC of the counter clock generator 410 are sequentially operated to sequentially operate through the first through n-th row counter clocks RCCLK1, RCCLK2-RCCLKn, and the second counter clock CCLK2. Therefore, the first to kth word lines WL0, WL1 to WLk and the redundant word line WLred are sequentially enabled.

  When the redundant word line WLred is disabled, the column decoder 435 outputs the block address BLKADD by the operation of the first to mth column counters CC1, CC2 to CCm, and the block address BLKADD selects the second memory cell array block BLK2. To do. This can be seen from the timing diagram of FIG. When the second memory cell array block BLK2 is selected, first to nth word lines (not shown) and redundant word lines (not shown) are sequentially enabled to perform a firing operation.

  The firing voltage VPP has a voltage level equal to or greater than the power supply voltage level. The voltage level can be further increased or decreased in consideration of the number of memory cell arrays connected. The firing voltage VPP will be described in more detail in another embodiment of the present invention. The firing current IFC is larger than the reset current, and will be described in more detail in another embodiment of the present invention.

  The driving unit 440 further controls the control unit 510 to control the firing current IFC to be applied only to the bit line of the phase change memory cell array selected by the block address BLKADD in response to the block address BLKADD and the firing mode signal XWIF. Can be provided. That is, by allowing the firing current IFC to be applied only by the selected memory cell array block, a more accurate firing operation can be performed. The control unit 510 can be a NAND gate. That is, only when both the block address BLKADD and the firing mode signal XWIF are enabled to a high level, the output of the NAND gate becomes a low level and turns on the transistors TR1 to TRl. The transistors TR1 to TRl are shown as PMOS transistors, but are not limited thereto.

  The phase change memory device 400 according to the embodiment of the present invention minimizes an externally input signal to an external clock signal EXCLK, a firing mode signal XWIF, a firing voltage VPP, a power supply voltage, a ground voltage, and the like. A large number of chips on one wafer can be tested at a time.

  The inventors have found that in the crystalline phase state, the phase change material is a mixture of a hexagonal close-packed (HCP) crystal structure and a face-centered cubic (FCC) crystal structure. The FCC crystal structure provides a greater resistance at approximately the square magnitude than the HCP crystal structure. However, the present inventor has found that more energy is required to convert the HCP crystal structure to the amorphous phase than is necessary to convert the FCC crystal structure to the amorphous phase. In the other methods described above, the FCC state is more suitable in the crystal-amorphous transition than HCP because the FCC state easily transitions from the crystalline state to the amorphous state.

  In addition, the present inventor has confirmed that, by applying a sufficiently high firing current or temperature, the phase change material or a part thereof (for example, a programmable volume) is changed to an amorphous or FCC crystalline phase. I found it. The inventor then found that after such firing, the programmable volume of the phase change material was in the FCC crystalline state at the set time. As a result, the present inventors have found that the reset current required to fulfill the reset state can be reduced by appropriately selecting the firing current. Such firing also reduces the resistance of the set state, but provides a larger margin between the set and reset resistance than exists before firing.

  FIG. 10A is a diagram illustrating one embodiment of a firing current applied by the present invention. The application of the firing current can be performed in the same manner as in the above-described embodiment. As shown, by applying a relatively high current pulse, the phase change material is converted to an amorphous phase after firing. As shown in FIG. 10A, this results in a lower reset current required in the next operation.

  FIG. 10B is a diagram showing still another embodiment of the present invention. In this embodiment, the same high firing current is applied, and then gradually a lower current is applied. As a result of such firing operation, the phase change material is converted to a high resistance FCC crystal state, but the same effect is obtained. That is, the same low reset current and low set resistance state can be obtained.

  FIG. 11 is a diagram illustrating the effect of the firing current on the reset current. In particular, this shows a decrease in the ratio of the reset current to an increase in the ratio of the firing current to the initial pre-firing reset current. Here, the width of the reset pulse is set at 500 nanoseconds, which is consistent with the embodiment of FIG. 10A. That is, firing causes the phase change material to become an amorphous phase. As shown in the figure, the post-firing reset current decreases as the reset current increases higher than the initial pre-firing reset current. In particular, if the firing current increases to 10% to 20% of the initial reset current (eg, 1.1 to 1.2 times the initial reset current) or more, the reset current will decrease by a considerable amount.

  FIG. 12 is a diagram illustrating the effect of the number of firings on the reset current. For a firing current that is 20% greater than the initial pre-firing reset current (eg, 1.2 times the initial reset current) and a pulse width of 500 nanoseconds (which becomes an amorphous phase after firing), FIG. FIG. 5 is a diagram showing a change in reset current depending on the number of firings. As shown in the figure, the reset current is not significantly affected even if the energization of the firing is performed many times.

  FIG. 13 is a diagram showing the effect of firing of the present invention on the resistance margin between reset and set states. The left side of FIG. 13 shows the resistance distribution in the reset and set states before firing (pre-firing). The right side of FIG. 13 shows the resistance distribution in the reset and set states after firing (post-firing). As shown in FIG. 13, the set and reset distributions almost overlap before firing. As a result, memory defects can occur. In contrast, after firing, a larger margin exists between the set and reset distributions, which significantly reduces the number of memory defects.

  14A and 14B are diagrams showing two improved examples by the firing process of the present invention. FIG. 14A shows a case where an amorphous phase is formed by firing, and FIG. 14B is a diagram showing a case where an FCC crystalline phase is formed by firing. As shown in the figure, in the above-described embodiment, a firing current 20% larger than the initial reset current (for example, 1.2 times the initial reset current) was selected as an example. This figure also shows that the decrease in reset current is an additional 20%, as expected from the example of FIG.

  FIG. 15 is a diagram showing another embodiment of the present invention. As shown, in step S1510, the semiconductor memory device is baked at a predetermined temperature for a predetermined time so that the phase change material has an HCP crystal state. For example, the temperature is below the melting point of the phase change material. In this embodiment, the programmable volume portion and the remaining portion of the phase change material have an HCP crystal structure. Next, in step S1512, a firing current is applied as shown in FIG. 10B so that the programmable volume has an FCC crystalline state. The remaining portion of the phase change material remains in the HCP crystal state.

  FIG. 16 is a diagram showing still another embodiment of the present invention. In the above-described embodiment, the firing operation is performed by applying a current to the phase change material. As described above, heat is generated when a current is applied. Thus, instead of using a current to apply heat to the phase change material, heat can also be applied directly. For example, FIG. 16 illustrates that a rapid thermal process is performed on a semiconductor device including phase change memory cells in step S1610. The rapid heat treatment is performed at a sufficient temperature for a sufficient time to change the phase change material to an amorphous state. For example, the temperature is higher than the melting point of the phase change material.

  As described above, preferred embodiments have been disclosed in the drawings and specification. Although specific terms are used herein, they are used merely to describe the present invention and are used to limit the scope of the invention as defined in the meaning and claims. It wasn't broken. Therefore, those skilled in the art can understand that various modifications and equivalent other embodiments are possible according to the present technology. Therefore, the substantial technical protection scope of the present invention should be determined by the technical idea of the appended claims.

1 is a structural diagram of a conventional phase change memory device. FIG. FIG. 2 illustrates set and reset pulses applied to program the memory cell of FIG. FIG. 2B shows the resistance state of the memory cell as a result of the pulse applied to FIG. 2A. FIG. 2 illustrates a programmable volume portion of a phase change material in the memory cell of FIG. It is a diagram which shows the set resistance distribution of the phase change substance before firing execution. It is a diagram which shows the set resistance distribution of the phase change substance after firing execution. It is a flowchart which shows the firing method which concerns on embodiment of this invention. 1 is a block diagram illustrating a phase change memory device of the present invention. It is the schematic which shows the drive unit of FIG. FIG. 8 is a timing diagram illustrating an operation of the phase change memory device of FIG. 7. It is a figure which shows embodiment of the firing current applied to the phase change substance of this invention. It is a figure which shows embodiment of the firing current applied to the phase change substance of this invention. It is a figure which shows the change rate of the reset current with respect to the change rate of firing current. It is a figure which shows the effect with respect to the frequency | count of performing the firing operation | movement of reset current. It is a figure which shows the effect of the firing operation with respect to the resistance difference between a set and a reset state. It is a figure which shows the specific form of the firing with respect to a reset electric current. It is a figure which shows the specific form of the firing with respect to a reset electric current. It is a figure which shows other embodiment of the firing which concerns on this invention. It is a figure which shows other embodiment of the firing operation | movement which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Substrate 102 Lower insulating layer 105 First contact hole 113 Lower electrode 115 Phase change material 119 Upper electrode 122 Upper insulating layer 125 Second contact hole 127 Conductive plug 129 Metal pattern

Claims (30)

In a method for reducing a reset current for resetting a part of a phase change material in a memory cell of a phase change memory device,
Converting at least a portion of the phase change material including a first crystalline phase into one of a second crystalline phase and an amorphous phase, wherein the second crystalline phase is more easily amorphous than the first crystalline phase. A method characterized by transitioning to a phase.   The method according to claim 1, wherein the first crystal phase has a hexagonal close-packed structure.   The method according to claim 2, wherein the second crystal phase has a face-centered cubic structure.   The method of claim 1, wherein the second crystalline phase has a face-centered cubic structure.   The method of claim 1, wherein the converting step performs a heat treatment to convert the first crystalline phase into one of the second crystalline phase and an amorphous phase.   The method according to claim 5, wherein the heat treatment is performed at a temperature higher than a melting point of the phase change material so as to convert the first crystalline phase into an amorphous phase.   The method of claim 5, further comprising changing at least a portion of the phase change material to the second crystalline phase after the converting step.   The method of claim 7, wherein the converting step comprises baking the phase change material for a predetermined period of time at a temperature below the melting point of the phase change material.   The method of claim 1, wherein the converting step applies current to the phase change material.   The method of claim 9, wherein the applied current is higher than a reset current when the conversion stage is not performed.   The method of claim 10, wherein the applied current is higher than or equal to 1.1 times a reset current when the conversion stage is not performed.   The method of claim 10, wherein the reset current after the conversion step is decreased by increasing the applied current.   11. The method of claim 10, wherein the converting stage applies current and the reset current after the converting stage is at least 20% smaller than the reset current before the converting stage.   11. The method according to claim 10, wherein the converting step applies a current having a pulse width such that the first crystalline phase is converted into an amorphous phase.   11. The method according to claim 10, wherein the converting step applies a current having a pulse width such that the first crystal phase is converted into the second crystal phase.   The method of claim 9, further comprising changing a portion of the phase change material that is not the first crystalline phase to the first crystalline phase before the converting step.   17. The method of claim 16, wherein the changing step comprises baking the phase change memory device for a predetermined period of time at a temperature below the melting point of the phase change material.   The method of claim 16, wherein the converting step converts only a portion of the phase change material such that a remaining portion of the phase change material remains in the first crystalline phase.   The method of claim 1, wherein the first crystalline phase has a lower resistance than the second crystalline phase. In a method of reducing a reset current for resetting a part of a phase change material in a memory cell of a phase change memory device to an amorphous phase,
Converting at least a portion of the phase change material in a mixed phase state to a single phase state.   21. The method of claim 20, wherein the converting step converts at least a portion of the phase change material in a mixed crystalline phase state to a single phase state.   The method of claim 21, wherein the single phase state is an amorphous phase.   The method of claim 21, wherein the single phase state is a single crystal phase. In a method of reducing a reset current for resetting a part of a phase change material in a memory cell of a phase change memory device to an amorphous phase,
Applying a current to the phase change material, wherein the reset current of the phase change material after the application step is lower than the reset current before the application step.   The set resistance, which is a resistance caused by a part of the phase change material when a current is applied in the application stage and is set in a crystalline phase, is lower than the set resistance before the application stage after the application stage. The method of claim 24, characterized in that   In the application step, a current is applied so that a margin between a set resistor and a reset resistor is increased, and the set resistor is a resistance caused by a part of the phase change material when set in a crystal phase, and the reset resistor is 25. The method of claim 24, wherein the resistance is due to a portion of the phase change material when set to an amorphous phase. In a method of reducing a reset current for resetting a part of a phase change material in a memory cell of a phase change memory device to an amorphous phase,
A method comprising performing a heat treatment on the phase change memory device, wherein a reset current of the phase change material after the execution stage is lower than a reset current before the execution stage. An upper electrode;
A lower electrode;
A phase change material disposed between the upper electrode and the lower electrode, wherein the phase change material is entirely a single phase, the single phase being an amorphous phase and a face-centered cubic structure phase. A phase change memory device characterized by being one of them. An upper electrode;
A lower electrode;
A phase change material disposed between the upper electrode and the lower electrode, wherein the phase change material includes a lower portion in contact with the lower electrode and a remaining portion, and the lower portion includes a first crystalline phase and an amorphous state. And the remaining portion includes at least a second crystalline phase, and the first crystalline phase is more easily transitioned to the amorphous phase than the second crystalline phase. In a method for improving the operation of a phase change memory device including at least one memory cell having a phase change material,
Treating the phase change material to reduce energy required to change a portion of the phase change material from a crystalline phase to an amorphous phase.

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