JP4479276B2 - Method for manufacturing lateral MOS transistor - Google Patents

Description

  The present invention relates to a method for manufacturing a lateral MOS transistor.

  For example, in an integrated circuit or the like used to drive an in-vehicle device, a lateral MOS (Lateral Diffused Metal Oxide Semiconductor) transistor is used as a high breakdown voltage element. Conventionally, as this type of lateral MOS transistor, there is a transistor described in Patent Document 1, for example. In this transistor, a base layer is provided in order to increase the breakdown voltage, and the impurity concentration of the channel layer formed so as to surround the source layer is partially increased in the vicinity of the source layer. In order to further increase the breakdown voltage, a so-called RESURF (surface electric field relaxation) structure is employed in which a pn junction is formed under the substrate surface and the electric field is relaxed by depletion of the pn junction during reverse bias.

Hereinafter, an example of such a lateral MOS transistor will be described with reference to FIGS. 15 and 16.
First, FIG. 15 is a plan view schematically showing a planar structure of a lateral MOS transistor formed on a semiconductor substrate.

  As shown in FIG. 15, the lateral MOS transistor is configured by alternately arranging source cells SC and drain cells DC on a semiconductor substrate. The source cell SC and the drain cell DC are electrically isolated by a field oxide film (element isolation insulating layer) IS and are connected in parallel through electrodes formed on the cells.

FIG. 16 is a cross-sectional view schematically showing the cross-sectional structure of this lateral MOS transistor. 16 corresponds to a cross-sectional view taken along the line AA in FIG.
As shown in FIG. 16, this transistor mainly includes a semiconductor substrate (silicon substrate) 410, an insulating layer 420, and a semiconductor layer 430 made of, for example, silicon formed on the insulating layer 420. Has been. Among these, the semiconductor layer 430 includes an N-type (first conductivity type) N ⁻ layer 431, a P-type (second conductivity type) P well 432, and various impurity regions formed above the P well 432. It is comprised. In addition, field oxide films (insulating layers for element isolation) IS4a and IS4b having a LOCOS (Local Oxidation Of Silicon) structure are formed on the surface, and the surface is separated into source cells and drain cells through them. . Incidentally, here, the structure of the source cell SC4 and the drain cell DC4 separated by the field oxide film IS4a is mainly shown.

  Among these cells, the drain cell DC4 includes an N-type drift layer (N well) DF4 that extends to an adjacent source cell and forms a pn junction with the P well 432, and a field oxide film on the surface of the drain cell DC4. An N-type drain layer 438 formed between IS4a and IS4b and having a concentration higher than that of the drift layer DF4 is formed. On the drain layer 438, a drain electrode 444b made of, for example, aluminum is electrically insulated from the gate electrodes 442b and 442c by an insulating film 443b and 443c made of, for example, BPSG (Boro Phospho Silicate Glass). Is formed. The drift layer DF4 functions as a carrier path to the drain layer 438. The gate electrode 442c is a gate electrode formed on the source cell adjacent to the drain cell DC4 via the gate insulating film 441c.

On the other hand, in the source cell SC4, a P-type channel layer CH4, a P-type base layer BS4, a P-type P ⁺ layer 436 having higher concentrations than these, and N-type source layers 437a and 437b are formed. Yes. On top of these, the gate insulating films 441a and 441b, the gate electrodes 442a and 442b made of polycrystalline silicon having a film thickness of, for example, “4000 mm”, the source electrode 444a made of aluminum, for example, and these electrodes are electrically connected. Insulating films 443a and 443b are formed.

  Here, the gate electrode 442b is formed on the semiconductor layer 430 via the gate insulating film 441b so that a part of the gate electrode 442b overlaps the field oxide film IS4a. The channel layer CH4 is formed in such a manner as to contact the drift layer DF4 and surround the source layers 437a and 437b including a part below the gate electrode 442b. The channel layer CH4 becomes a current path (carrier path) between the source layer 437b and the drain layer 438, and the current between the source and drain can be controlled through the voltage applied to the gate electrode 442b. .

  The base layer BS4 partially overlaps the channel layer CH4 to further increase the P-type impurity concentration of the channel layer CH4 immediately below the source layers 437a and 437b. As a result, the operation of the parasitic transistor formed by the source layer 437b, the channel layer CH4, and the drain layer 438 can be prevented. For example, the counter electromotive voltage applied when an L load such as a coil is connected to the drain electrode 438. Accordingly, the withstand voltage (L load resistance) is improved. The base layer BS4 is formed deeper and narrower than the channel layer CH4.

The source layers 437a and 437b are formed at a predetermined interval in a region where the base layer BS4 and the channel layer CH4 overlap to increase the concentration. The P ⁺ layer 436 is formed between the source layers 437a and 437b so as to penetrate both of them. The source electrode 444a is formed on the source layers 437a and 437b and the P ⁺ layer 436 so as to be in contact with all of them. The P ⁺ layer 436 is for taking the potential of the channel layer CH4, and this also prevents the operation of the parasitic transistor.

  Terminals G, S, and D in FIG. 16 are terminals electrically connected to the gate electrode 442b, the source electrode 444a, and the drain electrode 444b, respectively. In this lateral MOS transistor, the current between the source and drain (between the terminal S and the terminal D) is controlled through a voltage applied from the terminal G to the gate electrode 442b. In this lateral MOS transistor, transistors having the structure shown in FIG. 16 are connected in parallel. Therefore, a large current and a large output can be obtained by simultaneously operating the transistors connected in parallel.

  Next, an example of a method for manufacturing the lateral MOS transistor will be described with reference to FIG. FIG. 17 is a cross-sectional view showing an example of the manufacturing process for the manufacturing method of this lateral MOS transistor.

In this manufacturing, first, an SOI (Silicon On Insulator) substrate is prepared, in which the semiconductor substrate 410, the insulating layer 420, and the N ⁻ layer 431 (semiconductor layer 430) are sequentially stacked. Then, for example, after ion implantation and thermal diffusion are performed on the SOI substrate to form the P well 432, as shown in FIG. 17A, a resist RE41 patterned using a known lithography technique is used as a mask. An N-type impurity region 433 is formed by ion implantation of an N-type impurity such as arsenic (As) at a desired location. In this lithography process, mask alignment is performed using the alignment mark formed in the lithography process (first photo) performed first on the substrate.

  Next, as shown in FIG. 17B, field oxide films IS4a and IS4b having a LOCOS structure are formed by a well-known LOCOS oxidation method in such a manner that the surface of the semiconductor layer 430 is separated into source cells and drain cells. . In the alignment (positioning) of these field oxide films IS4a and IS4b, an alignment mark formed by first photo is used. In the subsequent lithography process, except for the case of self-alignment (self-alignment), the field oxide films IS4a and IS4b formed here are mask-aligned using alignment marks. Incidentally, here also, the structures of the source cell SC4 and the drain cell DC4 separated by the field oxide film IS4a are mainly shown.

  Thereafter, as shown in FIG. 17C, an insulating film 441 is formed on the semiconductor layer 430 by, for example, thermal oxidation, and an electrode material made of, for example, polycrystalline silicon is further formed on the insulating film 441. The gate electrodes 442a to 442c are formed by patterning, for example, by photolithography.

  Next, as shown in FIG. 18A, for example, boron is applied to the source cell SC4 using the gate electrodes 442a and 442b as a mask in a state where the drain cell DC4 is covered with, for example, a resist RE42 patterned by photolithography. A P-type impurity such as (B) is ion-implanted to form a P-type impurity region 435 in a self-aligning manner.

  Then, as shown in FIG. 18B, for example, a resist P43 patterned by using a photolithography technique is used as a mask to form a P type deeper and narrower than the P type impurity region 435. The impurity region 434 is formed.

Next, as shown in FIG. 18C, the impurity regions 433 to 435 are thermally diffused by a heat treatment of “1200 to 1400 ° C.”, for example, so that the drift layer (N well) DF4, the channel layer CH4, and the base layer BS4 is formed. Thereafter, ion implantation and thermal diffusion are performed on the source cell SC4 and the drain cell DC4, respectively, to form the source layers 437a and 437b, the drain layer 438, and the P ⁺ layer 436. Subsequently, after an insulating film is formed on the entire surface of the substrate, this is selectively removed to form contact holes to the source layers 437a and 437b and the drain layer 438, respectively. As a result, the gate insulating films 441a to 441c and the insulating films 443a to 443c are formed. Next, an electrode material made of, for example, aluminum is formed, and this is patterned to form a source electrode 444a and a drain electrode 444b. Thus, the lateral MOS transistor is formed.
Japanese Patent No. 3114592

  In general, in this type of lateral MOS transistor, the positions of the drift layer, the channel layer, and the base layer are closely related to the on-resistance and breakdown voltage (L load resistance) of the transistor.

FIG. 19A shows the relationship between the on-resistance (mΩ · mm ² ) and the L load withstand (mJ / mm ² ) and the width (μm) of the base layer for an example of such a lateral MOS transistor. It is a graph. Note that the width of the base layer shown here is the width of a photomask used when the base layer is formed. FIG. 19B is an enlarged sectional view showing a part of the lateral MOS transistor.

  As can be seen from the graph shown in FIG. 19 (a), when the width of the base layer is gradually increased, the width of the base layer becomes “1.4 μm”. The on-resistance, which has been kept constant, suddenly increases. On the other hand, with respect to the L load withstand capability, on the contrary, the L load withstand capability which has been maintained substantially constant until the width of the base layer becomes “0.8 μm” is improved. Then, when the width of the base layer becomes wider than “1.0 μm”, an L load resistance sufficient to withstand practical use is ensured. As shown in FIG. 19B, the increase in the on-resistance is caused by the base layer protruding from the channel layer below the gate electrode that becomes the actual channel (carrier passage) and the drift layer (N well). This is due to an increase in resistance due to overlapping.

  As described above, in this lateral MOS transistor, in order to ensure a withstand voltage (L load withstand capability) that can be practically used, it is necessary to increase the impurity concentration to the vicinity of the drain cell (drift layer) through the base layer. In order to keep the on-resistance low, it is necessary that the base layer does not protrude from the channel layer below the gate electrode. That is, in order to secure an L load withstand capability that can withstand practical use while keeping the on-resistance low, a range that satisfies these requirements, here “1.0 μm to 1.4 μm” (see FIG. 19A). It is necessary to match the width (position) of the base layer. For this reason, such a lateral MOS transistor has a very severe margin for misalignment and mask line width variation. Incidentally, this margin is “0.4 μm” here. In addition, although the positional displacement of the base layer has been described here as an example, the same problem occurs when the positional displacement occurs in the drift layer or the channel layer.

FIG. 20 is a comparison diagram showing the number of mask alignments of the drift layer (N well) DF4, the channel layer CH4, and the base layer BS4 in comparison with the conventional manufacturing method.
As shown in FIG. 20, in the conventional manufacturing method described above, the drift layer DF4 and the field oxide films IS4a and IS4b are each mask-aligned using alignment marks formed by first photo. Channel layer CH4 and base layer BS4 are mask-aligned using field oxide films IS4a and IS4b as alignment marks, respectively. More precisely, the channel layer CH4 is formed by self-alignment (self-alignment) using the electrode materials (gate electrodes 442a and 442b) patterned using the field oxide films IS4a and IS4b as alignment marks.

  That is, in this manufacturing method, the alignment (positioning) of the base layer BS4 with respect to the channel layer CH4 is aligned once, and the alignment of the channel layer CH4 and the base layer BS4 with respect to the drift layer DF4 is indirectly aligned twice. For this reason, for example, an alignment deviation of “0.4 μm” occurs.

  Thus, in the conventional manufacturing method described above, an alignment shift accompanying mask alignment is unavoidable, and it is difficult to obtain alignment (positioning) accuracy that satisfies the above conditions. Therefore, although the base layer BS4 can be formed to improve the breakdown voltage (L load tolerance) of the transistor, an increase in on-resistance is unavoidable.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method of manufacturing a lateral MOS transistor that can suitably suppress a performance degradation caused by misalignment.

In order to achieve such an object, in the method for manufacturing a lateral MOS transistor according to claim 1, after the surface of the semiconductor layer is separated into a source cell and a drain cell by an insulating layer for element isolation, After patterning the insulating film and the electrode material formed on the substrate, and forming at least a gate electrode through the gate insulating film on the source cell in the vicinity of the insulating layer as one of the patterned electrode materials, Drift layer which performs ion implantation to penetrate the insulating layer into the drain cell and the insulating layer and serves as a carrier path to the drain layer of the first conductivity type formed on the surface of the drain cell (B) ion implantation is performed on the source cell so as to include at least a part below the gate electrode. (C) forming an impurity region for forming a channel layer of the second conductivity type, and (c) performing ion implantation on the source cell to include a region of the second conductivity type below the source layer. Then, the step of forming an impurity region for forming a base layer whose concentration is increased in the periphery thereof is performed using the patterned electrode material as a mask.

  In general, in order to properly operate the lateral MOS transistor, it is necessary to ensure an appropriate width of the drift layer. Therefore, in the conventional manufacturing method described above, an impurity region (impurity region for forming the drift layer) is formed so as to include at least a part below the insulating layer before forming the insulating layer for element isolation. Therefore, an appropriate drift layer width is ensured. However, as described above, in such a manufacturing method, there is a concern about performance degradation due to misalignment. In this regard, in the above manufacturing method, the impurity region (the drift layer is formed so as to include at least a part below the insulating layer after forming the insulating layer for element isolation through ion implantation that penetrates the insulating layer. For this purpose, an appropriate drift layer width is secured. Then, the impurity region for forming the drift layer, the impurity region for forming the channel layer, and the impurity region for forming the base layer are formed using an electrode material that is patterned when forming the gate electrode as a mask. Self-alignment is performed. For this reason, the drift layer, the channel layer, and the base layer obtained by thermally diffusing these impurity regions, respectively, are formed with high positional accuracy without misalignment (positioning) associated with the mask alignment described above. That is, according to the manufacturing method described above, it is possible to suitably suppress performance degradation caused by misalignment. In addition, the process of said (a)-(c) is random.

Further, in the method of manufacturing a lateral MOS transistor according to claim 2, polycrystalline silicon is used as the electrode material, and an impurity region for forming the channel layer is formed using the patterned electrode material as a mask. after ion implantation to the source cell, the sidewall is formed on the patterned electrode material, then as a mask electrode material forming the side wall of this, the impurity regions for forming the base layer so that intends line ion implantation to said source cell to form a.

  As described above, in order to ensure a breakdown voltage (L load resistance) that can be practically used, it is necessary to increase the impurity concentration to the vicinity of the drain cell through the base layer. However, when the base layer protrudes from the channel layer below the gate electrode, the on-resistance is increased. In this regard, according to the above manufacturing method, the channel layer and the base layer are formed at appropriate locations through the sidewall formed on the electrode material. For this reason, it is possible to suitably suppress the above-described increase in on-resistance.

  In this case, in the method of manufacturing a lateral MOS transistor according to claim 3, an impurity region for forming the drift layer, an impurity region for forming the channel layer, and an impurity region for forming the base layer The thermal diffusion process is performed in the form of sharing one thermal diffusion process so that these impurity regions become a drift layer, a channel layer, and a base layer, respectively.

By doing so, the drift layer, the channel layer, and the base layer can be formed by a single thermal diffusion step, and thus energy saving can be achieved.
Further, the ion implantation for penetrating the insulating layer is realized by increasing the film thickness of the electrode material used as the mask relative to the film thickness of the insulating layer, as described in claim 4. By doing so, ion implantation that penetrates the insulating layer is easily realized.

  As the insulating layer, a field oxide film having a LOCOS structure or an insulating film having an STI structure can be used. These are generally used for element isolation (isolation) in a semiconductor process, and the formation method is well known. Therefore, according to the manufacturing method, the formation of the insulating layer itself can be facilitated, and the surface of the semiconductor layer can be appropriately separated.

(First embodiment)
1 to 6 show a first embodiment of a method for manufacturing a lateral MOS transistor according to the present invention.

  FIG. 1 schematically shows the schematic structure of a lateral MOS transistor to be manufactured in the manufacturing method according to this embodiment. FIG. 1 corresponds to FIG. That is, in FIG. 1, reference numerals 110, 120, 130 to 132, 136, 137 a and 137 b, 138, IS1 a and IS1 b are the elements indicated by reference numerals 410, 420, 430 to 432, 436, 437a and 437b and 438, and each element shown by IS4a and IS4b. In addition, reference numerals 141a to 141c, 142a to 142c, 143a to 143c, 144a and 144b, BS1, CH1, and DF1 denote elements indicated by reference numerals 441a to 441c, 442a to 442c, 443a to 443c, This corresponds to each element indicated by 444a and 444b, BS4, CH4, and DF4. Here, the overlapping description of these elements is omitted.

  As shown in FIG. 1, this transistor also basically has the same structure as the transistor illustrated in FIG. 16, and its operation mode is also as described above. However, in this transistor, the gate electrodes 142a to 142c are made relatively thicker than the field oxide films IS1a and IS1b. Side walls 145a to 145c are formed on the gate electrodes 142a to 142c, respectively. Through these, the drift layer DF1, the base layer BS1, and the channel layer CH1 are aligned (aligned) with high accuracy.

  A method for manufacturing the lateral MOS transistor according to this embodiment will be described below in detail with reference to FIGS. In these drawings, the same elements as those shown in FIG. 1 are denoted by the same reference numerals.

2A, first, as shown in FIG. 2A, for example, a semiconductor substrate 110 made of silicon and an insulating layer 120 made of silicon oxide, for example, and N made of N-type (first conductivity type) silicon, for example. ^- the layer 131 (semiconductor layer 130) is prepared an SOI (Silicon on Insulator) substrate which are stacked in this order. Next, as shown in FIG. 2B, a P-type (second conductivity type) impurity such as boron (B) is ion-implanted into the substrate, and the implanted impurity is diffused by, for example, thermal diffusion. Thus, the P well 132 is formed. As a result, the semiconductor layer 130 has a stacked structure having the P well 132 on the N ⁻ layer 131.

  Next, as shown in FIG. 3A, the surface of the semiconductor layer 130 is separated into a source cell and a drain cell by a well-known LOCOS (Local Oxidation Of Silicon) oxidation method, for example, with a film thickness of “1 μm”. Field oxide films (insulating layers for element isolation) IS1a and IS1b having a LOCOS structure are formed. That is, a silicon oxide film (pad oxide film) and a silicon nitride film are sequentially formed, and the silicon nitride film is selectively removed by, for example, photolithography to form an opening at a desired location. Then, only the opening not covered with the silicon nitride film is locally thermally oxidized to form the field oxide films IS1a and IS1b, and the formed silicon oxide film and silicon nitride film are removed. In this lithography process, mask alignment is performed using the alignment mark formed in the lithography process (first photo) performed first on the substrate.

Incidentally, here, the structure of the source cell SC1 and the drain cell DC1 separated mainly by the field oxide film IS1a is mainly shown.
Next, as shown in FIG. 3B, an insulating film 141 made of, for example, silicon oxide is formed on the semiconductor layer 130 by, for example, thermal oxidation. Next, as shown in FIG. 3C, an electrode material made of polycrystalline silicon having a film thickness of, for example, “6000 mm” is formed on the formed insulating film 141 and patterned by, for example, photolithography. Thus, gate electrodes 142a to 142c are formed. At this time, the film thickness of the electrode material is set relatively thick with respect to the film thickness of the field oxide films IS1a and IS1b. Also in the lithography process here, mask alignment is performed using an alignment mark formed by first photo.

Next, as shown in FIG. 4A, for example, boron (B) is applied to the source cell SC1 using the gate electrodes 142a and 142b as a mask while covering the drain cell DC1 with a resist RE11 patterned by photolithography, for example. P-type impurities such as, for example, are ion-implanted with an implantation energy of “20 keV to 40 keV”. Thus, after the P-type impurity region 135 is formed in a self-aligned manner, the resist RE11 is removed. The concentration of the P-type impurity region 135 is, for example, “1.0 × 10 ⁻¹³ cm ^{−3 to} 9.0 × 10 ⁻¹³ cm ⁻³ ”.

Next, as shown in FIG. 4B, for example, the drain cell DC1 and the field oxide films IS1a and IS1b are covered with the gate electrode 142b and 142c as a mask while covering the source cell SC1 with a resist RE12 patterned by photolithography. Then, high-acceleration ion implantation is performed so as to penetrate these field oxide films. At this time, the implanted impurity is, for example, an N-type impurity such as arsenic (As), and the implantation energy is, for example, “200 keV to 400 keV”. Then, after thus forming an N-type impurity region 133 including parts under the field oxide films IS1a and IS1b in a self-aligning manner, the resist RE12 is removed. The concentration of the N-type impurity region 133 is, for example, “1.0 × 10 ⁻¹³ cm ^{−3 to} 9.0 × 10 ⁻¹³ cm ⁻³ ”. In this embodiment, the width of the drift layer for properly operating the lateral MOS transistor is secured through high acceleration ion implantation that penetrates the field oxide films IS1a and IS1b.

  Next, as shown in FIG. 4C, the sidewalls 145a to 145c are formed on the gate electrodes 142a to 142c, for example, by a well-known sidewall formation method. That is, after a silicon oxide film is formed on the entire surface of the substrate, it is etched back using anisotropic etching so that the silicon oxide film is left only on the side walls of the gate electrodes 142a to 142c. When forming a CMOS (complementary MOS) together with the lateral MOS transistor on the SOI substrate, the side wall forming step and the CMOS side wall forming step are performed in a common manner. Thus, the sidewalls 145a to 145c can be formed without adding a new manufacturing process.

Then, as shown in FIG. 5A, for example, the source cell SC1 is covered with the gate electrodes 142a and 142b formed with the sidewalls 145a and 145b while covering the drain cell DC1 with a resist RE13 patterned by photolithography, for example. Is ion-implanted. At this time, the impurity to be implanted is a P-type impurity such as boron (B), and the implantation energy is, for example, “20 keV to 40 keV”. Then, after the P-type impurity region 134 is formed in a self-aligning manner, the resist RE13 is removed. The concentration of the P-type impurity region 134 is, for example, “1.0 × 10 ⁻¹³ cm ^{−3 to} 9.0 × 10 ⁻¹³ cm ⁻³ ”.

  In this way, after the P-type impurity region 135 is formed, the sidewalls 145a and 145b are formed, and ion implantation is performed using these as masks to form the P-type impurity region 134. Thus, a P-type impurity region 134 that is narrower than the type impurity region 135 is formed. Therefore, by thermally diffusing these impurity regions, the base layer BS1 narrower than the channel layer CH1 is easily formed, and the base layer BS1 does not protrude from the channel layer CH1 below the gate electrode 142b. . As a result, the above-described increase in on-resistance can be suitably suppressed.

  Next, as shown in FIG. 5B, the impurity regions 133 and 134 and the impurity region 135 are thermally diffused, for example, by performing a heat treatment of “1200 ° C. to 1400 ° C.”, for example. A layer (N well) DF1, a base layer BS1, and a channel layer CH1 are used.

  In this way, the thermal diffusion of the impurity regions 133 to 135 is performed in the form of sharing one thermal diffusion process, so that the drift layer DF1, the channel layer CH1, and the base layer BS1 are formed by one thermal diffusion process. Can be formed. As a result, energy saving is achieved.

Further, in order to obtain the structure shown in FIG. 5C, ions of N-type impurities such as arsenic (As) are implanted into desired locations of the source cell SC1 and the drain cell DC1 with an implantation energy of, for example, “20 keV to 40 keV”. After the implantation, an appropriate heat treatment is performed to form the source layers 137a and 137b and the drain layer 138. At this time, the drain layer 138 is formed in a self-aligned manner using the field oxide films IS1a and IS1b as masks. Thereafter, as also shown in FIG. 5C, the source cell SC1 is selectively ion-implanted with a P-type impurity such as boron (B), and then subjected to an appropriate heat treatment to form a P ⁺ layer. 136 is formed. The N-type impurity concentration of the source layers 137a and 137b and the drain layer 138 is, for example, “1.0 × 10 ⁻¹⁵ cm ^{−3 to} 9.0 × 10 ⁻¹⁵ cm ⁻³ ”. The P type impurity concentration of the P ⁺ layer 136 is, for example, “1.0 × 10 ⁻¹⁵ cm ^{−3 to} 9.0 × 10 ⁻¹⁵ cm ⁻³ ”.

  Next, as shown in FIG. 6A, after an insulating film made of, for example, BPSG (borophosphosilicate glass) is formed on the entire surface of the substrate, the insulating film including this is selectively removed by etching, and the source Contact holes for layers 137a and 137b and drain layer 138 are formed. Thus, gate insulating films 141a to 141c and insulating films 143a to 143c are formed.

  Then, as shown in FIG. 6B, after depositing an electrode material made of, for example, aluminum in a manner in which these contact holes are buried, the electrode material is patterned to form a source electrode 144a and a drain electrode 144b. .

Through the above steps, the lateral MOS transistor shown in FIG. 1 is manufactured.
As described above, in the method for manufacturing the lateral MOS transistor according to this embodiment, the drift layer DF1, the channel layer CH1, and the base layer BS1 are formed by the electrode material (gate electrodes 142a to 142c patterned through one lithography process). ) Is used as a mask for self-alignment. For this reason, the drift layer DF1, the channel layer CH1, and the base layer BS1 are formed with high positional accuracy without misalignment associated with mask alignment. In other words, this makes it possible to suitably suppress performance degradation due to misalignment.

As described above, according to the method for manufacturing a lateral MOS transistor according to this embodiment, the following excellent effects can be obtained.
(1) The surface of the semiconductor layer 130 is separated into source cells and drain cells by field oxide films IS1a and IS1b having a LOCOS structure. The insulating film and electrode material formed on the semiconductor layer 130 are patterned to form gate electrodes 142a to 142c made of polycrystalline silicon through the gate insulating films 141a to 141c. Thereafter, ion implantation is performed on the source cell SC1 using the patterned electrode material (gate electrodes 142a and 142b) as a mask to form a P-type impurity region 135. Next, using the patterned electrode material (gate electrodes 142b and 142c) as a mask, the drain cell DC1 and the field oxide films IS1a and IS1b are ion-implanted so as to penetrate the field oxide films to form N-type impurities. Region 133 is formed. Next, sidewalls 145a to 145c are formed on the gate electrodes 142a to 142c, and then ion implantation is performed on the source cell SC1 using the patterned electrode material (gate electrodes 142a and 142b) as a mask to form P-type impurities. Region 134 is formed. Then, the impurity regions 133 to 135 thus formed are thermally diffused to form the drift layer DF1, the base layer BS1, and the channel layer CH1. As a result, the drift layer DF1, the channel layer CH1, and the base layer BS1 are formed with high positional accuracy without misalignment due to mask alignment, and as a result, performance degradation due to misalignment can be suitably suppressed. Become.

  (2) Further, by reducing the on-resistance, the area of the chip on which the transistor is mounted can be reduced, the number of wafers processed can be reduced, and energy can be effectively utilized. Further, by suppressing the increase in on-resistance, the yield can be improved, so that the cost can be reduced and the energy can be saved.

  (3) Further, the channel layer CH1 and the base layer BS1 are formed at appropriate locations through the sidewalls 145a and 145b. For this reason, it is possible to suitably suppress the above-described increase in on-resistance.

(4) The impurity regions 133 to 135 are thermally diffused by sharing one thermal diffusion process. Thereby, energy saving is achieved.
(Second Embodiment)
Next, FIGS. 7 to 9 show a second embodiment of a method for manufacturing a lateral MOS transistor according to the present invention.

  FIG. 7 schematically shows a schematic structure of a lateral MOS transistor to be manufactured in the manufacturing method according to this embodiment. FIG. 7 corresponds to FIG. That is, in FIG. 7, reference numerals 210, 220, 230 to 232, 236, 237a and 237b, 238, BS2, CH2, and DF2 are the elements 110, 120, 130 to 132, 136, 137a and 137b, 138, BS1, CH1, and DF1. Also, the elements indicated by reference numerals 241a to 241c, 242a to 242c, 243a to 243c, 244a and 244b, IS2a and IS2b are the reference numerals 141a to 141c, 142a to 142c, 143a to 143c, 144a and It corresponds to each element shown by 144b, IS1a and IS1b. Here, the overlapping description of these elements is omitted.

  As shown in FIG. 7, this transistor also basically has the same structure as the transistor illustrated in FIG. 1, and its operation mode is also as described above. However, in this transistor, field oxide films IS2a and IS2b having an STI (Shallow Trench Isolation) structure are formed instead of the field oxide films IS1a and IS1b having the LOCOS structure shown in FIG.

  Hereinafter, with reference to FIG. 8 and FIG. 9, the manufacturing method of the lateral MOS transistor according to this embodiment will be described focusing on the differences from the first embodiment. Note that the steps shown in these figures correspond to the steps shown in FIGS.

In this manufacturing, first, as shown in FIG. 2A, first, a semiconductor substrate 210 made of, for example, silicon, an insulating layer 220 made of, for example, silicon oxide, and an N ⁻ layer 231 made of, for example, N-type silicon ( An SOI substrate is prepared in which semiconductor layers 230) are sequentially stacked. Then, a P well 232 is formed on the N ⁻ layer 231 by a process similar to the process shown in FIG.

  Next, as shown in FIG. 8A, the surface of the semiconductor layer 230 is separated into a source cell and a drain cell by, for example, a well-known STI formation method, for example, with a film thickness (depth) of “1 μm”. Field oxide films (insulating layers for element isolation) IS2a and IS2b having an STI structure are formed. That is, a silicon oxide film (pad oxide film) and a silicon nitride film are sequentially formed on the semiconductor layer 230, and selective etching is performed using, for example, a photolithography technique to form the field oxide films IS2a and IS2b. Therefore, a trench (groove) is formed at a desired location on the surface of the semiconductor layer 230. After that, for example, an insulating film made of silicon oxide is deposited by CVD (chemical vapor deposition) or the like to completely fill the trench, and the insulating film deposited outside the trench is removed by CMP (chemical mechanical polishing). To do. Thus, the field oxide films IS2a and IS2b are formed, and the formed silicon oxide film and silicon nitride film are removed. In this lithography process, mask alignment is performed using the alignment mark formed in the lithography process (first photo) performed first on the substrate.

Incidentally, also in this embodiment, the structure of the source cell SC2 and the drain cell DC2 separated by the field oxide film IS2a is mainly shown.
Then, through steps similar to those shown in FIGS. 3B to 3C, an insulating film 241 made of, for example, silicon oxide, and a gate electrode 242a, made of, for example, polycrystalline silicon having a thickness of “6000”. 242c is formed. Also in this case, the film thickness of the electrode material of the gate electrodes 242a to 242c is set relatively thick with respect to the film thickness of the field oxide films IS2a and IS2b.

  Subsequently, the same process as that shown in FIG. 4A is performed. That is, as shown in FIG. 8B, for example, the drain cell DC2 is covered with a resist RE21 patterned by photolithography, for example, and ion implantation is performed on the source cell SC2 using the gate electrodes 242a and 242b as a mask. After forming the type impurity region 235, the resist RE21 is removed. In this case as well, conditions such as implantation energy are the same as those in the process shown in FIG.

  Next, as shown in FIG. 8C, for example, the drain cell DC2 and the field oxide films IS2a and IS2b are covered with the gate electrode 242b and 242c as a mask while covering the source cell SC2 with a resist RE22 patterned by photolithography. Then, high acceleration ion implantation is performed so as to penetrate these field oxide films. In this case as well, conditions such as implantation energy are the same as those in the process shown in FIG. Then, after thus forming an N-type impurity region 233 including parts under the field oxide films IS2a and IS2b in a self-aligning manner, the resist RE22 is removed. In this embodiment, the width of the drift layer for properly operating the lateral MOS transistor is ensured through high acceleration ion implantation that penetrates the field oxide films IS2a and IS2b.

  Then, through the same process as shown in FIG. 4C, sidewalls 245a to 245c are formed on the gate electrodes 242a to 242c, respectively, and then the same as the process shown in FIG. 5A. The process is performed. That is, as shown in FIG. 9A, the drain cell DC2 is covered with a resist RE23 patterned by, for example, photolithography, and the source cell SC2 is formed using the gate electrodes 242a and 242b formed with the sidewalls 245a and 245b as a mask. On the other hand, ion implantation is performed. Then, after the P-type impurity region 234 is formed in a self-aligning manner, the resist RE23 is removed. In this case as well, conditions such as implantation energy are the same as those in the process shown in FIG. Also in this embodiment, the side walls 245a and 245b prevent the base layer BS2 from protruding from the channel layer CH2 below the gate electrode 242b. As a result, the above-described increase in on-resistance can be suitably suppressed.

  Next, as shown in FIG. 9B, the impurity regions 233 and 234 and the impurity region 235 are thermally diffused, for example, by performing a heat treatment of “1200 ° C. to 1400 ° C.”, for example. The layer (N-well) DF2, the base layer BS2, and the channel layer CH2 are used. Also here, the drift layer DF2, the channel layer CH2, and the base layer BS2 are formed by a single thermal diffusion process, thereby saving energy.

Then, through steps similar to those shown in FIGS. 5C and 6A to 6B, the source layers 237a and 237b, the drain layer 238, the P ⁺ layer 236, and the gate insulating films 241a to 241a A structure 241c, insulating films 243a to 243c, a source electrode 244a, and a drain electrode 244b are formed to have a structure shown in FIG.

Through the above steps, the lateral MOS transistor shown in FIG. 7 is manufactured.
As described above, also in the method of manufacturing the lateral MOS transistor according to this embodiment, the formation of the drift layer DF2, the channel layer CH2, and the base layer BS2 is performed once in the same lithography process as in the first embodiment. This is performed by self-alignment using the electrode material (gate electrodes 242a to 242c) patterned through the mask. For this reason, the drift layer DF2, the channel layer CH2, and the base layer BS2 are formed with high positional accuracy without misalignment due to mask alignment in the lithography process. As a result, it is possible to suppress an increase in on-resistance due to the above-described misalignment due to mask alignment while forming the base layer BS2 to increase the breakdown voltage.

  As described above, the method of manufacturing the lateral MOS transistor according to this embodiment can obtain the same effect as or equivalent to the effects (1) to (4) of the first embodiment. Can do.

( Comparative example )
Next, in FIGS. 10 to 14, showing a comparative example of a method of manufacturing the lateral type MOS transistor.

FIG. 10 schematically shows a schematic structure of a lateral MOS transistor to be manufactured in the manufacturing method according to this comparative example . FIG. 10 corresponds to FIG. That is, in this FIG. 10, the elements indicated by reference numerals 310, 320, 330 to 332, 336, 337a and 337b, 338, BS3, CH3, DF3 are the reference numerals 210, 220, 230 to 232, 236, 237a and 237b, 238, BS2, CH2, and DF2 respectively. Also, the elements indicated by reference numerals 341a to 341c, 342a to 342c, 343a to 343c, 344a and 344b, IS3a and IS3b are the reference numerals 241a to 241c, 242a to 242c, 243a to 243c, 244a and It corresponds to each element indicated by 244b, IS2a and IS2b. Here, the overlapping description of these elements is omitted.

  As shown in FIG. 10, this transistor also basically has the same structure as the transistor illustrated in FIG. 7, and its operation mode is also as described above. However, in this transistor, the drift layer DF3, the base layer BS3, and the channel layer CH3 are accurately aligned without increasing the thickness of the gate electrode 342 relative to the thickness of the field oxide films IS3a and IS3b. ing.

Hereinafter, a method for manufacturing a lateral MOS transistor according to this comparative example will be described with reference to FIGS. 11 to 13 focusing on differences from the first and second embodiments. In these drawings, the same elements as those shown in FIG. 10 are denoted by the same reference numerals.

In this manufacturing, first, as shown in FIG. 2A, first, a semiconductor substrate 310 made of, for example, silicon, an insulating layer 320 made of, for example, silicon oxide, and an N ⁻ layer 331 made of, for example, N-type silicon ( An SOI substrate configured by sequentially stacking semiconductor layers 330) is prepared. Then, a P well 332 is formed on the N ⁻ layer 331 by the same process as that shown in FIG.

  Next, as illustrated in FIG. 11A, a silicon oxide film (pad oxide film) 351 and a silicon nitride film 352 are sequentially formed on the semiconductor layer 330. Next, a resist RE31 is formed on the silicon oxide film 351 and the silicon nitride film 352, and is patterned by, for example, photolithography to form an opening at a desired location. In this lithography process, mask alignment is performed using the alignment mark formed in the lithography process (first photo) performed first on the substrate.

  Then, as shown in FIG. 11B, etching is performed using the patterned resist RE31 as a mask to separate the surface of the semiconductor layer 330 into source cells and drain cells, for example, with a depth of “1 μm”. Trenches (grooves) T3a and T3b are formed.

Next, as shown in FIG. 11C, using the resist RE31 as a mask, N-type impurities such as arsenic (As) are ionized into the trenches T3a and T3b with an implantation energy of “200 keV to 400 keV”, for example. inject. Then, N-type impurity regions 333a and 333b including a part below trenches T3a and T3b are formed in a self-aligning manner, and then the resist RE31 is removed. The concentration of these N-type impurity regions 333a and 333b is, for example, “1.0 × 10 ⁻¹³ cm ^{−3 to} 9.0 × 10 ⁻¹³ cm ⁻³ ”. In this comparative example , the width of the drift layer for properly operating the lateral MOS transistor is secured through ion implantation into the trenches T3a and T3b.

  Thereafter, an insulating film made of, for example, silicon oxide (TEOS film) is deposited by, for example, CVD (chemical vapor deposition) to completely fill the trenches T3a and T3b, and the insulating film deposited outside the trench is CMP (chemically). Then, the silicon oxide film 351 and the silicon nitride film 352 are removed. Thus, as shown in FIG. 12A, a field oxide film (element isolation) having an STI structure of, for example, a film thickness (depth) of “1 μm” in a mode in which the surface of the semiconductor layer 330 is separated into a source cell and a drain cell. Insulating layer) IS3a and IS3b are formed.

Incidentally, also in this comparative example , the structure of the source cell SC3 and the drain cell DC3 separated by the field oxide film IS3a is mainly shown.
Next, as illustrated in FIG. 12B, an insulating film 341 made of, for example, silicon oxide is formed on the semiconductor layer 330 by, for example, thermal oxidation, and the film thickness “ A gate electrode 342a to 342c is formed by forming an electrode material made of polycrystalline silicon having a thickness of 4000 mm and patterning the electrode material by, for example, photolithography. In this lithography process, the trenches T3a and T3b or the corresponding field oxide films IS3a and IS3b are used as alignment marks.

Next, as shown in FIG. 12C, for example, boron (B) or the like is formed on the source cell SC3 using the gate electrodes 342a and 342b as a mask while covering the drain cell DC3 with a resist RE32 patterned by photolithography, for example. The P-type impurity is ion-implanted with an implantation energy of, for example, “20 keV to 40 keV”. Then, after the P-type impurity region 335 is formed in a self-aligning manner, the resist RE32 is removed. The concentration of the P-type impurity region 335 is, for example, “1.0 × 10 ⁻¹³ cm ^{−3 to} 9.0 × 10 ⁻¹³ cm ⁻³ ”.

Next, through the same process as that shown in FIG. 4C, sidewalls 345a to 345c are formed on the gate electrodes 342a to 342c, respectively. Then, as shown in FIG. 13A, the source cell is covered with the gate electrodes 342a and 342b formed with the side walls 345a and 345b, while covering the drain cell DC3 with a resist RE33 patterned by, for example, photolithography. Ion implantation is performed on SC3. At this time, the impurity to be implanted is a P-type impurity such as boron (B), and the implantation energy is, for example, “20 keV to 40 keV”. Then, after the P-type impurity region 334 is formed in a self-aligning manner, the resist RE33 is removed. The concentration of the P-type impurity region 334 is, for example, “1.0 × 10 ⁻¹³ cm ^{−3 to} 9.0 × 10 ⁻¹³ cm ⁻³ ”.

Next, for example, by performing a heat treatment of “1200 ° C. to 1400 ° C.”, the impurity regions 333a and 333b, the impurity region 334, and the impurity region 335 are thermally diffused, respectively, and these are diffused into the above-described drift layer (N well) DF3. , Base layer BS3, and channel layer CH3. Then, through steps similar to the steps shown in FIGS. 5C and 6A to 6B, the source layers 337a and 337b, the drain layer 338, the P ⁺ layer 336, and the gate insulating films 341a to 341c. Then, insulating films 343a to 343c, a source electrode 344a, and a drain electrode 344b are formed to have a structure shown in FIG.

Through the above steps, the lateral MOS transistor shown in FIG. 10 is manufactured.
FIG. 14 is a comparison diagram showing the number of mask alignments of the drift layer (N well) DF3, the channel layer CH3, and the base layer BS3 in comparison with the above manufacturing method.

  As shown in FIG. 14, in the above manufacturing method, the drift layer DF3 and the field oxide films IS3a and IS3b are aligned (aligned) by the same lithography process using the alignment mark formed by the first photo. The The channel layer CH3 and the base layer BS3 are mask-aligned using the trenches T3a and T3b or the corresponding field oxide films IS3a and IS3b as alignment marks. More precisely, the channel layer CH3 and the base layer BS3 are electrode materials (gate electrodes 342a and 342b) patterned using the trenches T3a and T3b or the corresponding field oxide films IS3a and IS3b as alignment marks. Is formed by self-alignment (self-alignment).

  That is, according to this manufacturing method, the alignment (positioning) of the channel layer CH3 and the base layer BS3 with respect to the drift layer DF3 can be performed once. That is, according to such a manufacturing method, it is possible to suppress an increase in on-resistance due to the above-described misalignment due to mask alignment while forming the base layer BS3 to increase the breakdown voltage.

As described above, according to the manufacturing method of the lateral MOS transistor according to this comparative example, so that effects such as is obtained.
(1) Using the resist RE31 as a mask, trenches T3a and T3b that separate the surface of the semiconductor layer 330 into source cells and drain cells are formed. Next, impurity regions 333a and 333b are formed by performing ion implantation into trenches T3a and T3b, using resist RE31 as a mask. Thereafter, an insulating film is buried in trenches T3a and T3b to form field oxide films IS3a and IS3b having an STI structure. Then, using the trenches T3a and T3b or the electrode materials (gate electrodes 342a and 342b) patterned using the field oxide films IS3a and IS3b corresponding to the trenches T3a and T3b as masks, ion implantation and heat are applied to the source cell SC1. Perform diffusion. In this way, the P-type channel layer CH3 and the P-type base layer BS3 are formed.

  As a result, while increasing the withstand voltage by forming the base layer BS3, it is possible to suitably suppress an increase in on-resistance due to the above-described misalignment due to mask alignment.

(Other embodiments)
The above embodiments and comparative examples may be modified as follows.
In the comparative example , trenches T3a and T3b that separate the surface of the semiconductor layer 330 into source cells and drain cells are formed using the resist RE31 as a mask. Thereafter, impurity regions 333a and 333b for forming a drift layer are formed by performing ion implantation on the trenches T3a and T3b using the resist RE31 as a mask. Instead, the surface of the semiconductor layer 330 is separated into source cells and drain cells by the trenches T3a and T3b, and the trenches and the drain cells DC3 are formed with respect to the trenches and the drain cells DC3 using a mask patterned using the trenches as alignment marks. Impurity regions for forming the drift layer may be formed by ion implantation. This also makes it possible to align the channel layer CH3 and the base layer BS3 with respect to the drift layer DF3 once (alignment). That is, even by such a manufacturing method, an effect similar to or equivalent to the effect (1) of the comparative example can be obtained.

In the first or second embodiment, the formation order of the impurity regions 133 to 135 or the impurity regions 233 to 235 is arbitrary. Also in the comparative example , the order of forming the impurity regions 334 and 335 is arbitrary.

  In the first or second embodiment, the thermal diffusion of the impurity regions 133 to 135 or the impurity regions 233 to 235 is performed by sharing one thermal diffusion process. However, the present invention is not limited to this. For example, a thermal diffusion process suitable for the impurity regions may be performed on each of the impurity regions 133 to 135 or the impurity regions 233 to 235.

In the second embodiment or the comparative example , the surface of the semiconductor layer is separated into the source cell and the drain cell by the field oxide film IS2a or IS3a having the STI structure. However, it is not necessarily required to be a field oxide film, and other insulating films can be appropriately employed. The point is that the surface of the semiconductor layer can be separated into the source cell and the drain cell.

  In the first or second embodiment, ion implantation is performed using only the gate electrode as a mask to form the drift layer, the channel layer, and the base layer. However, the present invention is not limited to this. For example, in the patterning of the electrode material performed when the gate electrode is formed, a dummy pattern that is not used as an electrode may be formed together with the gate electrode, and this may be used as a mask.

In each of the above embodiments and comparative examples , when the position of the channel layer or the base layer can be set to an appropriate position by, for example , the temperature of thermal diffusion, the step of forming the sidewall may be omitted. Good. In this case, an electrode material other than polycrystalline silicon can be used as a material for the gate electrode.

In each of the above-described embodiments and comparative examples , a method for manufacturing a lateral MOS transistor having a RESURF (surface electric field relaxation) structure was mentioned. However, the present invention is not limited to this, and for example, the P-well 132, 232, or 332 is omitted. The present invention can be similarly applied to a method of manufacturing a lateral MOS transistor having a structure. Further, the source cells and the drain cells do not necessarily have to be formed in such a manner that they are alternately arranged two-dimensionally (see FIG. 15). Further, it is not always necessary to use an SOI substrate.

In the above embodiments and comparative examples , the present invention can be similarly applied to a method of manufacturing a lateral MOS transistor having a structure in which the conductivity types (N type and P type) are interchanged.
・ Others
(A) The surface of the semiconductor layer is separated into a source cell and a drain cell by a trench, and ion implantation is performed on the trench and the drain cell using a mask patterned using the trench as an alignment mark. Impurity regions for forming the drift layer are formed. Thereafter, an insulating film having an STI structure is formed by embedding an insulating film in the trench, and mask alignment is performed using the trench as an alignment mark for a mask pattern to be processed in a subsequent process.
(B) A trench that separates the surface of the semiconductor layer into a source cell and a drain cell is formed using an appropriate mask, and ion implantation is performed on the trench and the drain cell using the mask to drift. Impurity regions for forming the layers are formed. Thereafter, an insulating film having an STI structure is formed by embedding an insulating film in the trench, and mask alignment is performed using the trench as an alignment mark for a mask pattern to be processed in a subsequent process.
The above comparative example can be changed as appropriate as long as the condition is satisfied.

Sectional drawing which shows typically the schematic structure of the horizontal MOS transistor made into manufacture object in 1st Embodiment of the manufacturing method of the horizontal MOS transistor concerning this invention. (A)-(b) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. (A)-(b) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. Sectional drawing which shows typically the schematic structure of the horizontal MOS transistor made into manufacture object in 2nd Embodiment of the manufacturing method of the horizontal MOS transistor concerning this invention. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the embodiment. For lateral MOS transistor of the comparative example of a method of manufacturing a lateral type MOS transistor and the production of the subject, cross-sectional view schematically showing the schematic structure. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal MOS transistor concerning the comparative example . (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal MOS transistor concerning the comparative example . (A)-(b) is sectional drawing which shows the manufacturing process about the manufacturing method of the horizontal type | mold MOS transistor concerning the comparative example . The comparison figure which compares and shows the mask alignment frequency of a drift layer, a channel layer, and a base layer about the manufacturing method of the horizontal MOS transistor concerning the comparative example. The top view which shows typically the planar structure about the horizontal MOS transistor made into the manufacturing object in the manufacturing method of the horizontal MOS transistor concerning each said embodiment and comparative example . Sectional drawing which shows typically the schematic structure about an example of the horizontal MOS transistor made into the manufacture object in the manufacturing method of the conventional horizontal MOS transistor. (A)-(c) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional horizontal type | mold MOS transistor. (A)-(c) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional horizontal type | mold MOS transistor. A graph showing the relationship between the on-resistance (mΩ · mm ² ) and L load resistance (mJ / mm ² ) of a general lateral MOS transistor and the width (μm) of the base layer, (b) is a general lateral MOS FIG. 10 is an enlarged cross-sectional view of part of a transistor. The comparison figure which compares and shows the mask alignment frequency of a drift layer, a channel layer, and a base layer about an example of the manufacturing method of the conventional horizontal MOS transistor.

Explanation of symbols

110, 210, 310 ... Semiconductor substrate, 120, 220, 320 ... Insulating layer, 130, 230, 330 ... Semiconductor layer, 131, 231, 331 ... N ^- layer, 132, 232, 332 ... P well, 133, 233, 333a, 333b ... impurity regions (impurity regions for forming the drift layer), 134, 234, 334 ... impurity regions (impurity regions for forming the base layer), 135, 235, 335 ... impurity regions (channel layers) Impurity regions for forming) 136, 236, 336... P ⁺ layer, 137a, 137b, 237a, 237b, 337a, 337b ... source layer, 138, 238, 338 ... drain layer, 141a-141c, 241a-241c, 341a to 341c: gate insulating films, 142a to 142c, 242a to 242c, 342a to 342c ... Gate electrode, 143, 243, 343 ... Insulating film, 144a, 244a, 344a ... Source electrode, 144b, 244b, 344b ... Drain electrode, 145a-145c, 245a-245c, 345a-345c ... Side wall, BS1-BS3 ... Base layer, CH1 to CH3 ... Channel layer, DF1 to DF3 ... Drift layer, IS, IS1a, IS1b, IS2a, IS2b, IS3a, IS3b ... Field oxide film (insulating layer for element isolation), DC, DC1 to DC3 ... Drain cell, SC, SC1 to SC3... Source cell.

Claims (6)

One of the patterned electrode materials is obtained by patterning the insulating film and electrode material formed on the semiconductor layer after separating the surface of the semiconductor layer into a source cell and a drain cell by an insulating layer for element isolation. After forming at least a gate electrode on the source cell in the vicinity of the insulating layer via a gate insulating film,
(A) A carrier path to the drain layer made of the first conductivity type and formed on the surface of the drain cell by performing ion implantation to penetrate the insulating layer into the drain cell and the insulating layer Forming an impurity region for forming a drift layer to be
(B) performing an ion implantation on the source cell to form an impurity region for forming a channel layer of the second conductivity type including at least a part below the gate electrode;
(C) performing ion implantation on the source cell to form an impurity region for forming a base layer made of the second conductivity type and having a high concentration around the source layer and under the source layer; Using the patterned electrode material as a mask. A method for manufacturing a lateral MOS transistor. The electrode material is made of polycrystalline silicon, and ion implantation is performed on the source cell to form an impurity region for forming the channel layer using the patterned electrode material as a mask, and then the patterned electrode is formed. the sidewall is formed on the timber, then as a mask electrode material forming the side wall of this, it intends line ion implantation to said source cell to form an impurity region for forming said base layer claim 2. A method for producing a lateral MOS transistor according to 1. The thermal diffusion process for the impurity region for forming the drift layer, the impurity region for forming the channel layer, and the impurity region for forming the base layer is shared with one thermal diffusion step. The method for manufacturing a lateral MOS transistor according to claim 2, wherein the impurity regions are used as a drift layer, a channel layer, and a base layer, respectively. The ion implantation for penetrating the insulating layer is realized by making the film thickness of the electrode material used as the mask relatively larger than the film thickness of the insulating layer. A method for producing a lateral MOS transistor according to claim 1. The method for manufacturing a lateral MOS transistor according to claim 1, wherein the insulating layer is made of a field oxide film having a LOCOS structure. The method for manufacturing a lateral MOS transistor according to claim 1, wherein the insulating layer is made of an insulating film having an STI structure.

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