JP4862327B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a plurality of elements including MOS transistors having a trench gate structure and an element isolation region for insulating and isolating the elements, and a method for manufacturing the same.

Conventionally, in a MOS transistor having a trench gate structure, since electric field concentration occurs in the gate insulating film at the opening corner (shoulder) of the trench having a small curvature radius, in order to avoid a decrease in the breakdown voltage of the gate insulating film due to this, For example, it has been proposed to increase the radius of curvature by thermal oxidation (the corners of the opening are rounded and have a gentle shape) (see, for example, Non-Patent Document 1 and Patent Document 1).
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 8, AUGUST 1987, p1681-1687 Japanese Patent No. 3396553

  By the way, in a semiconductor device, a plurality of elements such as MOS transistors are provided on one semiconductor substrate, and each element is insulated and isolated by an element isolation region (for example, a LOCOS oxide film or STI). That is, an element isolation region is provided in the vicinity of the trench of the MOS transistor.

  According to the present inventors, although the opening corner of the trench was processed into a rounded and gentle shape, electric field concentration might occur in the gate insulating film depending on the positional relationship between the element isolation region and the trench. It became clear that the cost of the semiconductor device increased.

  In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve the reliability of the gate insulating film and reduce the cost.

  As a result of confirmation by the present inventor, although the opening corner of the trench is processed into a rounded and gentle shape, the opening corner overlaps with the element isolation region (in other words, the opening angle In the case where the edge of the part is in the element isolation region), since the connecting portion between the edge of the element isolation region and the opening corner is an angular shape, the electric field strength of the gate insulating film at the opening corner is It became clear that the electric field strength of the gate insulating film in the flat portion was significantly larger. Further, when the trench and the element isolation region are separated from each other, the electric field concentration can be suppressed. However, the element area increases even if the trench is separated too much, so that the cost increases. Therefore, it is preferable that the trench and the element isolation region have a predetermined positional relationship.

On the other hand, the invention according to claim 1 is a semiconductor device having a plurality of elements including a MOS transistor having a trench gate structure and an element isolation region for insulating and isolating the elements, wherein the trench opening of the MOS transistor is formed. The corner is processed into a rounded and gentle shape, and the distance between the end of the opening corner of the trench on the surface of the semiconductor substrate and the end of the isolation region adjacent to the MOS transistor on the trench side If Xc is Xc, it is configured to satisfy Xc = 0 . In the above description, the opening corner of the trench refers to a portion having a rounded and gentle shape that connects the flat portion of the sidewall of the trench and the flat portion of the substrate surface, and is an end portion of the opening corner. Indicates a boundary portion with the flat portion of the substrate surface.

As described above, according to the present invention, since Xc = 0 , the opening corner portion and the element isolation region do not overlap (the end portions coincide ). Therefore, electric field concentration in the gate insulating film at the opening corner can be suppressed, and the reliability of the gate insulating film can be improved. Further, since Xc = 0 , the distance from the trench to the element isolation region can be shortened to reduce the element area. Therefore, according to the present invention, the reliability of the gate insulating film can be improved and the cost can be reduced (downsized) .

Next, a second aspect of the present invention relates to a manufacturing method for manufacturing the semiconductor device according to the first aspect, and a plurality of elements including MOS transistors having a trench gate structure and an element isolation region for insulating and isolating the elements from each other. A device isolation region forming step of forming an element isolation region in a semiconductor substrate, a trench formation step of forming a trench in the vicinity of the element isolation region of the semiconductor substrate, and at least opening of the trench The curvature radius of the corner is made larger than that at the time of trench formation, and the gate corner film is formed on the surface of the trench by forming a gate insulating film on the surface of the trench with a rounded and gentle shape. A gate forming step of forming a gate electrode in the trench, and an element isolation region adjacent to the end of the opening corner of the trench on the surface of the semiconductor substrate and the MOS transistor When the distance between the end portion of the trench side and Xc, the isolation region formation step, a trench forming step, and the music Daehwa step, so as to satisfy Xc = 0, to form an element isolation region and the trench Features.

Since the operational effects of the present invention are the same as the operational effects of the invention described in claim 1, the description thereof is omitted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
1A and 1B are diagrams illustrating a schematic configuration of a semiconductor device according to the present embodiment, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along a line AA in FIG. As shown in FIGS. 1A and 1B, a semiconductor device 100 according to this embodiment includes a plurality of elements including a trench gate structure MOS transistor 20 in a semiconductor substrate 10 and element isolation for insulating and isolating the elements from each other. This is a semiconductor device having a LOCOS oxide film 30 as a region. In FIG. 1, only a part is shown for convenience.

  The semiconductor substrate 10 is not particularly limited. For example, a substrate made of silicon or an SOI (Silicon On Insulator) substrate in which an insulating film is embedded may be used.

  The trench gate structure MOS transistor 20 is configured as, for example, a vertical N-channel transistor having an N conductivity type region as a source and a drain. The MOS transistor 20 includes an n − type diffusion region (not shown) which is a drain region formed on the semiconductor substrate 10 and a p type diffusion region which is a base region selectively formed on the surface layer portion of the diffusion region. (P-well), an n + -type diffusion region that is a source region selectively formed in the surface layer portion of the diffusion region, a diffusion region that is a drain region and penetrates through a diffusion region that is a source region and a diffusion region that is a base region A trench 21 formed so as to reach the region (a region surrounded by an alternate long and short dash line in FIG. 1A), a gate electrode 23 embedded in the trench 21 via the gate insulating film 22, and an interlayer insulating film (not shown) , Source electrode, drain electrode, wiring and the like.

  In the trench 21, the shape of the opening corner (shoulder) that connects the flat portion of the sidewall of the trench 21 and the flat portion of the substrate surface is a rounded and gentle shape to suppress electrolytic concentration. . A LOCOS oxide film 30 as an element isolation region is formed around the MOS transistor 20. In the present embodiment, three trenches 21 are formed in a region surrounded by the LOCOS oxide film 30. In FIG. 1, reference numeral 21 a indicates an end of the opening corner of the trench 21 (in other words, a boundary part with a flat part of the substrate surface or a rounded gentle end part). Reference numeral 30a denotes an end portion of the LOCOS oxide film 30 on the trench 21 side. Reference numeral 40 denotes a contact for connecting the source region and the drain region to the source electrode and the drain electrode, respectively.

  Here, in the semiconductor device 100 having the above configuration, the inventor investigated the relationship between the positional relationship between the trench 21 and the LOCOS oxide film 30 and the electric field concentration at the opening corner of the trench 21. The result is shown in FIG. FIG. 2 shows a flat portion of the substrate surface when the distance between the end 21c of the opening corner of the trench 21 and the end 30a of the LOCOS oxide film 30 is Xc (see FIG. 1B). It is a simulation result which shows the relationship between Xc and the electric field strength ratio of the gate insulating film 22 of the opening corner | angular part with respect to the gate insulating film 22. FIG. 3 is a diagram showing the positional relationship between the trench 21 (the end 21a of the opening corner) and the LOCOS oxide film 30 (the end 30a), where (a) is Xc> 0 and (b) is Xc = 0, (c) shows the case of Xc <0.

  As shown in FIG. 3A, in the configuration in which Xc> 0, that is, in the configuration having a connecting flat portion between the end 21a of the opening corner and the end 30a of the LOCOS oxide film 30, FIG. As shown, the electric field strength of the gate insulating film 22 at the opening corner is approximately 1.2 times the electric field strength of the gate insulating film 22 in the flat portion. Further, as shown in FIG. 3B, the same applies to the configuration in which Xc = 0, that is, the end portion 21a of the opening corner and the end portion 30a of the LOCOS oxide film 30 coincide.

  However, as shown in FIG. 3C, Xc <0, that is, a configuration in which the opening corner portion of the trench 21 partially overlaps the LOCOS oxide film 30 (in other words, the end portion 21a of the opening corner portion is LOCOS). In the structure in the oxide film 30), as shown in FIG. 2, the electric field strength of the gate insulating film 22 at the corners of the opening is significantly larger than the electric field strength of the gate insulating film 22 at the flat portion. The intensity ratio was larger than about 1.2.

  This is because the connecting portion between the end portion 30a of the LOCOS oxide film 30 and the opening corner portion of the trench 21 has an angular shape, so that the electric field strength of the gate insulating film 22 at the opening corner portion is equal to the gate insulation at the flat portion. It is considered that the value is significantly larger than the electric field strength of the film 22.

  Actually, when the MOS transistor having the configuration shown in FIG. 3A and the configuration shown in FIG. 3C was formed and the gate voltage and the gate current were measured, as shown in FIG. 4, Xc <0. The configured transistor flowed a larger gate current than the transistor configured to satisfy Xc> 0. Therefore, it is clear that electric field concentration occurs at Xc <0. When electric field concentration occurs in this way, an excessive electric field is applied to the gate insulating film 22 and the reliability is lowered. That is, the lifetime of the gate insulating film 22 against the destruction phenomenon with time is remarkably shortened. FIG. 4 is a diagram showing the relationship between the gate voltage and the gate current.

  In order to suppress electric field concentration, it is preferable to satisfy Xc ≧ 0. However, even if the distance between the trench 21 and the LOCOS oxide film 30 that is the element isolation region is too large, the element area increases, resulting in an increase in cost. Therefore, the trench 21 and the LOCOS oxide film 30 need to be in a predetermined positional relationship so that the reliability of the gate insulating film 22 is improved and the cost is reduced.

Therefore, in the present embodiment, the above-described semiconductor device 100 (see FIG. 1) is configured so that Xc satisfies the following equation.
(Formula 1) 0 ≦ Xc ≦ ΔWi + ΔWt + 2Xa
Here, ΔWi is an allowable width that allows processing variation (processing accuracy) of the LOCOS oxide film 30, ΔWt is an allowable width that allows processing variation (processing accuracy) of the trench 21, and Xa is a positional variation of the trench 21 with respect to the LOCOS oxide film 30. This is an allowable width that allows (positioning accuracy). In the present embodiment, as the allowable widths ΔWi, ΔWt, and the allowable width Xa, values obtained by adding a predetermined margin to each variation value (accuracy) are employed. However, as the allowable widths ΔWi, ΔWt, and Xa, the values (accuracy) of the respective variations may be employed.

  Next, Equation 1 will be described with reference to FIGS. FIGS. 5A and 5B are diagrams for explaining the expression 1. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line BB in FIG. FIG. 5 corresponds to FIG.

As described above, in the semiconductor device 100 according to the present embodiment, the periphery of the MOS transistor 20 is surrounded by the LOCOS oxide film 30. Therefore, as shown in FIG. 5A, in the longitudinal direction of the trench 21, the distance between both end portions 21a of the trench 21 is Wt, and the distance between the end portions 30a of the LOCOS oxide film 30 respectively facing the both end portions 21a. Is Wi. Both Wt and Wi have processing variations in their respective forming steps, and are set to have a predetermined length even when processing variations occur. Here, assuming that the respective target values (processing center values) are Wtc and Wic, and the processing variations (processing accuracy) are ΔWt and ΔWi, respectively, Wt and Wi can be expressed by Equations 2 and 3, respectively.
(Formula 2) Wt = Wtc ± ΔWt
(Formula 3) Wi = Wic ± ΔWi
Further, in the present embodiment, as will be described later, after forming the LOCOS oxide film 30, the trench 21 is formed using the LOCOS oxide film 30 as a positioning reference. However, the position variation (positioning) of the trench 21 with respect to the LOCOS oxide film 30 is determined. Accuracy) occurs. Therefore, the above-described Xa is set as an allowable width Xa that allows this positional variation.

For example, when Wt and Wi shown in Equations 2 and 3 are formed with processing center values (that is, no processing variation), and the positional deviation of the trench 21 with respect to the LOCOS oxide film 30 is 0, Xc is expressed by Equation 4 and LOCOS oxidation is performed. When the positional deviation of the trench 21 with respect to the film 30 is Xa (maximum), Xc of which the position is shifted and the interval is narrowed is expressed by Equation 5, and Xc of the position which is shifted and the interval is widened is expressed by Equation 6. .
(Expression 4) Xc = 1/2 × ΔWi + 1/2 × ΔWt + Xa
(Formula 5) Xc = 1/2 × ΔWi + 1/2 × ΔWt
(Expression 6) Xc = 1/2 × ΔWi + 1/2 × ΔWt + 2Xa
Further, when Wt is the maximum value and Wi is the minimum value, and the positional deviation of the trench 21 with respect to the LOCOS oxide film 30 is 0, Xc is expressed by Equation 7, and the positional deviation of the trench 21 with respect to the LOCOS oxide film 30 is Xa ( In the case of (maximum), Xc of the one where the interval is shifted and the interval is narrowed is expressed by Equation 8, and Xc of the one where the interval is shifted and the interval is widened is expressed by Equation 9 (Expression 7)
(Formula 8) Xc = 0
(Formula 9) Xc = 2Xa
Further, when Wt is the minimum value and Wi is the maximum value, and the positional deviation of the trench 21 with respect to the LOCOS oxide film 30 is 0, Xc is expressed by Equation 10, and the positional deviation of the trench 21 with respect to the LOCOS oxide film 30 is Xa. In the case of (maximum), Xc of which the position is shifted and the interval is narrowed is expressed by Equation 11, and Xc of the position which is shifted and the interval is widened is expressed by Equation 12.
(Expression 10) Xc = ΔWi + ΔWt + Xa
(Formula 11) Xc = ΔWi + ΔWt
(Expression 12) Xc = ΔWi + ΔWt + 2Xa
Therefore, as can be seen from the results shown in Equations 4 to 12, if Xc is set within the range shown in Equation 1, the opening corner portion of the trench 21 is taken into consideration in consideration of processing variations and position (decision) variations. In the semiconductor device 100 having the MOS transistor 20 having the trench gate structure having a rounded and gentle shape, it is possible to achieve both improvement in reliability of the gate insulating film 22 and cost reduction.

  In particular, since the above Expression 12 is the maximum, Xc (that is, the respective processing center values Wtc and Wic) may be set so as to satisfy Expression 12. In this case, when there is a possibility that processing variations and position (decision) variations may occur, it is possible to stably improve the reliability of the gate insulating film 22 and reduce the cost. Note that the value of the right side (ΔWi + ΔWt + 2Xa) of Equation 12 is generally about 0.5 μm. Therefore, the element area can be minimized (cost reduction) without unnecessarily increasing the value of Xc.

  Next, an example of the method for manufacturing the semiconductor device 100 that satisfies Formula 1 will be described below. A known semiconductor manufacturing technique can be applied to each process of manufacturing the semiconductor device 100. First, a LOCOS oxide film 30 which is an element isolation region is formed on the semiconductor substrate 10, and after each diffusion region is formed, a trench 21 is formed in the vicinity of the LOCOS oxide film 30 using the formed LOCOS oxide film 30 as a positioning reference. After the trench 21 is formed, for example, by forming a sacrificial oxide film by thermal oxidation and removing the film, the radius of curvature of at least the opening corner of the trench 21 is made larger than that at the time of trench formation, and the opening corner is rounded. Use a gentle shape.

  Here, in the step of forming the LOCOS oxide film 30, the step of forming the trench 21, and the step of enlarging the curvature of the opening corner, the LOCOS oxidation is performed so as to satisfy Equation 1 (or Equation 12). The film 30 and the trench 21 may be formed.

  Then, a gate insulating film 22 is formed on the surface of the trench 21 by a thermal oxidation method, a vapor phase growth method, or the like, and a gate electrode material is embedded in the trench 21 through the gate insulating film 22 to form the gate electrode 23. Thereafter, an interlayer insulating film, a source electrode, a drain electrode, a wiring, and the like are formed, and the semiconductor device 100 shown in FIG.

  Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be implemented with various modifications.

  In this embodiment, the example which has the LOCOS oxide film 30 as an element isolation region was shown. However, it is not limited to the LOCOS oxide film 30. For example, an STI oxide film or a trench isolation region may be used. Also, a combination thereof may be used.

  For example, when the trench isolation region is formed as the element isolation region, the LOCOS oxide film 30 is formed with reference to the trench isolation region, and the trench 21 is formed with reference to the trench isolation region, the LOCOS oxide film 30 and The positional relationship with the trench 21 is a positional relationship that is indirectly positioned through the trench isolation region. In this case, as shown in the present embodiment, the variation (positioning accuracy) Xa ′ due to the positioning of the trench 21 indirectly with respect to the LOCOS oxide film 30 may be applied as the allowable width Xa that allows the positional variation. .

  In the present embodiment, a LOCOS oxide film 30 is provided so as to surround the element (MOS transistor 20), and in the longitudinal direction of the trench 21, end portions of the LOCOS oxide film 30 respectively opposed to both end portions 21 a of the trench 21. An example is shown in which the distance between 30a is Wi, and the processing variation is ΔWi. However, the site (length) that serves as a reference for processing variations in the element isolation region is not limited to the above example. For example, as shown in FIG. 6, when the LOCOS oxide film 30 is provided only on one end 30a side in the longitudinal direction of the trench 21, the width of the LOCOS oxide film 30 may be Wi, and the processing variation may be ΔWi. . Even in that case, by setting Xc so as to satisfy Formula 1 (or Formula 12) shown in the present embodiment, it is possible to achieve both improvement in reliability of the gate insulating film 22 and cost reduction. FIG. 6 is a diagram illustrating a modification of the present embodiment.

  In the present embodiment, an example in which the LOCOS oxide films 30 are provided on both sides in the longitudinal direction of the trench 21 and Xc is taken into consideration is shown. However, the same applies to the short direction. For example, when it is necessary to consider the positional relationship between the LOCOS oxide film 30 formed in both the longitudinal direction and the lateral direction and the trench 21 (when processing variations and positional variations differ between the longitudinal direction and the lateral direction). Therefore, Xc may be set individually so as to satisfy Expression 1 (or Expression 12) in each direction. Thereby, the reliability improvement and cost reduction of the gate insulating film 22 can be made compatible.

It is a figure which shows schematic structure of the semiconductor device which concerns on 1st Embodiment, (a) is a top view, (b) is sectional drawing in the AA cross section of (a). It is a simulation result which shows the relationship between the electric field strength ratio of the gate insulating film of the opening corner | angular part with respect to the gate insulating film in the flat part of the substrate surface, and Xc. It is a figure which shows the positional relationship of a trench and a LOCOS oxide film, (a) shows the case where Xc> 0, (b) shows Xc = 0, (c) shows the case of Xc <0. It is a figure which shows the relationship between a gate voltage and a gate current. It is a figure for demonstrating Formula 1, (a) is a top view, (b) is sectional drawing in the BB cross section of (a). It is a figure which shows a modification.

Explanation of symbols

10 ... Semiconductor substrate 20 ... MOS transistor (element)
21... Trench 21 a... Edge portion 22 of opening hole gate gate insulating film 23 gate electrode 30 LOCOS oxide film (element isolation region)
30a ... LOCOS oxide film end 100 ... semiconductor device

Claims (2)

A semiconductor device having a plurality of elements including a MOS transistor having a trench gate structure and an element isolation region for insulating and isolating the elements,
The opening corner of the trench of the MOS transistor has been processed into a rounded and gentle shape,
When the distance between the end of the opening corner of the trench on the semiconductor substrate surface and the end of the element isolation region adjacent to the MOS transistor on the trench side is Xc , Xc = 0 is satisfied. A semiconductor device characterized by comprising. A method for manufacturing a semiconductor device having a plurality of elements including a MOS transistor having a trench gate structure and an element isolation region for insulating and isolating the elements,
An element isolation region forming step for forming the element isolation region in a semiconductor substrate;
Forming a trench in the vicinity of the element isolation region of the semiconductor substrate; and
A step of increasing the radius of curvature of at least the opening corner of the trench larger than that at the time of forming the trench, and making the opening corner to a rounded and gentle shape; and
Forming a gate insulating film on the trench surface, and forming a gate electrode in the trench through the gate insulating film,
When the distance between the end of the opening corner of the trench on the semiconductor substrate surface and the end of the element isolation region adjacent to the MOS transistor on the trench side is Xc ,
In the element isolation region forming step, the trench forming step, and the bending step, the element isolation region and the trench are formed so as to satisfy Xc = 0 .

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