JP4479180B2 - Multilayer circuit board manufacturing method - Google Patents

Description

    The present invention relates to a method for manufacturing a multilayer circuit board such as a printed wiring board and an interposer used in various electronic devices, and more particularly to a method for electrical connection between layers in the printed wiring board and the interposer.

    A method for manufacturing a conventional multilayer circuit board (printed wiring board and interposer) will be described below.

    An example of a conventional method for producing a multilayer circuit board (printed wiring board and interposer) is shown in FIGS. 3 (a) to 3 (f) and FIGS.

First, electroless copper plating is performed on an insulating base material (111) obtained by impregnating a glass cloth with an epoxy resin to form a plating base layer (121) (see FIG. 3A).

Next, a liquid photoresist is applied on the plating base layer (121) and dried to form a photosensitive layer (131) (see FIG. 3B), and a series of patterning processes such as pattern exposure and development are performed. A first resist pattern (131a) is formed (see FIG. 3C).

Next, electrolytic copper plating is performed using the second resist pattern (132) as a mask to form a lower conductor layer (141) having a predetermined thickness on the plating base layer (121) (see FIG. 3D). .

Next, the first resist pattern (131a) is stripped with a dedicated stripping solution, the plating base layer (121) under the first resist pattern (131a) is removed by flash etching, and the lower wiring layer ( 141a) (see FIG. 3E).

Next, a liquid resin solution is applied on the insulating base material (111) and the lower wiring layer (141a) , and is heated and dried to form an insulating layer (151) (see FIG. 3F).

Next, via holes (152) are formed in the insulating layer (151) at a predetermined position on the lower wiring layer (141a) by laser processing, desmearing, plating catalyst application, and electroless copper plating are performed. A formation (in particular, not shown) is formed (see FIG. 4G).

Next, a photosensitive layer is formed by a method such as applying a liquid photoresist, and a series of patterning processes such as pattern exposure and development are performed to form a second resist pattern (132) (FIG. 4H). reference).

Next, electrolytic copper plating is performed using the second resist pattern (132) as a mask to form an upper conductor layer (142) and a via (143) (see FIG. 4 (i)).

Next, the second resist pattern (132) is stripped with a dedicated stripping solution, and the plating base layer under the second resist pattern (132) is removed by flash etching, and the upper wiring layer (142a) is removed. Then, the upper wiring layer (142a) is electrically connected to the lower wiring layer (141a) through the via (143) to obtain a two-sided printed wiring board and an interposer (see FIG. 4 (j)).

    In the printed wiring board and interposer manufacturing method as described above, vias for electrical connection between layers are formed with via holes (openings) in the interlayer insulating layer, and conductors are formed in the via holes by electrolytic copper plating. It is embedded and formed.

    Specifically, a photoresist layer or an insulating layer having a thickness of 40 to 50 μm is formed, and a patterning process such as pattern exposure and development is performed on the photoresist layer to form a via hole, or a predetermined insulating layer is formed. There is a laser processing method to form a hole for via by irradiating a laser beam to the position, and then pretreatment such as roughening treatment, plating catalyst application and electroless copper plating, etc. for via by electrolytic copper plating etc. In general, a via having a filled structure is formed by embedding a conductor in a hole.

    In the method of embedding a conductor in the via hole by electrolytic copper plating, it is difficult to uniformly embed the conductor in the via hole (opening) as the via becomes finer, and the via hole (opening) Therefore, the diameter of the lower portion of the via is reduced (if the 60 μm via is formed in the resin layer having a thickness of 40 to 50 μm, the diameter of the lower portion of the via in contact with the wiring layer is 30 to 40 μm). Adhesion with the lower wiring layer is reduced, and there is a problem such as partial delamination during resistance tests such as thermal shock and heat cycle. When the via diameter is small and the interlayer insulating layer is thick The tendency is getting stronger.

    Several via formation methods for solving these problems have been proposed (see, for example, Patent Document 1).

However, due to recent demands for finer and higher density wiring layers, a via diameter of about 60 μm is required, and there is a strong demand for cost reduction of printed wiring boards and interposers. The current situation is that it is no longer available.
JP 11-243279 A

    The present invention has been devised in view of the above-described problems, and provides a method for manufacturing a multilayer circuit board (printed wiring board and interposer) that is reduced in cost and improves the reliability of electrical connection between layers. Objective.

In order to achieve the above object, the present invention provides a method for producing a multilayer circuit board comprising the following steps in a method for producing a multilayer circuit board such as a printed wiring board or an interposer.
(A) A step of forming a plating underlayer on the insulating substrate.
(B) A step of forming a photosensitive layer on the plating base layer .
(C) A step of forming a first resist pattern by performing a series of patterning processes such as pattern exposure and development.
(D) A step of performing electrolytic copper plating using the first resist pattern as a mask to form a base conductor layer on the plating base layer .
(E) A step of forming a protruding conductor at a predetermined position of the underlying conductor layer.
(F) A step of performing electrolytic copper plating using the first resist pattern as a mask to form a lower wiring layer made of a protruding conductor having an upper conductor layer formed on the surface .
(G) The first resist pattern is stripped, the plating base layer under the first resist pattern is removed by etching, and a lower wiring layer made of a protruding conductor having an upper conductor layer formed on the surface Forming.
(H) A step of forming an insulating layer.
(I) A step of polishing the surface of the insulating layer to form a via-corresponding conductor in which the upper part of the protruding conductor having a conductor layer formed on the surface is exposed.
(J) A step of forming a plating base layer and a photosensitive layer .
(K) A step of repeating the steps (c) to (j) as many times as necessary.
(L) A step of forming a second resist pattern by performing a series of patterning processes such as pattern exposure and development.
(M) A step of performing electrolytic copper plating using the second resist pattern as a mask to form a surface conductor layer on the plating base layer.
Finally, (n) a step of removing the second resist pattern, removing the plating base layer under the second resist pattern by etching, and forming an upper wiring layer on the polished insulating layer.

    In the method for producing a multilayer circuit board according to the present invention, a protruding conductor is formed on a conductor layer, and after forming an insulating layer, surface polishing is performed to expose the upper portion of the protruding conductor to form a via. Excellent electrical connection between the layer and the protruding conductor (equivalent to via) can be obtained, and a multilayer circuit board (printed wiring board or interposer) having excellent reliability can be obtained.

    Further, the manufacturing process is shortened compared to the conventional method, and the cost of the multilayer circuit board can be reduced.

    Hereinafter, the manufacturing method of the multilayer circuit board of this invention is demonstrated.

Figure 1 (a) ~ (f) and FIG. 2 (g) ~ (n) , shows a schematic configuration partial sectional view showing an embodiment of a method for manufacturing a multilayer circuit board of the present invention in order of steps.

First, a plating base layer (21) is formed on an insulating base material (11) made of an epoxy resin by a method such as electroless copper plating (see FIG. 1 (a)).

Next, a photosensitive film (31) is formed by laminating a dry film on the plating base layer (21) (see FIG. 1B), and a series of patterning processes such as pattern exposure and development are performed . The resist pattern (31a) is formed (see FIG. 1C).

Next, electrolytic copper plating is performed using the first resist pattern (31a) as a mask to form a first conductor layer (41) having a predetermined thickness (see FIG. 1 (d)).

Next, a protruding conductor (51) having a predetermined shape is formed at a predetermined position on the base conductor layer (41) (see FIG. 1 (e)).

The protruding conductor (51) serves as a via for interlayer connection. As a forming method, a conductive paste is screen-printed, a solder ball is placed and heated and reflowed, or the conductive paste is pushed out by a dispenser. There is a way.

Next, electrolytic copper plating is performed using the first resist pattern (31a) as a mask, and an upper conductor layer (42) having a predetermined thickness is formed on the base conductor layer (41) and the protruding conductor (51). (See FIG. 1 (f)). The upper conductor layer (42) is formed to ensure the surface conductivity of the protruding conductor (51) .

Next, the first resist pattern (31a) is stripped with a dedicated stripping solution, the plating base layer (21) under the first resist pattern (31a) is removed by soft etching, and the lower wiring layer ( 43) and a protruding conductor (51a) having a conductor layer formed on the surface covered with the upper conductor layer (42) (see FIG. 2G).

Next, a resin sheet such as a prepreg is laminated on the insulating substrate (11 ) to form an insulating layer (61) having a predetermined thickness (see FIG. 2 (h)).

Next, the surface of the insulating layer (61) is polished to form a via-corresponding conductor (51b) in which a part of the upper portion of the protruding conductor (51a) having a conductor layer formed on the surface is exposed. (11) A via-corresponding conductor (51b) is formed on the lower wiring layer (43) (see FIG. 2 (i)).

Next, a plating catalyst is applied and electroless copper plating is performed to form a plating underlayer (particularly not shown), and a second resist pattern (32) and an opening (34) are formed by a known method . (See FIG. 2 (l) ), electrolytic copper plating is performed using the second resist pattern (32) as a mask to form a surface conductor layer (44) having a predetermined thickness ( see FIG. 2 (m) ).

Next, the second resist pattern (32) is stripped with a dedicated stripping solution, the plating base layer under the second resist pattern (32) is removed by flash etching, and the upper wiring layer (44a) is removed. And forming a two-layer printed wiring board and an interposer substrate in which the lower wiring layer (43) and the upper wiring layer (44a) are electrically connected by a conductor (51b) corresponding to a via (FIG. 2 (n)). reference).

Here, as for the example of the manufacturing method of the multilayer circuit board, the printed wiring board and the interposer board of the two-layer circuit board have been described, but a series of patterning processes such as pattern exposure and development described above are performed. repeatedly necessity times the surface conductor layer forming step of step through 2 to form a first resist pattern (k), after 2 (l), the (m) step, finally, FIG. 2 (n) By performing the resist pattern peeling process, a multilayer circuit board having a desired number of layers can be obtained.

    In the multilayer circuit board manufacturing method of the present invention, a protruding conductor is formed on a conductor layer, an insulating layer is formed, and then surface polishing is performed to expose the upper portion of the protruding conductor to form a via. Compared to the method of forming a via hole (opening) in the insulating layer on the conductor layer and filling the conductor hole by electrolytic copper plating, the conductor layer and the protruding conductor (equivalent to via) are superior. Electrical connection is obtained, and a multilayer circuit board (printed wiring board or interposer) having excellent reliability can be obtained.

    Further, the manufacturing process is shortened compared to the conventional method, and the cost of the multilayer circuit board can be reduced.

    Hereinafter, the present invention will be described in detail by way of examples.

First, the circuit board having wiring layers on both surfaces of the insulating base is formed (in particular, not shown) insulating layer (11) is formed by performing a plating catalyst application and electroless copper plating, plating underlying layer (21) was formed (see FIG. 1A).

Next, a dry film photoresist having a thickness of 12 μm is laminated on the surface of the plating base layer (21) to form a photosensitive layer (31) (see FIG. 1B), pattern exposure and development are performed, and the first The resist pattern (31a) was formed (see FIG. 1C).

Next, electrolytic copper plating was performed using the first resist pattern (31a) as a mask to form a 6 μm-thick underlying conductor layer (41) (see FIG. 1D).

Next, a solder ball having a diameter of 50 μm was placed on a predetermined position of the base conductor layer (41) with a dedicated ball bonder, and heated and melted to form a protruding conductor (51) (see FIG. 1 (e)). ).

Next, electrolytic copper plating was performed using the first resist pattern (31a) as a mask to form a 12 μm thick upper conductor layer (42) on the base conductor layer (41) and the protruding conductor (51) . (See FIG. 1 (f)).

Next, the first resist pattern (31a) is stripped with a dedicated stripping solution, and the plating base layer (21) located under the first resist pattern (31a) is removed by soft etching with an aqueous ammonium persulfate solution, A lower wiring layer (43) and a protruding conductor (51a) having a conductor layer formed on the surface were formed (see FIG. 2 (g)).

Next, the epoxy resin sheet was laminated with a vacuum pressurizing and heating laminator, and subsequently smoothed by a flat plate press to form an insulating layer (61) (see FIG. 2 (h)).

Next, the surface of the insulating layer (61) is polished 2 to 3 μm to form a via-corresponding conductor (51b) in which the upper part of the protruding conductor (51a) having a conductor layer formed on the surface is exposed, A conductor (51b) corresponding to a via was formed on the lower wiring layer (43) on the insulating substrate (11) (see FIG. 2 (i)).

Next, a plating catalyst is applied and electroless copper plating is performed to form a plating base layer (particularly not shown), and a second resist pattern (32) is formed by a known method (FIG. 2 (l)). Reference), electrolytic copper plating was performed using the second resist pattern (32) as a mask to form a 10 μm thick surface conductor layer (44) ( see FIG. 2 (m) ).

Next, the second resist pattern (32) is stripped with a special stripping solution, and the plating base layer under the second resist pattern (32) is removed by soft etching with an aqueous solution of ammonium persulfate to form an upper wiring layer. (44a) was formed, and a four-layer printed wiring board and an interposer substrate in which the lower wiring layer (43) and the upper wiring layer (44a) were electrically connected by the via-corresponding conductor (51b) were obtained ( ( See FIG. 2 (n) ).

(A)-(f) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board (printed wiring board or interposer) of this invention. (G)- (n) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board (printed wiring board or interposer) of this invention. (A)-(f) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the conventional multilayer circuit board (printed wiring board or interposer). (G)-(j) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the conventional multilayer circuit board (printed wiring board or interposer).

11, 111 ... Insulating substrate (insulating layer)
21, 121, plating underlayers 31, 131, photosensitive layers 31 a, 131 a, first resist pattern 32, 132, second resist pattern 41, base conductor layer 42,. upper base conductor layer 44 ... front conductive layer 141 ... lower conductive layer 142 ... upper conductor layer 43,141A ... lower wiring layer 44a, 142a ... upper wiring layer 51 ...... protruding conductor 51a ...... Projection-like conductor with a conductor layer formed on the surface 51b ...... Conductor equivalent to via 61, 151 ...... Insulating layer 61a ...... Polished insulating layer 143 ...... Via 152 ...... Via hole (opening) Part)

Claims (1)

In the manufacturing method of multilayer circuit boards, such as a printed wiring board and an interposer, the manufacturing method of a multilayer circuit board characterized by including the following processes.
(A) A step of forming a plating underlayer on the insulating substrate.
(B) A step of forming a photosensitive layer on the plating base layer .
(C) A step of forming a first resist pattern by performing a series of patterning processes such as pattern exposure and development.
(D) A step of performing electrolytic copper plating using the first resist pattern as a mask to form a base conductor layer on the plating base layer .
(E) A step of forming a protruding conductor at a predetermined position of the underlying conductor layer.
(F) A step of performing electrolytic copper plating using the first resist pattern as a mask to form a lower wiring layer made of a protruding conductor having an upper conductor layer formed on the surface .
(G) The first resist pattern is stripped, the plating base layer under the first resist pattern is removed by etching, and a lower wiring layer made of a protruding conductor having an upper conductor layer formed on the surface Forming.
(H) A step of forming an insulating layer.
(I) A step of polishing the surface of the insulating layer to form a via-corresponding conductor in which the upper part of the protruding conductor having a conductor layer formed on the surface is exposed.
(J) A step of forming a plating base layer and a photosensitive layer .
(K) A step of repeating the steps (c) to (j) as many times as necessary.
(L) A step of forming a second resist pattern by performing a series of patterning processes such as pattern exposure and development.
(M) A step of performing electrolytic copper plating using the second resist pattern as a mask to form a surface conductor layer on the plating base layer.
Finally, (n) a step of removing the second resist pattern, removing the plating base layer under the second resist pattern by etching, and forming an upper wiring layer on the polished insulating layer.

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