JP4476993B2 - プログラマブルロジックデバイスの広範なプログラマブル性のためのヘテロなトランシーバアーキテクチャ - Google Patents

プログラマブルロジックデバイスの広範なプログラマブル性のためのヘテロなトランシーバアーキテクチャ Download PDF

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Publication number
JP4476993B2
JP4476993B2 JP2006351009A JP2006351009A JP4476993B2 JP 4476993 B2 JP4476993 B2 JP 4476993B2 JP 2006351009 A JP2006351009 A JP 2006351009A JP 2006351009 A JP2006351009 A JP 2006351009A JP 4476993 B2 JP4476993 B2 JP 4476993B2
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channel
channels
bit rate
circuitry
clock signal
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Expired - Fee Related
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JP2006351009A
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Japanese (ja)
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JP2007282183A5 (enExample
JP2007282183A (ja
Inventor
シュマライエフ セルゲイ
ダブリュー． ベリョーザ ビル
エイチ． リー チョン
エイチ． パテル ラケシュ
ウォン ウィルソン
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Altera Corp
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Altera Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2006351009A 2006-04-11 2006-12-27 プログラマブルロジックデバイスの広範なプログラマブル性のためのヘテロなトランシーバアーキテクチャ Expired - Fee Related JP4476993B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/402,417 US7616657B2 (en) 2006-04-11 2006-04-11 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Publications (3)

Publication Number Publication Date
JP2007282183A JP2007282183A (ja) 2007-10-25
JP2007282183A5 JP2007282183A5 (enExample) 2010-02-12
JP4476993B2 true JP4476993B2 (ja) 2010-06-09

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JP2006351009A Expired - Fee Related JP4476993B2 (ja) 2006-04-11 2006-12-27 プログラマブルロジックデバイスの広範なプログラマブル性のためのヘテロなトランシーバアーキテクチャ

Country Status (4)

Country Link
US (3) US7616657B2 (enExample)
EP (1) EP1845622A3 (enExample)
JP (1) JP4476993B2 (enExample)
CN (2) CN102882512B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7903679B1 (en) 2006-04-11 2011-03-08 Altera Corporation Power supply filtering for programmable logic device having heterogeneous serial interface architecture
US8184651B2 (en) * 2008-04-09 2012-05-22 Altera Corporation PLD architecture optimized for 10G Ethernet physical layer solution
JP5272926B2 (ja) 2009-06-29 2013-08-28 富士通株式会社 データ送信回路
US8228102B1 (en) 2010-03-03 2012-07-24 Altera Corporation Phase-locked loop architecture and clock distribution system
US8406258B1 (en) 2010-04-01 2013-03-26 Altera Corporation Apparatus and methods for low-jitter transceiver clocking
JP5560867B2 (ja) 2010-04-12 2014-07-30 富士通株式会社 データ受信回路
FR2959636B1 (fr) * 2010-04-28 2012-07-13 Canon Kk Procede d'acces a une partie spatio-temporelle d'une sequence video d'images
US8397096B2 (en) * 2010-05-21 2013-03-12 Altera Corporation Heterogeneous physical media attachment circuitry for integrated circuit devices
US8488623B2 (en) * 2010-07-28 2013-07-16 Altera Corporation Scalable interconnect modules with flexible channel bonding
US8464088B1 (en) * 2010-10-29 2013-06-11 Altera Corporation Multiple channel bonding in a high speed clock network
US9191245B2 (en) 2011-03-08 2015-11-17 Tektronix, Inc. Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
US8855186B2 (en) * 2011-03-08 2014-10-07 Tektronix, Inc. Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
US8700825B1 (en) * 2012-11-16 2014-04-15 Altera Corporation Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system
US9348358B2 (en) 2014-04-18 2016-05-24 Fujitsu Limited Clock multiplication and distribution
US10158457B2 (en) * 2014-12-02 2018-12-18 Avago Technologies International Sales Pte. Limited Coordinating frequency division multiplexing transmissions
CN105807078A (zh) * 2016-03-15 2016-07-27 株洲南车时代电气股份有限公司 一种速度传感器接线方法
MY205935A (en) * 2021-09-23 2024-11-21 Skyechip Sdn Bhd An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650638B1 (en) * 2000-03-06 2003-11-18 Agilent Technologies, Inc. Decoding method and decoder for 64b/66b coded packetized serial data
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US6650140B2 (en) 2001-03-19 2003-11-18 Altera Corporation Programmable logic device with high speed serial interface circuitry
US6750675B2 (en) * 2001-09-17 2004-06-15 Altera Corporation Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
US20040042504A1 (en) * 2002-09-03 2004-03-04 Khoury John Michael Aligning data bits in frequency synchronous data channels
US6831480B1 (en) * 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
US6724328B1 (en) * 2003-06-03 2004-04-20 Altera Corporation Byte alignment for serial data receiver
US6946873B1 (en) * 2004-03-26 2005-09-20 Network Equipment Technologies, Inc. Method and system for recovering and aligning synchronous data of multiple phase-misaligned groups of bits into a single synchronous wide bus
CN100518045C (zh) * 2004-05-26 2009-07-22 中兴通讯股份有限公司 一种实现时钟互同步的方法
US8189729B2 (en) * 2005-08-03 2012-05-29 Altera Corporation Wide range and dynamically reconfigurable clock data recovery architecture
US7539278B2 (en) * 2005-12-02 2009-05-26 Altera Corporation Programmable transceivers that are able to operate over wide frequency ranges
US7411464B1 (en) * 2006-05-08 2008-08-12 Altera Corporation Systems and methods for mitigating phase jitter in a periodic signal

Also Published As

Publication number Publication date
EP1845622A3 (en) 2008-12-10
CN102882512B (zh) 2016-01-06
US7616657B2 (en) 2009-11-10
US20110211621A1 (en) 2011-09-01
US20070237186A1 (en) 2007-10-11
US20100058099A1 (en) 2010-03-04
US7940814B2 (en) 2011-05-10
US8787352B2 (en) 2014-07-22
CN101056100A (zh) 2007-10-17
JP2007282183A (ja) 2007-10-25
EP1845622A2 (en) 2007-10-17
CN102882512A (zh) 2013-01-16
CN101056100B (zh) 2012-12-05

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