JP2007282183A5 - - Google Patents

Download PDF

Info

Publication number
JP2007282183A5
JP2007282183A5 JP2006351009A JP2006351009A JP2007282183A5 JP 2007282183 A5 JP2007282183 A5 JP 2007282183A5 JP 2006351009 A JP2006351009 A JP 2006351009A JP 2006351009 A JP2006351009 A JP 2006351009A JP 2007282183 A5 JP2007282183 A5 JP 2007282183A5
Authority
JP
Japan
Prior art keywords
channel
bit rate
channels
locked loop
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006351009A
Other languages
English (en)
Japanese (ja)
Other versions
JP4476993B2 (ja
JP2007282183A (ja
Filing date
Publication date
Priority claimed from US11/402,417 external-priority patent/US7616657B2/en
Application filed filed Critical
Publication of JP2007282183A publication Critical patent/JP2007282183A/ja
Publication of JP2007282183A5 publication Critical patent/JP2007282183A5/ja
Application granted granted Critical
Publication of JP4476993B2 publication Critical patent/JP4476993B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2006351009A 2006-04-11 2006-12-27 プログラマブルロジックデバイスの広範なプログラマブル性のためのヘテロなトランシーバアーキテクチャ Expired - Fee Related JP4476993B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/402,417 US7616657B2 (en) 2006-04-11 2006-04-11 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Publications (3)

Publication Number Publication Date
JP2007282183A JP2007282183A (ja) 2007-10-25
JP2007282183A5 true JP2007282183A5 (enExample) 2010-02-12
JP4476993B2 JP4476993B2 (ja) 2010-06-09

Family

ID=37890767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006351009A Expired - Fee Related JP4476993B2 (ja) 2006-04-11 2006-12-27 プログラマブルロジックデバイスの広範なプログラマブル性のためのヘテロなトランシーバアーキテクチャ

Country Status (4)

Country Link
US (3) US7616657B2 (enExample)
EP (1) EP1845622A3 (enExample)
JP (1) JP4476993B2 (enExample)
CN (2) CN101056100B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7903679B1 (en) 2006-04-11 2011-03-08 Altera Corporation Power supply filtering for programmable logic device having heterogeneous serial interface architecture
US8184651B2 (en) * 2008-04-09 2012-05-22 Altera Corporation PLD architecture optimized for 10G Ethernet physical layer solution
JP5272926B2 (ja) 2009-06-29 2013-08-28 富士通株式会社 データ送信回路
US8228102B1 (en) 2010-03-03 2012-07-24 Altera Corporation Phase-locked loop architecture and clock distribution system
US8406258B1 (en) 2010-04-01 2013-03-26 Altera Corporation Apparatus and methods for low-jitter transceiver clocking
JP5560867B2 (ja) 2010-04-12 2014-07-30 富士通株式会社 データ受信回路
FR2959636B1 (fr) * 2010-04-28 2012-07-13 Canon Kk Procede d'acces a une partie spatio-temporelle d'une sequence video d'images
US8397096B2 (en) * 2010-05-21 2013-03-12 Altera Corporation Heterogeneous physical media attachment circuitry for integrated circuit devices
US8488623B2 (en) * 2010-07-28 2013-07-16 Altera Corporation Scalable interconnect modules with flexible channel bonding
US8464088B1 (en) * 2010-10-29 2013-06-11 Altera Corporation Multiple channel bonding in a high speed clock network
US9191245B2 (en) 2011-03-08 2015-11-17 Tektronix, Inc. Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
US8855186B2 (en) * 2011-03-08 2014-10-07 Tektronix, Inc. Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
US8700825B1 (en) * 2012-11-16 2014-04-15 Altera Corporation Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system
US9348358B2 (en) 2014-04-18 2016-05-24 Fujitsu Limited Clock multiplication and distribution
US10158457B2 (en) * 2014-12-02 2018-12-18 Avago Technologies International Sales Pte. Limited Coordinating frequency division multiplexing transmissions
CN105807078A (zh) * 2016-03-15 2016-07-27 株洲南车时代电气股份有限公司 一种速度传感器接线方法
MY205935A (en) * 2021-09-23 2024-11-21 Skyechip Sdn Bhd An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650638B1 (en) * 2000-03-06 2003-11-18 Agilent Technologies, Inc. Decoding method and decoder for 64b/66b coded packetized serial data
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US6650140B2 (en) 2001-03-19 2003-11-18 Altera Corporation Programmable logic device with high speed serial interface circuitry
US6750675B2 (en) * 2001-09-17 2004-06-15 Altera Corporation Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
US20040042504A1 (en) * 2002-09-03 2004-03-04 Khoury John Michael Aligning data bits in frequency synchronous data channels
US6831480B1 (en) * 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
US6724328B1 (en) * 2003-06-03 2004-04-20 Altera Corporation Byte alignment for serial data receiver
US6946873B1 (en) * 2004-03-26 2005-09-20 Network Equipment Technologies, Inc. Method and system for recovering and aligning synchronous data of multiple phase-misaligned groups of bits into a single synchronous wide bus
CN100518045C (zh) * 2004-05-26 2009-07-22 中兴通讯股份有限公司 一种实现时钟互同步的方法
US8189729B2 (en) 2005-08-03 2012-05-29 Altera Corporation Wide range and dynamically reconfigurable clock data recovery architecture
US7539278B2 (en) 2005-12-02 2009-05-26 Altera Corporation Programmable transceivers that are able to operate over wide frequency ranges
US7411464B1 (en) 2006-05-08 2008-08-12 Altera Corporation Systems and methods for mitigating phase jitter in a periodic signal

Similar Documents

Publication Publication Date Title
JP2007282183A5 (enExample)
CN101056100B (zh) 用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构
CN101512956B (zh) 用于高速lvds通信的同步的方法和设备
US9940298B2 (en) Signal conditioner discovery and control in a multi-segment data path
US8976846B2 (en) Wireless transmission system and wireless transmitter, wireless receiver, wireless transmission method, wireless reception method and wireless communication method used with same
EP1388975B1 (en) System and method for data transition control in a multirate communication system
US9965435B2 (en) Communication low-speed and high-speed parallel bit streams over a high-speed serial bus
KR100976114B1 (ko) 디지털 비디오 인터페이스 시스템, 데이터 통신 방법 및시스템
CN109154927A (zh) 低延时多协议重定时器
TW201606511A (zh) 用於晶片至晶片通信之系統及方法
TW201246816A (en) RF module control interface
US9419786B2 (en) Multi-lane serial link signal receiving system
JPWO2012147258A1 (ja) チャネル間スキュー調整回路
US20080192640A1 (en) Loopback Circuit
US7728625B1 (en) Serial interface for programmable logic devices
KR101585063B1 (ko) 외부 클락신호를 사용하지 않는 직렬 데이터 통신용 디바이스 phy
KR20160043319A (ko) Serdes 회로 구동 방법
KR101232057B1 (ko) 이중 모드 리시버
EP3161969B1 (en) Skew control for three-phase communication
ATA et al. Protocol Description
US20200120421A1 (en) Scrambling data-port audio in soundwire systems
FIFO Supported Features for PCIe Gen3
Handbook This chapter provides details about Stratix® IV GX and GT transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. f For information about upcoming Stratix IV device features, refer to the Upcoming
PCS et al. Supported Features for PCIe Configurations
Semiconductor High-speed serdes interfaces in high value fpgas