CN101056100B - 用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构 - Google Patents

用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构 Download PDF

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Publication number
CN101056100B
CN101056100B CN200710001930.9A CN200710001930A CN101056100B CN 101056100 B CN101056100 B CN 101056100B CN 200710001930 A CN200710001930 A CN 200710001930A CN 101056100 B CN101056100 B CN 101056100B
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Prior art keywords
channel
bit rate
clock signal
maximum bit
circuits system
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CN200710001930.9A
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Chinese (zh)
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CN101056100A (zh
Inventor
S·舒马拉耶夫
B·W·贝芮扎
C·H·李
R·H·帕特尔
W·王
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Intel Corp
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Altera Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
CN200710001930.9A 2006-04-11 2007-01-15 用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构 Active CN101056100B (zh)

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CN201210397425.1A CN102882512B (zh) 2006-04-11 2007-01-15 用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/402,417 US7616657B2 (en) 2006-04-11 2006-04-11 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
US11/402,417 2006-04-11

Related Child Applications (1)

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CN201210397425.1A Division CN102882512B (zh) 2006-04-11 2007-01-15 用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构

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CN101056100A CN101056100A (zh) 2007-10-17
CN101056100B true CN101056100B (zh) 2012-12-05

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CN200710001930.9A Active CN101056100B (zh) 2006-04-11 2007-01-15 用于可编程逻辑器件的宽范围可编程能力的异构收发器体系结构

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US (3) US7616657B2 (enExample)
EP (1) EP1845622A3 (enExample)
JP (1) JP4476993B2 (enExample)
CN (2) CN102882512B (enExample)

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* Cited by examiner, † Cited by third party
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US7903679B1 (en) 2006-04-11 2011-03-08 Altera Corporation Power supply filtering for programmable logic device having heterogeneous serial interface architecture
US8184651B2 (en) * 2008-04-09 2012-05-22 Altera Corporation PLD architecture optimized for 10G Ethernet physical layer solution
JP5272926B2 (ja) 2009-06-29 2013-08-28 富士通株式会社 データ送信回路
US8228102B1 (en) 2010-03-03 2012-07-24 Altera Corporation Phase-locked loop architecture and clock distribution system
US8406258B1 (en) 2010-04-01 2013-03-26 Altera Corporation Apparatus and methods for low-jitter transceiver clocking
JP5560867B2 (ja) 2010-04-12 2014-07-30 富士通株式会社 データ受信回路
FR2959636B1 (fr) * 2010-04-28 2012-07-13 Canon Kk Procede d'acces a une partie spatio-temporelle d'une sequence video d'images
US8397096B2 (en) * 2010-05-21 2013-03-12 Altera Corporation Heterogeneous physical media attachment circuitry for integrated circuit devices
US8488623B2 (en) * 2010-07-28 2013-07-16 Altera Corporation Scalable interconnect modules with flexible channel bonding
US8464088B1 (en) * 2010-10-29 2013-06-11 Altera Corporation Multiple channel bonding in a high speed clock network
US9191245B2 (en) 2011-03-08 2015-11-17 Tektronix, Inc. Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
US8855186B2 (en) * 2011-03-08 2014-10-07 Tektronix, Inc. Methods and systems for providing optimum decision feedback equalization of high-speed serial data links
US8700825B1 (en) * 2012-11-16 2014-04-15 Altera Corporation Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system
US9348358B2 (en) 2014-04-18 2016-05-24 Fujitsu Limited Clock multiplication and distribution
US10158457B2 (en) * 2014-12-02 2018-12-18 Avago Technologies International Sales Pte. Limited Coordinating frequency division multiplexing transmissions
CN105807078A (zh) * 2016-03-15 2016-07-27 株洲南车时代电气股份有限公司 一种速度传感器接线方法
MY205935A (en) * 2021-09-23 2024-11-21 Skyechip Sdn Bhd An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1248372A2 (en) * 2001-03-19 2002-10-09 Altera Corporation (a Delaware Corporation) Programmable logic device with high speed serial interface circuitry
US6650638B1 (en) * 2000-03-06 2003-11-18 Agilent Technologies, Inc. Decoding method and decoder for 64b/66b coded packetized serial data
US6724328B1 (en) * 2003-06-03 2004-04-20 Altera Corporation Byte alignment for serial data receiver
US6750675B2 (en) * 2001-09-17 2004-06-15 Altera Corporation Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
US6831480B1 (en) * 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
CN1585273A (zh) * 2004-05-26 2005-02-23 中兴通讯股份有限公司 一种实现时钟互同步的方法
US6946873B1 (en) * 2004-03-26 2005-09-20 Network Equipment Technologies, Inc. Method and system for recovering and aligning synchronous data of multiple phase-misaligned groups of bits into a single synchronous wide bus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US20040042504A1 (en) * 2002-09-03 2004-03-04 Khoury John Michael Aligning data bits in frequency synchronous data channels
US8189729B2 (en) * 2005-08-03 2012-05-29 Altera Corporation Wide range and dynamically reconfigurable clock data recovery architecture
US7539278B2 (en) * 2005-12-02 2009-05-26 Altera Corporation Programmable transceivers that are able to operate over wide frequency ranges
US7411464B1 (en) * 2006-05-08 2008-08-12 Altera Corporation Systems and methods for mitigating phase jitter in a periodic signal

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650638B1 (en) * 2000-03-06 2003-11-18 Agilent Technologies, Inc. Decoding method and decoder for 64b/66b coded packetized serial data
EP1248372A2 (en) * 2001-03-19 2002-10-09 Altera Corporation (a Delaware Corporation) Programmable logic device with high speed serial interface circuitry
US6750675B2 (en) * 2001-09-17 2004-06-15 Altera Corporation Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
US6831480B1 (en) * 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
US6724328B1 (en) * 2003-06-03 2004-04-20 Altera Corporation Byte alignment for serial data receiver
US6946873B1 (en) * 2004-03-26 2005-09-20 Network Equipment Technologies, Inc. Method and system for recovering and aligning synchronous data of multiple phase-misaligned groups of bits into a single synchronous wide bus
CN1585273A (zh) * 2004-05-26 2005-02-23 中兴通讯股份有限公司 一种实现时钟互同步的方法

Also Published As

Publication number Publication date
EP1845622A3 (en) 2008-12-10
CN102882512B (zh) 2016-01-06
US7616657B2 (en) 2009-11-10
JP4476993B2 (ja) 2010-06-09
US20110211621A1 (en) 2011-09-01
US20070237186A1 (en) 2007-10-11
US20100058099A1 (en) 2010-03-04
US7940814B2 (en) 2011-05-10
US8787352B2 (en) 2014-07-22
CN101056100A (zh) 2007-10-17
JP2007282183A (ja) 2007-10-25
EP1845622A2 (en) 2007-10-17
CN102882512A (zh) 2013-01-16

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Effective date of registration: 20220906

Address after: California, USA

Patentee after: INTEL Corp.

Address before: California, USA

Patentee before: Altera Corp.