JP4476064B2 - 多数個取り電子部品収納用パッケージおよび電子装置 - Google Patents
多数個取り電子部品収納用パッケージおよび電子装置 Download PDFInfo
- Publication number
- JP4476064B2 JP4476064B2 JP2004220833A JP2004220833A JP4476064B2 JP 4476064 B2 JP4476064 B2 JP 4476064B2 JP 2004220833 A JP2004220833 A JP 2004220833A JP 2004220833 A JP2004220833 A JP 2004220833A JP 4476064 B2 JP4476064 B2 JP 4476064B2
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- JP
- Japan
- Prior art keywords
- ceramic
- layer
- main surface
- electronic component
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Description
2:電子部品収納用パッケージ
2a:凹部
2b:配線導体
2c:内部導体
3:分割溝
5:メタライズ層
5a:上部メタライズ層
5b:下部メタライズ層
6:セラミック層
6a:上部セラミック層
6b:下部セラミック層
7:蓋体
8:電子部品
Claims (3)
- 上側主面及び下側主面に複数の区画に区分する分割溝がそれぞれ形成されるとともに、前記各区画の中央部に電子部品を収容するための凹部が形成されたセラミック母基板と、
前記凹部の周辺部に形成された上部メタライズ層と、
前記凹部の底面に形成されるとともに電子部品に電気的に接続される配線導体と、
前記セラミック母基板の下側主面の前記各区画に形成された下部メタライズ層と、
前記配線導体と前記下部メタライズ層とを電気的に接続する内部導体と、を具備してなる多数個取り電子部品収納用パッケージであって、
前記分割溝の内面から前記主面の前記分割溝の周囲にかけて前記セラミック母基板と同じ材質のセラミック層が形成され、前記セラミック層における前記分割溝の周囲に形成された部分が、前記上部メタライズ層及び前記下部メタライズ層よりもそれぞれ前記主面上に突出していることを特徴とする多数個取り電子部品収納用パッケージ。 - 前記上部メタライズ層及び下部メタライズ層の一部が、前記セラミック層により被覆されていることを特徴とする請求項1に記載の多数個取り電子部品収納用パッケージ。
- 請求項1又は2に記載の多数個取り電子部品収納用パッケージと、前記凹部に収容されて前記配線導体に電気的に接続された電子部品と、前記セラミック母基板の上側主面の前記各凹部を覆うようにそれぞれ取着された蓋体とを具備して成る多数個取り電子装置を前記分割溝に沿って分割して成ることを特徴とする電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004220833A JP4476064B2 (ja) | 2004-07-28 | 2004-07-28 | 多数個取り電子部品収納用パッケージおよび電子装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004220833A JP4476064B2 (ja) | 2004-07-28 | 2004-07-28 | 多数個取り電子部品収納用パッケージおよび電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041286A JP2006041286A (ja) | 2006-02-09 |
JP4476064B2 true JP4476064B2 (ja) | 2010-06-09 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004220833A Expired - Fee Related JP4476064B2 (ja) | 2004-07-28 | 2004-07-28 | 多数個取り電子部品収納用パッケージおよび電子装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4476064B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4646825B2 (ja) * | 2006-02-22 | 2011-03-09 | 京セラ株式会社 | 多数個取り配線基板 |
JP2012009767A (ja) * | 2009-11-27 | 2012-01-12 | Kyocera Corp | 多数個取り配線基板およびその製造方法、ならびに配線基板およびその製造方法 |
JP6129491B2 (ja) * | 2012-08-06 | 2017-05-17 | Ngkエレクトロデバイス株式会社 | 多数個取り配線基板 |
JP6417056B2 (ja) | 2016-01-22 | 2018-10-31 | 京セラ株式会社 | 電子部品収納用パッケージ、多数個取り配線基板、電子装置および電子モジュール |
CN115884526B (zh) * | 2022-09-06 | 2023-09-15 | 珠海越亚半导体股份有限公司 | 一种高散热混合基板制作方法及半导体结构 |
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2004
- 2004-07-28 JP JP2004220833A patent/JP4476064B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2006041286A (ja) | 2006-02-09 |
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