JP4461873B2 - Zinc oxide processing method and thin film transistor manufacturing method - Google Patents

Description

The present invention relates to a method for processing zinc oxide and a method for manufacturing a thin film transistor .

  For example, in a thin film transistor, a gate electrode is provided on the upper surface of an insulating substrate, a gate insulating film is provided on the upper surface of the insulating substrate including the gate electrode, and a semiconductor thin film made of intrinsic amorphous silicon on the upper surface of the gate insulating film on the gate electrode. A channel protective film is provided in the center of the upper surface of the semiconductor thin film, and a contact layer made of n-type amorphous silicon is provided on both sides of the upper surface of the channel protective film and on the upper surface of the semiconductor thin film on both sides of the channel protective film. Are provided with source / drain electrodes (for example, see Patent Document 1).

Japanese Patent Laid-Open No. 5-67786 (FIG. 2)

  Recently, instead of amorphous silicon, higher mobility can be obtained, and therefore it is considered to use zinc oxide (ZnO). As a method of manufacturing such a thin film transistor using zinc oxide, for example, a semiconductor thin film forming layer made of intrinsic zinc oxide is formed on a gate insulating film, and silicon nitride is formed on the upper surface of the semiconductor thin film forming layer. Forming a channel protective film to be a pattern, forming a contact layer forming layer made of n-type zinc oxide on the upper surface of the semiconductor thin film forming layer including the channel protective film, and then forming the contact layer forming layer and the semiconductor thin film The contact layer and the semiconductor thin film are formed in the device area by continuously patterning the working layer using dilute acetic acid, and then the source / drain electrode forming layer made of chromium is formed thereon, and then the source It is conceivable to form the source / drain electrodes by patterning the drain electrode forming layer using a chromium etching solution.

  However, in the above manufacturing method, since the etching solution for chromium exhibits an excessively high etching rate with respect to the semiconductor thin film and the contact layer made of zinc oxide formed in the device area, the etching solution for zinc is formed from the zinc oxide formed in the device area. It has been found that relatively large side etching occurs in the resulting semiconductor thin film and contact layer, resulting in poor processing accuracy.

Therefore, an object of the present invention is to provide a zinc oxide processing method and a thin film transistor manufacturing method capable of improving processing accuracy.

In order to achieve the above object, the present invention is characterized in that a zinc oxide layer formed on a substrate is etched using an alkaline developer or using dilute acetic acid under special conditions.

According to this invention, excessive etching of the zinc oxide layer is suppressed by etching the zinc oxide layer formed on the substrate using an alkaline developer or using dilute acetic acid under special conditions. In addition, side etching is less likely to occur in the zinc oxide layer formed in the device area, and as a result, the processing accuracy can be improved.

(First embodiment)
FIG. 1 shows a cross-sectional view of a thin film transistor having a zinc oxide layer formed by the zinc oxide processing method according to the first embodiment of the present invention. In this thin film transistor, a gate electrode 2 made of chromium, aluminum or the like is provided on the upper surface of an insulating substrate 1 made of glass or the like. A gate insulating film 3 made of silicon nitride is provided on the upper surface of the insulating substrate 1 including the gate electrode 2. A semiconductor thin film 4 made of intrinsic zinc oxide is provided on the upper surface of the gate insulating film 3 on the gate electrode 2.

  A channel protective film 5 made of silicon nitride is provided at substantially the center of the upper surface of the semiconductor thin film 4. Contact layers 6 made of n-type zinc oxide are provided on both sides of the upper surface of the channel protective film 5 and on the upper surface of the semiconductor thin film 4 on both sides thereof. A source / drain electrode 7 made of an aluminum-based metal such as aluminum or an aluminum alloy (for example, an Al—Nd—Ti alloy) is provided on the upper surface of each contact layer 6. Here, the peripheral side surfaces 4a, 6a and 7a of the semiconductor thin film 4, the contact layer 6 and the source / drain electrode 7 are inclined surfaces inclined at a certain angle.

  Next, an example of a method for manufacturing this thin film transistor will be described. First, as shown in FIG. 2, a gate electrode 2 is formed by patterning a metal layer made of aluminum, chromium, or the like formed by sputtering on the upper surface of an insulating substrate 1 made of glass or the like. Next, a gate insulating film 3 made of silicon nitride, a semiconductor thin film forming layer 11 made of intrinsic zinc oxide, and a channel protective film forming layer made of silicon nitride are formed on the upper surface of the insulating substrate 1 including the gate electrode 2 by plasma CVD. 12 are continuously formed. Next, the channel protective film 5 is formed by patterning the channel protective film forming layer 12.

  Next, as shown in FIG. 3, a contact layer forming layer 13 made of n-type zinc oxide is formed on the upper surface of the semiconductor thin film forming layer 11 including the channel protective film 5 by plasma CVD. Next, the source / drain electrode forming layer 14 made of an aluminum-based metal is formed on the upper surface of the contact layer forming layer 13 by sputtering. Next, a positive resist layer 15 is formed on the entire upper surface of the source / drain electrode forming layer 14 by screen printing, spin coating, or the like.

  Here, the thickness of the semiconductor thin film forming layer 11 is about 1000 mm, the thickness of the contact layer forming layer 13 is about 500 mm, the thickness of the source / drain electrode forming layer 14 is about 3300 mm, and the resist layer 15 The film thickness was about 1.5 μm. In this case, the photoresist for forming the resist layer 15 is a positive resist (for example, Nagase positive resist 35102) containing 2-ethoxyethyl acetate as a main component and containing a cresol novolac resin and a naphthoquinone diad compound.

  Next, the resist layer 15 is exposed using an exposure mask (not shown) having a light-shielding portion in a region corresponding to the designed source / drain formation region, and the resist layer is shown in FIG. An area outside the source / drain formation region 15 is defined as an exposure region 15a. Next, the state shown in FIG. 3 is accommodated in a developing device or an etching device, and the resist developer is 95 to 99 wt% water and 2.38 wt% tetramethylammonium hydroxide (for example, Nagase Positive Developer). When development is performed using NPD-1), the exposed region 15a is removed from the resist layer 15, and a resist pattern 15b composed of an unexposed region is formed in a region corresponding to the designed source / drain formation region. .

  Next, when the development process is continued, that is, in the same apparatus, using the resist developer with the resist pattern 15b as a mask, the source / drain electrode forming layer 14, the contact layer forming layer 13, and the semiconductor When the thin film forming layer 11 is continuously etched in the same apparatus, it is as shown in FIG. That is, when the resist developer is used, the aluminum-based metal layer and the zinc oxide layer can be etched. However, in this case, since the resist pattern 15b is also etched to some extent, the peripheral side surface 15c of the resist pattern 15b recedes inward, and the peripheral side surface 15c becomes an inclined surface inclined at a certain angle.

  As the resist pattern 15b recedes toward the inner side of the peripheral side surface 15c, the peripheral side surface 7a of the source / drain electrode 7 also recedes inward, and the peripheral side surface 7a also becomes an inclined surface inclined at an angle. . Further, the peripheral side surface 6a of the contact layer 6 also recedes inward, and the peripheral side surface 6a also becomes an inclined surface inclined at an angle. Further, the peripheral side surface 4a of the semiconductor thin film 4 also recedes inward, and the peripheral side surface 4a also becomes an inclined surface inclined at an angle. Thereafter, when the resist pattern 15b is peeled off, the thin film transistor shown in FIG. 1 is obtained.

  In the thin film transistor thus obtained, the source / drain electrode forming layer 14, the contact layer forming layer 13 and the semiconductor thin film forming layer 11 made of a metal that can be etched by the resist developer are used as the resist developer. Since the etching is continuously performed in the same apparatus, the source / drain electrode 7, the contact layer 6, and the peripheral side surfaces 7 a and 6 a of the semiconductor thin film 4 are moved along with the receding toward the inner side of the peripheral side surface 15 c of the resist pattern 15 b. 4a recedes inward, and the peripheral side surfaces 7a, 6a, 4a become inclined surfaces inclined at a certain angle, thereby suppressing excessive etching of the contact layer 6 and the semiconductor thin film 4; and Side etching can be made difficult to occur in the contact layer 6 and the semiconductor thin film 4, , It is possible to improve the machining accuracy.

  Incidentally, when the resist developer was used as an etching solution, the etching rate ratio of resist: Al: zinc oxide was 25: 4 to 5: 1 to 0.7. On the other hand, when etching with an etching solution for aluminum, the resist is hardly etched, and the ratio of the etching rate of Al: zinc oxide is approximately 1.2: 1. Therefore, when the Al-based metal is etched using the resist developer as an etching solution, the side etching amount of the zinc oxide film under the Al-based metal is 1/4 to less than that when etching with the aluminum etching solution. It can be reduced to about 1/5. In the above, when the etching rate for the resist developer is larger than that of zinc oxide in the metal layer, the edge portion on the metal layer interface side of zinc oxide does not enter the inside of the metal layer. It is desirable to use such a metal material because it is possible to eliminate the problem of being broken and becoming a foreign object.

  However, in this case, the source / drain electrode forming layer 14, the contact layer forming layer 13 and the semiconductor thin film forming layer 11 are continuously etched in the same apparatus from the beginning using the resist developer. Therefore, the retreat amount toward the inside of the peripheral side surface 15c of the resist pattern 15b is relatively large, and the side etching amount of the semiconductor thin film 4 and the contact layer 6 that are actually formed increases. For example, if the time for etching the source / drain electrode 7 made of Al-based metal with a thickness of 3300 μm using the resist developer is 12 minutes and 30 seconds, the edge of the resist layer 15 is approximately 1.5 μm. fall back. As the resist layer 15 recedes, the amount by which the edge portions of the source / drain electrodes 7, the semiconductor thin film 4 and the contact layer 6 recede, that is, the side etching amount increases. Therefore, a second embodiment of the present invention that can reduce the side etching amount of the semiconductor thin film 4 and the contact layer 6 that are actually formed will now be described.

(Second Embodiment)
FIG. 5 shows a sectional view of a thin film transistor provided with a zinc oxide layer formed by the zinc oxide processing method according to the second embodiment of the present invention. In this thin film transistor, the difference from the case shown in FIG. 1 is that the amount of receding toward the inside of the peripheral side surfaces 7a, 6a and 4a of the source / drain electrode 7, the contact layer 6 and the semiconductor thin film 4 is somewhat larger than that shown in FIG. It is a point which decreases and the inclination angle of these peripheral side surfaces 7a, 6a, 4a is somewhat larger than the case shown in FIG.

  Next, an example of a method for manufacturing this thin film transistor will be described. In this case, after forming the resist pattern 15b as shown in FIG. 3, the source / drain electrode forming layer 14 is half-etched using an etching solution for aluminum with the resist pattern 15b as a mask as shown in FIG. Thus, the thickness of the source / drain electrode formation layer 14a in the region other than the region under the resist pattern 15b is reduced. In this case, the etching solution for aluminum used was 9.6 wt% nitric acid, 6.0 wt% acetic acid, 67.0 wt% phosphoric acid, and 17.4 wt% water. In this aluminum etching solution, the resist pattern 15b is hardly etched and is maintained at the designed size.

  For example, when the source / drain electrode forming layer 14 made of an Al-based metal having a thickness of 3300 mm is etched using an etching solution for aluminum, the entire thickness is etched in about 50 seconds, but the entire thickness is etched. A little before, for example, the etching time is set to 30 to 45 seconds, and the etching process is finished in a state where about 40 to 10% of the film thickness remains. In this state, the peripheral side surface 14b of the source / drain electrode forming layer 14 under the resist pattern 15b is a steeply inclined surface.

  Next, using the resist developer with the resist pattern 15b as a mask, the source / drain electrode forming layer 14a, the contact layer forming layer 13 and the semiconductor thin film forming layer 11 in the region other than the region below the resist pattern 15b are made identical. When continuously etched in the apparatus, the result is as shown in FIG. Also in this case, the resist pattern 15b is slightly etched. However, since the film thickness of the source / drain electrode forming layer 14a in the region other than the region under the resist pattern 15b is thinned in advance, the etching time is correspondingly increased. As a result, the amount of receding toward the inside of the peripheral side surface 15c of the resist pattern 15b is reduced to some extent as compared to the case shown in FIG. 4, and the inclination angle of the peripheral side surface 15c becomes somewhat larger than that shown in FIG.

  That is, if the source / drain electrode forming layer 14 remains in a state where about 40 to 10% of the original film thickness remains, the etching time using the resist developer is the resist development over the entire film thickness. Compared to the case of etching using a liquid, the amount is reduced to about 40 to 10%. Therefore, the amount of side etching of the source / drain electrode 7, the contact layer 6 and the semiconductor thin film 4 can be reduced accordingly. it can. Thereafter, when the resist pattern 15b is peeled off, the thin film transistor shown in FIG. 5 is obtained.

  In the thin film transistor thus obtained, the amount of receding toward the inside of the peripheral side surfaces 7a, 6a and 4a of the source / drain electrode 7, the contact layer 6 and the semiconductor thin film 4 is reduced to some extent as compared with the case shown in FIG. Since the inclination angles of these peripheral side surfaces 7a, 6a, 4a are somewhat larger than those shown in FIG. 1, the sizes of the semiconductor thin film 4 and the contact layer 6 that are actually formed can be brought close to the designed sizes. . By the way, it is possible to make the sizes of the semiconductor thin film 4 and the contact layer 6 actually formed closer to the designed size. Next, the sizes of the semiconductor thin film 4 and the contact layer 6 actually formed are set next. A third embodiment of the present invention that can be brought closer to the design size will be described.

(Third embodiment)
FIG. 8 shows a cross-sectional view of a thin film transistor provided with a zinc oxide layer formed by the zinc oxide processing method according to the third embodiment of the present invention. In this thin film transistor, the difference from the case shown in FIG. 5 is that the amount of receding toward the inside of the peripheral side surface 7a of the source / drain electrode 7 is further reduced as compared with the case shown in FIG. The amount of retreat toward the inside of the peripheral side surfaces 4a and 6a is further reduced as compared with the case shown in FIG.

  Next, an example of a method for manufacturing this thin film transistor will be described. In this case, as shown in FIG. 6, after thinning the film thickness of the source / drain electrode forming layer 14a in the region other than the region under the resist pattern 15b, the resist pattern 15b is used as a mask and the resist developer is used. The source / drain electrode forming layer 14a in the region other than under the pattern 15b is removed by etching, and the etching process using the resist developer is continued as it is. As shown in FIG. 13 is half-etched, and the process is completed in a state where the film thickness of the contact layer forming layer 13 in the region other than the region under the source / drain electrode 7 is reduced.

  However, in this case as well, the resist pattern 15b is slightly etched. In this case, the etching time is such that the source / drain electrode forming layer 14a is removed by etching in a region other than the region under the resist pattern 15b, followed by contact. Since the time is short enough to half-etch the layer forming layer 13, the amount of recession of the resist pattern 15b toward the inner side of the peripheral side surface 15c is further reduced, and the inclination angle of the peripheral side surface 15c is shown in FIG. It will be somewhat larger than the case.

  As the amount of receding toward the inside of the peripheral side surface 15c of the resist pattern 15b further decreases, the amount of receding toward the inside of the peripheral side surface 7a of the source / drain electrode 7 further decreases, and this peripheral side surface 7a. Is somewhat larger than the case shown in FIG. Further, the amount of receding toward the inner side of the peripheral side surface 13b of the contact layer forming layer 13 below the source / drain electrode 7 is further reduced, and the inclination angle of the peripheral side surface 13b is somewhat larger than that shown in FIG. Become.

  Next, using the resist pattern 15b as a mask, the contact layer forming layer 13a and the semiconductor thin film forming layer in regions other than the source / drain electrode forming layer 7 using dilute acetic acid (1 to 0.5 wt% aqueous solution of acetic acid) When 11 is continuously etched in the same apparatus, it becomes as shown in FIG. In this case, the resist pattern 15b and the source / drain electrodes 7 are hardly etched with the dilute acetic acid. Accordingly, in the state shown in FIG. 9, the contact layer forming layer 13 and the semiconductor thin film forming layer 11 in the region other than the region below the source / drain electrode 7 are removed by etching. As shown in FIG. 7, the contact layer 6 and the semiconductor thin film 4 are formed, and the peripheral side surfaces 6a and 4a are steeply inclined surfaces. Thereafter, when the resist pattern 15b is peeled off, the thin film transistor shown in FIG. 8 is obtained.

  In the thin film transistor thus obtained, the retreat amount of the source / drain electrode 7 toward the inner side of the peripheral side surface 15c is further reduced, and the inclination angle of the peripheral side surface 15c is somewhat larger than that shown in FIG. Since the peripheral side surfaces 6a and 4a of the contact layer 6 and the semiconductor thin film 4 formed under the source / drain electrodes 7 become steeply inclined surfaces, the sizes of the actually formed semiconductor thin film 4 and the contact layer 6 are designed. You can get closer to the size above. Moreover, since the etching rate of the diluted acetic acid with respect to zinc oxide is about 1000 kg / min, the etching time with the diluted acetic acid can be made shorter than the etching time with the resist developer.

(Fourth embodiment)
In the third embodiment, the case where the size of the semiconductor thin film 4 and the contact layer 6 can be made closer to the design size has been described. Next, the size of the semiconductor thin film 4 and the contact layer 6 is changed to the design size. A fourth embodiment of the present invention that can be further approximated to will be described.

  FIG. 11 is a sectional view of a thin film transistor provided with a zinc oxide layer formed by the zinc oxide processing method according to the fourth embodiment of the present invention. In this thin film transistor, the main difference from the case shown in FIG. 8 is that a second source / drain electrode 8 made of chromium is provided on the upper surface of the first source / drain electrode 7 made of aluminum. In this case, the peripheral side surface 7a of the first source / drain electrode 7 is inclined to some extent, but the peripheral side surface 8a of the second source / drain electrode 8 is steeply inclined.

  Next, an example of a method for manufacturing this thin film transistor will be described. In this case, as shown in FIG. 3, after the first source / drain electrode formation layer 14 made of aluminum is formed, the upper surface of the first source / drain electrode formation layer 14 is formed as shown in FIG. Then, a second source / drain electrode forming layer 16 made of chromium is formed by sputtering, and then corresponds to the designed source / drain forming region on the upper surface of the second source / drain electrode forming layer 16. A resist pattern 15b is formed in the region. In this case, the thickness of the semiconductor thin film forming layer 11 is about 1000 mm, the thickness of the contact layer forming layer 13 is about 500 mm, the thickness of the first source / drain electrode forming layer 14 is about 3300 mm, The film thickness of the second source / drain electrode formation layer 16 was about 1000 mm, and the film thickness of the resist layer 15 was about 1.5 μm.

  Next, when the second source / drain electrode forming layer 16 is etched by using the resist pattern 15b as a mask and a chromium etching solution, the second source / drain is formed below the resist pattern 15b as shown in FIG. Electrode 8 is formed. In this case, the etching solution for chromium was 9.6 wt% nitric acid, 6.0 wt% acetic acid, 67.0 wt% phosphoric acid, and 17.4 wt% water. In this chromium etching solution, the resist pattern 15b is hardly etched and is maintained at the designed size. Therefore, in this state, the peripheral side surface 8a of the second source / drain electrode 8 under the resist pattern 15b is a steeply inclined surface.

  Next, using the resist developer using the resist pattern 15b as a mask, the first source / drain electrode forming layer 14, the contact layer forming layer 13 and the semiconductor thin film forming layer 11 are continuously formed in the same apparatus. Then, the etching is as shown in FIG. Also in this case, since the resist pattern 15b is slightly etched, the peripheral side surface 15c of the resist pattern 15b recedes inward as in the case shown in FIG. 4, and the peripheral side surface 15c is inclined at an angle. It becomes a surface. However, in this case, the second source / drain electrode 8 made of chromium is hardly etched by the resist developer. Therefore, in this case, the second source / drain electrode 8 functions as an etching mask.

  Then, even if the peripheral side surface 15c of the resist pattern 15b recedes relatively inward as in the case shown in FIG. 4, the second source / drain electrode 8 functions as an etching mask, so that the first The amount of receding toward the inner side of the peripheral side surface 7a of the source / drain electrode 7, that is, the side etching amount is smaller than that shown in FIG. This reduces the amount of side etching of the contact layer 6 and the peripheral side surfaces 6a and 4a of the semiconductor thin film 4 formed under the first source / drain electrode 7, and the size of the contact layer 6 and the semiconductor thin film 4 is designed. You can get closer to the size. Thereafter, when the resist pattern 15b is peeled off, the thin film transistor shown in FIG. 11 is obtained.

  In the thin film transistor thus obtained, the second source / drain electrode 8 made of chromium is hardly etched by the resist developer and functions as an etching mask. Even if the peripheral side surface 7a of the first source / drain electrode 7 to be formed is slightly retracted inward, the contact layer 6 formed under the first source / drain electrode 7 and the peripheral side surface 6a of the semiconductor thin film 4 are formed. 4a becomes a steep inclined surface, and the size of the contact layer 6 and the semiconductor thin film 4 can be brought close to the designed size.

(Other embodiments)
After the step shown in FIG. 13, as shown in FIG. 6, the first source / drain electrode forming layer 14 is half-etched using the aluminum etching solution, and then left using the resist developer. The thin first source / drain electrode forming layer 14a, the contact layer forming layer 13 and the semiconductor thin film forming layer 11 may be continuously etched in the same apparatus.

  Further, after the step shown in FIG. 13, as shown in FIG. 6, the first source / drain electrode formation layer 14 is half-etched using the aluminum etching solution, and then the resist developing solution is used. Then, the remaining first source / drain electrode forming layer 14a of the thin film is removed by etching. Subsequently, as shown in FIG. 9, the contact layer forming layer 13 is half-etched, and then the diluted acetic acid is removed. The remaining thin film contact layer forming layer 13a and the semiconductor thin film forming layer 11 may be continuously etched in the same apparatus.

  In the above embodiment, the thin film transistor in which the zinc oxide layer is a semiconductor layer is described. However, the present invention is not limited to the case in which zinc oxide is a semiconductor layer. The present invention can be widely applied to the case where a zinc oxide film is formed and patterned by etching.

Sectional drawing of the thin-film transistor provided with the zinc oxide layer formed by the processing method of the zinc oxide as 1st Embodiment of this invention. Sectional drawing of an original process in the case of manufacture of the thin-film transistor shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the thin-film transistor provided with the zinc oxide layer formed by the processing method of the zinc oxide as 2nd Embodiment of this invention. Sectional drawing of a predetermined | prescribed process in the case of manufacture of the thin-film transistor shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the thin-film transistor provided with the zinc oxide layer formed by the processing method of the zinc oxide as 3rd Embodiment of this invention. Sectional drawing of a predetermined | prescribed process in the case of manufacture of the thin-film transistor shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the thin-film transistor provided with the zinc oxide layer formed by the processing method of the zinc oxide as 1st Embodiment of this invention. Sectional drawing of a predetermined | prescribed process in the case of manufacture of the thin-film transistor shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Gate electrode 3 Gate insulating film 4 Semiconductor thin film 5 Channel protective film 6 Contact layer 7 Source / drain electrode 11 Semiconductor thin film forming layer 13 Contact layer forming layer 14 Source / drain electrode forming layer 15 Resist layer 15b Resist pattern

Claims (13)

Forming a zinc oxide layer on the substrate, forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer, and forming a resist layer on the metal layer; the the step of the resist layer forming a resist pattern by etching using the alkaline developer, the resist pattern in the same apparatus the metal layer and the zinc oxide layer by using the alkaline developer as a mask And a step of continuously etching the zinc oxide. 2. The zinc oxide processing method according to claim 1, wherein the alkaline developer contains tetramethylammonium hydroxide . 3. The zinc oxide processing method according to claim 2, wherein the etching rate by the alkaline developer is higher in the metal layer than in the zinc oxide layer. Forming a zinc oxide layer on the substrate, forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer, and forming a resist layer on the metal layer; Etching the resist layer with an alkaline developer to form a resist pattern, and half-etching the metal layer with a metal etchant using the resist pattern as a mask, except under the resist pattern Thinly leaving the metal layer in the region, and continuously etching the thin metal layer and the zinc oxide layer in the same apparatus using the alkaline developer with the resist pattern as a mask. A method for processing zinc oxide, comprising: Forming a zinc oxide layer on the substrate, forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer, and forming a resist layer on the metal layer; Etching the resist layer with an alkaline developer to form a resist pattern, and half-etching the metal layer with a metal etchant using the resist pattern as a mask, except under the resist pattern Thinly leaving the metal layer in the region, etching and removing the thin metal layer using the alkaline developer with the resist pattern as a mask, and dilute acetic acid using the resist pattern as a mask And a step of etching the zinc oxide layer. Forming a zinc oxide layer on the substrate, forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer, and forming a resist layer on the metal layer; Etching the resist layer with an alkaline developer to form a resist pattern, and half-etching the metal layer with a metal etchant using the resist pattern as a mask, except under the resist pattern A step of thinly leaving the metal layer in a region, a step of etching and removing a part of the thin metal layer and the zinc oxide layer using the alkaline developer with the resist pattern as a mask, Etching the remaining portion of the zinc oxide layer with dilute acetic acid using the resist pattern as a mask. Method for processing a zinc oxide having. The invention according to any one of claims 1 to 6 , wherein the metal layer is formed of an aluminum-based metal. The invention according to any one of claims 1 to 6 , wherein the step of forming another metal layer that is not etched with the alkaline developer on the upper surface of the metal layer, and the step of forming the metal layer on the upper surface of the another metal layer. And etching the other metal layer using another metal etching solution using the resist pattern as a mask. 9. The zinc oxide processing method according to claim 8 , wherein the another metal layer is formed of chromium. Forming a zinc oxide layer to be a semiconductor thin film on the first insulating layer;
Forming a protective film comprising a second insulating layer on the zinc oxide layer;
Forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer and the protective film, and that serves as a source electrode and a drain electrode;
Forming a resist layer on the metal layer;
Etching the resist layer with an alkaline developer to form a resist pattern;
The metal layer and the zinc oxide layer are continuously etched in the same apparatus using the alkaline developer with the resist pattern as a mask, and the source electrode and the drain electrode including the metal layer and the zinc oxide are etched. And a step of forming the semiconductor thin film including a physical layer. Forming a zinc oxide layer to be a semiconductor thin film on the first insulating layer;
Forming a protective film comprising a second insulating layer on the zinc oxide layer;
Forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer and the protective film, and that serves as a source electrode and a drain electrode;
Forming a resist layer on the metal layer;
Etching the resist layer with an alkaline developer to form a resist pattern;
The metal layer is half-etched using a metal etching solution with the resist pattern as a mask to leave the metal layer thinly in a region other than under the resist pattern, and the alkaline developer is used with the resist pattern as a mask. The thin metal layer and the zinc oxide layer are continuously etched in the same apparatus to form the source electrode and the drain electrode including the metal layer and the semiconductor thin film including the zinc oxide layer. And a process for manufacturing the thin film transistor. Forming a zinc oxide layer to be a semiconductor thin film on the first insulating layer;
Forming a protective film comprising a second insulating layer on the zinc oxide layer;
Forming a metal layer that can be etched with an alkaline developer on the zinc oxide layer and the protective film, and that serves as a source electrode and a drain electrode;
Forming a resist layer on the metal layer;
Etching the resist layer with an alkaline developer to form a resist pattern;
The metal layer is half-etched using a metal etching solution with the resist pattern as a mask to leave the metal layer thinly in a region other than under the resist pattern, and the alkaline developer is used with the resist pattern as a mask. Etching and removing a portion of the thin metal layer and the zinc oxide layer, and etching the remaining portion of the zinc oxide layer using dilute acetic acid using the resist pattern as a mask. Forming the source electrode, the drain electrode, and the semiconductor thin film including the zinc oxide layer. In the invention according to any one of claims 10 to 12,
After the step of forming the metal layer and before the step of forming the resist layer, including the step of forming another metal layer that is not etched with the alkaline developer on the upper surface of the metal layer,
After the step of forming the resist pattern and before the step of forming the source and drain electrodes and the semiconductor thin film, the another metal layer is formed using another metal etching solution using the resist pattern as a mask. A method for manufacturing a thin film transistor, comprising: a step of etching the substrate.

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