CN112928027A - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
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- CN112928027A CN112928027A CN202110181636.0A CN202110181636A CN112928027A CN 112928027 A CN112928027 A CN 112928027A CN 202110181636 A CN202110181636 A CN 202110181636A CN 112928027 A CN112928027 A CN 112928027A
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- 239000010409 thin film Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 113
- 238000005530 etching Methods 0.000 claims abstract description 93
- 239000004065 semiconductor Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 239000007788 liquid Substances 0.000 claims abstract description 23
- 238000001039 wet etching Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 34
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 30
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 13
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 13
- 229910052750 molybdenum Inorganic materials 0.000 claims description 13
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 11
- 239000011733 molybdenum Substances 0.000 claims description 11
- 239000008367 deionised water Substances 0.000 claims description 10
- 229910021641 deionized water Inorganic materials 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 2
- 239000000243 solution Substances 0.000 description 39
- 239000010408 film Substances 0.000 description 11
- 239000002585 base Substances 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 239000002253 acid Substances 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention provides a thin film transistor and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, and forming a gate electrode on the substrate; depositing a gate electrode insulating layer covering the gate electrode on the substrate; forming an oxide semiconductor layer on the gate electrode insulating layer; depositing a second metal layer and a first metal layer on the oxide semiconductor layer in succession; coating photoresist on the first metal layer; carrying out first wet etching on the exposed first metal layer by using first etching liquid; performing second wet etching on the exposed second metal layer by using second etching liquid; and removing the photoresist. The thin film transistor and the manufacturing method thereof can well protect the oxide semiconductor layer from being etched by the etching liquid, and solve the problem that the oxide semiconductor layer at the channel is cut off.
Description
Technical Field
The invention relates to the field of display, in particular to a thin film transistor and a manufacturing method thereof.
Background
With the continuous development of technology, display technology has been rapidly developed, thin Film transistor tft (thin Film transistor) technology is developed from the original a-Si (amorphous silicon) thin Film transistor to the present LTPS (low temperature polysilicon) thin Film transistor, Oxide thin Film transistor, etc., and the thin Film transistor of the compound semiconductor active layer material represented by metal Oxide has the advantages of high mobility, simple manufacturing process, good large area uniformity, low manufacturing cost, etc.
In the Oxide thin film transistor manufacturing technology, a Back Channel Etch (BCE) process and an Etch Stopper Type (ESL) process are generally adopted, wherein the ESL process is to manufacture an Etch Stopper layer on an Oxide semiconductor layer and Etch a via hole to connect a source drain electrode and an active layer, the process can better protect the Oxide semiconductor, but a composition process is added, so that the manufacturing process of the thin film transistor is complex, the cost is increased, and the Channel size of the thin film transistor is limited; although the BCE process omits a patterning process of the etching stopper layer, the oxide semiconductor cannot be well protected, that is, the BCE process may damage the compound semiconductor active layer while forming the source and the drain.
Because the metal aluminum has good conductivity and low cost, the metal aluminum is widely used as a source/drain (S/D) electrode in the production of a TFT (thin film transistor) with a bottom gate back channel etching structure, the corresponding wet etching liquid is generally an acid-base solution, such as a mixed acid solution consisting of phosphoric acid, nitric acid and other acids, and the like, in the mixed acid solution, the phosphoric acid plays a main etching role, and the nitric acid can oxidize the metal to accelerate the etching of the metal. Since the oxide semiconductor is very sensitive to acid and alkali, a general acid-alkali solution can rapidly etch the oxide active layer. Therefore, for an oxide TFT of a BCE structure, when an aluminum thin film is used for its source/drain electrode, the oxide semiconductor at the channel is very easily cut off because of the requirement of over-etching when wet etching the source/drain electrode and the active layer is generally thin. As shown in fig. 1, a gate electrode 12 is disposed on a substrate 11, a gate insulating layer 13 is disposed on the substrate 11 and the gate electrode 12, an oxide semiconductor layer 14 is covered on the gate insulating layer 13, and source/drain electrodes 15 are covered on the oxide semiconductor layer 14 and the gate insulating layer 13 and disposed on two sides of the oxide semiconductor layer 14, respectively, when the source/drain electrodes 15 are wet-etched, the source/drain electrodes 15 and the oxide semiconductor layer 14 form a channel, an etching solution directly contacts the oxide semiconductor layer 14, a portion of the oxide semiconductor layer 14 under the source/drain electrodes 15 will be etched away, but since the oxide semiconductor layer 14 is thin, a fracture is likely to occur, and an etching solution with a high Al/IGZO (indium gallium zinc oxide) selectivity ratio, that is, such an etching solution is not found at present, and can rapidly etch aluminum, while the etch rate to IGZO is very small or almost zero.
Disclosure of Invention
In order to solve the technical problems, the invention provides a thin film transistor and a manufacturing method thereof, which can well protect an oxide semiconductor from being etched by an etching solution and solve the problem that the oxide semiconductor at a channel is cut off.
The invention provides a manufacturing method of a thin film transistor, which comprises the following steps:
providing a substrate, and forming a gate electrode on the substrate;
depositing a gate electrode insulating layer covering the gate electrode on the substrate base plate;
forming an oxide semiconductor layer on the gate electrode insulating layer;
continuously depositing a second metal layer and a first metal layer on the oxide semiconductor layer, wherein the second metal layer covers the oxide semiconductor layer, and the first metal layer is positioned on the second metal layer;
coating photoresist on the first metal layer, and removing part of the photoresist including the channel region through exposure and development to form a photoresist pattern;
performing first wet etching on the exposed first metal layer by using first etching liquid to remove the first metal layer which is not covered by the photoresist;
performing second wet etching on the exposed second metal layer by using second etching liquid to remove the second metal layer which is not covered by the photoresist;
and removing the photoresist to obtain a source electrode and a drain electrode which are respectively contacted with two ends of the oxide semiconductor layer.
Further, the first metal layer is aluminum, and the second metal layer is molybdenum.
Further, the first etching solution is a phosphoric acid solution, and the second etching solution is a mixed solution of hydrogen peroxide and ammonia water.
Further, the first etching liquid is prepared from phosphoric acid and deionized water, wherein the phosphoric acid accounts for 30-100 wt% of the first etching liquid; the second etching solution is prepared from hydrogen peroxide, ammonia water and deionized water, wherein the hydrogen peroxide accounts for 1 wt% -60 wt% of the second etching solution, and the ammonia water accounts for 0 wt% -60 wt% of the second etching solution.
Furthermore, the etching temperature of the first wet etching is 20-60 ℃, and the etching temperature of the second wet etching is 15-30 ℃.
Further, the oxide semiconductor layer is IGZO or another metal oxide semiconductor.
The present invention also includes a thin film transistor comprising:
a substrate base plate;
a gate electrode formed on the substrate base plate;
a gate electrode insulating layer formed on the substrate base plate and covering the gate electrode;
a semiconductor layer formed on the gate electrode insulating layer;
a source electrode and a drain electrode formed on the semiconductor layer, the source electrode and the drain electrode being spaced apart from each other and contacting both ends of the semiconductor layer, respectively; the semiconductor layer is an oxide semiconductor layer, and either one of the source electrode and the drain electrode includes a first metal layer and a second metal layer, wherein the second metal layer covers the oxide semiconductor layer, and the first metal layer is located on the second metal layer.
Further, the first metal layer is aluminum, and the second metal layer is molybdenum.
Further, the oxide semiconductor layer is IGZO or another metal oxide semiconductor.
Further, the thickness of the oxide semiconductor layer is 30-80 nm, the thickness of the second metal layer is 20-60 nm, and the thickness of the first metal layer is 200-400 nm.
According to the thin film transistor and the manufacturing method thereof, provided by the invention, the condition that the oxide semiconductor layer is etched and broken in the wet etching process is avoided by a method of etching the source electrode and the drain electrode in two steps, when the first metal layer of the source electrode and the first metal layer of the drain electrode are etched by the first etching liquid, the first etching liquid cannot etch the second metal layer of the source electrode and the second metal layer of the drain electrode, and when the second etching liquid etches the second metal layer of the source electrode and the second metal layer of the drain electrode, the second etching liquid cannot etch the oxide semiconductor layer, so that the problem that the oxide semiconductor layer at the channel is etched and broken is solved, and the production yield of the thin film transistor is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of an oxide thin film transistor in the prior art.
Fig. 2 is a schematic cross-sectional view of a thin film transistor in an embodiment of the invention.
Fig. 3a to 3h are schematic views illustrating a manufacturing process of a thin film transistor according to an embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Thin Film transistor (tft) is widely used in display devices, and the technology of thin Film transistor is also developed from the original a-Si thin Film transistor to the present LTPS (low temperature polysilicon) thin Film transistor, Oxide thin Film transistor, and the like, among which, the thin Film transistor of compound semiconductor active layer material represented by metal Oxide is more popular because of its advantages of high mobility, simple manufacturing process, good uniformity of large area, low manufacturing cost, and the like.
The invention provides a manufacturing method of a thin film transistor, as shown in fig. 3a to 3h, the manufacturing method comprises the following steps:
providing a substrate 21, and forming a gate electrode 22 on the substrate 21, as shown in fig. 3 a; specifically, the base substrate 21 may be a glass substrate or a plastic substrate, and the gate electrode 22 may be a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, or Cu, or may be a composite film composed of a plurality of metal films.
Depositing a gate electrode insulating layer 23 on the substrate 21 covering the gate electrode 22, see fig. 3 b; specifically, the gate electrode insulating layer 23 is, for example, silicon oxide (SiO)x) Silicon nitride (SiN)x) Or silicon oxynitride (SiON)x)。
Forming an oxide semiconductor layer 24 on the gate insulating layer 23, see fig. 3 c; further, the oxide semiconductor layer 24 is IGZO or other metal oxide semiconductor.
Depositing a second metal layer 252 and a first metal layer 251 on the oxide semiconductor layer 24, wherein the second metal layer 252 covers the oxide semiconductor layer 24, and the first metal layer 251 is located on the second metal layer 252, please refer to fig. 3 d; further, the first metal layer 251 is aluminum, and the second metal layer 252 is molybdenum.
Coating the photoresist 26 on the first metal layer 251, and removing a portion of the photoresist 26 including the channel region by exposure and development to form a photoresist pattern, as shown in fig. 3e and 3 f; specifically, as shown in fig. 3f, after exposing and developing the photoresist 26, the photoresist 26 directly above the gate electrode 22 is removed to form a groove 261, and portions of the photoresist 26 at two ends of the photoresist 26 are also removed, so as to finally obtain a photoresist pattern.
Performing a first wet etching on the exposed first metal layer 251 by using a first etching solution to remove the first metal layer 251 not covered by the photoresist 26, please refer to fig. 3 g; specifically, the first etching solution etches the first metal layer 251 along the groove 261 to form an inclination angle 253 of 50 ° to 70 °, for example, the angle of the inclination angle 253 is 60 °, which facilitates the deposition of subsequent films.
Performing a second wet etching on the exposed second metal layer 252 by using a second etching solution to remove the second metal layer 252 not covered by the photoresist 26, please refer to fig. 3 h; specifically, the second etching liquid etches the second metal layer 252 along the groove 261 and the inclination angle 253, and finally the channel 241 is formed.
The photoresist 26 is removed to obtain a source electrode 25a and a drain electrode 25b which are in contact with both ends of the oxide semiconductor layer 24, respectively, see fig. 2.
Further, the first etching solution is a phosphoric acid solution, and the second etching solution is a mixed solution of hydrogen peroxide and ammonia water.
Specifically, the first etching liquid is prepared from phosphoric acid and deionized water, wherein the phosphoric acid accounts for 30-100 wt% of the first etching liquid; the second etching solution is prepared from hydrogen peroxide, ammonia water and deionized water, wherein the hydrogen peroxide accounts for 1-60 wt% of the second etching solution, and the ammonia water accounts for 0-60 wt% of the second etching solution.
Furthermore, the etching temperature of the first wet etching is 20-60 ℃, and the etching temperature of the second wet etching is 15-30 ℃. For example, the etching temperature of the first wet etching is 40 ℃, and at this temperature, the etching rate of the first metal layer 251 is higher, and the etching rate of the second metal layer 252 is slower, or no etching occurs; the etching temperature of the second wet etching is 25 ℃, and at this temperature, the etching rate of the second metal layer 252 is high, and the etching rate of the oxide semiconductor layer 24 is low, or no etching occurs.
The reason why the oxide semiconductor layer 24 is not etched in the process of wet etching the source electrode 25a and the drain electrode 25b is: when the first metal layer 251 is etched by the first etching solution, the etching rate of the first etching solution to the metal aluminum is high, the etching rate of the second metal layer 252 to the metal molybdenum is low or no etching occurs, when the second metal layer 252 is etched by the second etching solution, the etching rate of the second etching solution to the metal molybdenum is high, the etching rate to the IGZO of the oxide semiconductor layer 24 is low or no etching occurs, and the IGZO film at the channel 241 is protected by the second metal layer 252, so that the IGZO film at the channel 241 is completely retained. Meanwhile, when the second metal layer 252 is etched, the second etching liquid has a slower etching rate or does not etch the metal aluminum, so that the first metal layer 251 is not over-etched, which is not beneficial to the deposition of subsequent films.
For example, the first etching solution is prepared from 80ml of phosphoric acid solution and 20ml of deionized water, wherein phosphoric acid in the phosphoric acid solution accounts for 85 wt%; the second etching solution is prepared from 10ml of hydrogen peroxide, 10ml of ammonia water and 50ml of deionized water, wherein the mass percent of hydrogen peroxide in the hydrogen peroxide is 30 wt%, and the mass percent of ammonia in the ammonia water is 25 wt%. The etching temperatures of the first etching solution and the second etching solution are respectively 40 ℃ and 25 ℃ (room temperature is also possible), in this case, the first metal layer 251 forms an inclination angle 253 of 60 ° at the channel 241, which is a better inclination angle, and facilitates the deposition of subsequent films. The following are etching rates of aluminum, molybdenum and amorphous indium gallium zinc oxide (a-IGZO) in the first etching liquid and the second etching liquid, respectively, in the case where the first metal layer 251 is aluminum (Al), the second metal layer 252 is molybdenum (Mo), and the oxide semiconductor layer 24 is amorphous indium gallium zinc oxide (a-IGZO):
in conclusion, the following results are obtained:
when the first metal layer 251 is aluminum (Al), the second metal layer 252 is molybdenum (Mo), and the oxide semiconductor layer 24 is amorphous indium gallium zinc oxide (a-IGZO), when the first etching solution is prepared from 80ml of phosphoric acid solution and 20ml of deionized water, wherein phosphoric acid in the phosphoric acid solution accounts for 85 wt%, and the etching temperature is 40 ℃, the etching rate of the first metal layer 251 is 89.145(nm/min ), and the second metal layer 252 is not etched; when the second etching solution is prepared from 10ml of hydrogen peroxide, 10ml of ammonia water and 50ml of deionized water, wherein the mass percent of hydrogen peroxide in the hydrogen peroxide is 30 wt%, the mass percent of ammonia in the ammonia water is 25 wt%, and the temperature of the etching solution is 25 ℃, the etching rate of the second metal layer 252 is 180(nm/min ), and the oxide semiconductor layer 24 is not etched.
The present invention also provides a thin film transistor, as shown in fig. 2, which includes a substrate base plate 21; a gate electrode 22 formed on the substrate base plate 21; a gate electrode insulating layer 23 formed on the base substrate 21 and covering the gate electrode 22; a semiconductor layer formed on the gate electrode insulating layer 23; a source electrode 25a and a drain electrode 25b formed on the semiconductor layer, the source electrode 25a and the drain electrode 25b being spaced apart from each other and contacting both ends of the semiconductor layer, respectively; specifically, the base substrate 21 may be a glass substrate or a plastic substrate, the gate electrode 22 may be a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, or Cu, or may be a composite film composed of a plurality of metal films, and the gate insulating layer 23 may be, for example, silicon oxide (SiO) or the likex) Silicon nitride (SiN)x) Or silicon oxynitride (SiON)x)。
Further, the semiconductor layer is the oxide semiconductor layer 24, and any one of the source electrode 25a and the drain electrode 25b includes a first metal layer 251 and a second metal layer 252, wherein the second metal layer 252 covers the oxide semiconductor layer 24, and the first metal layer 251 is located on the second metal layer 252.
Further, the first metal layer 251 is aluminum, and the second metal layer 252 is molybdenum.
Further, the oxide semiconductor layer 24 is IGZO or other metal oxide semiconductor.
Further, the thickness of the oxide semiconductor layer 24 is 30 to 80nm, the thickness of the second metal layer 252 is 20 to 60nm, and the thickness of the first metal layer 251 is 200 to 400 nm.
Further, the inclination angle 253 of the first metal layer 251 is 50-70 °, for example, the inclination angle 253 is 60 °, and the inclination angle 253 in the degree range facilitates the deposition of subsequent films, and does not cause the occurrence of cracking during the deposition of subsequent films.
Compared with the prior art, the thin film transistor and the manufacturing method thereof provided by the invention have the advantages that the metal layer is additionally arranged on the oxide semiconductor layer 24 to serve as the second metal layer 252 of the source electrode 25a and the drain electrode 25b, the source electrode 25a and the drain electrode 25b are etched in two steps in the manufacturing method, when the first metal layer 251 of the source electrode 25a and the first metal layer 251 of the drain electrode 25b are etched by the first etching liquid, the etching rate of the second metal layer 252 is slower or no etching occurs, when the second metal layer 252 of the source electrode 25a and the second metal layer 252 of the drain electrode 25b are etched by the second etching liquid, the etching rate of the oxide semiconductor layer 24 is slower or no etching occurs, so that the oxide semiconductor layer 24 is protected from being etched by the etching liquid, and the situation that the oxide semiconductor layer 24 is etched and broken in the wet etching process is avoided.
In this document, the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for the purpose of clarity and convenience of description of the technical solutions, and thus, should not be construed as limiting the present invention.
As used herein, the ordinal adjectives "first", "second", etc., used to describe an element are merely to distinguish between similar elements and do not imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, including not only those elements listed, but also other elements not expressly listed.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method for manufacturing a thin film transistor is characterized by comprising the following steps:
providing a substrate (21), and forming a gate electrode (22) on the substrate (21);
depositing a gate electrode insulating layer (23) covering the gate electrode (22) on the base substrate (21);
forming an oxide semiconductor layer (24) on the gate electrode insulating layer (23);
continuously depositing a second metal layer (252) and a first metal layer (251) on the oxide semiconductor layer (24), wherein the second metal layer (252) covers the oxide semiconductor layer (24), the first metal layer (251) being located on the second metal layer (252);
coating photoresist (26) on the first metal layer (251), and removing a part of the photoresist (26) including a channel region through exposure and development to form a photoresist pattern;
carrying out first wet etching on the exposed first metal layer (251) by using first etching liquid to remove the first metal layer (251) which is not covered by the photoresist (26);
performing second wet etching on the exposed second metal layer (252) by using second etching liquid to remove the second metal layer (252) which is not covered by the photoresist (26);
and removing the photoresist (26) to obtain a source electrode (25a) and a drain electrode (25b) which are respectively contacted with two ends of the oxide semiconductor layer (24).
2. The method of manufacturing a thin film transistor according to claim 1, wherein the first metal layer (251) is aluminum and the second metal layer (252) is molybdenum.
3. The method of manufacturing a thin film transistor according to claim 2, wherein the first etching solution is a phosphoric acid solution, and the second etching solution is a mixture of hydrogen peroxide and ammonia water.
4. The method for manufacturing the thin film transistor according to claim 3, wherein the first etching solution is prepared from phosphoric acid and deionized water, wherein the phosphoric acid accounts for 30 wt% -100 wt% of the first etching solution; the second etching solution is prepared from hydrogen peroxide, ammonia water and deionized water, wherein the hydrogen peroxide accounts for 1 wt% -60 wt% of the second etching solution, and the ammonia water accounts for 0 wt% -60 wt% of the second etching solution.
5. The method for manufacturing a thin film transistor according to claim 3, wherein the etching temperature of the first wet etching is 20 ℃ to 60 ℃, and the etching temperature of the second wet etching is 15 ℃ to 30 ℃.
6. The method for manufacturing a thin film transistor according to any one of claims 1 to 5, wherein the oxide semiconductor layer (24) is IGZO or another metal oxide semiconductor.
7. A thin film transistor, comprising:
a substrate base plate (21);
a gate electrode (22) formed on the base substrate (21);
a gate electrode insulating layer (23) formed on the base substrate (21) and covering the gate electrode (22);
a semiconductor layer formed on the gate electrode insulating layer (23);
a source electrode (25a) and a drain electrode (25b) formed on the semiconductor layer, the source electrode (25a) and the drain electrode (25b) being spaced apart from each other and contacting both ends of the semiconductor layer, respectively;
characterized in that the semiconductor layer is an oxide semiconductor layer (24), and either one of the source electrode (25a) and the drain electrode (25b) includes a first metal layer (251) and a second metal layer (252), wherein the second metal layer (252) covers the oxide semiconductor layer (24), and the first metal layer (251) is located on the second metal layer (252).
8. The thin film transistor of claim 7, wherein the first metal layer (251) is aluminum and the second metal layer (252) is molybdenum.
9. The thin film transistor according to claim 8, wherein the oxide semiconductor layer (24) is IGZO.
10. The thin film transistor according to claim 8, wherein the oxide semiconductor layer (24) has a thickness of 30 to 80nm, the second metal layer (252) has a thickness of 20 to 60nm, and the first metal layer (251) has a thickness of 200 to 400 nm.
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