WO2018205794A1

WO2018205794A1 - Thin film transistor and preparation method therefor, array substrate and display device

Info

Publication number: WO2018205794A1
Application number: PCT/CN2018/082848
Authority: WO
Inventors: 宋振; 王国英
Original assignee: 京东方科技集团股份有限公司
Priority date: 2017-05-11
Filing date: 2018-04-12
Publication date: 2018-11-15
Also published as: CN107170807A; CN107170807B

Abstract

A thin film transistor and a preparation method therefor, an array substrate and a display device. The thin film transistor comprises: an active layer (20) located on a substrate (10), the active layer (20) comprising a source region (21), a drain region (23) and a channel region (22); and a first source (31), a first drain (32) and a gate insulating layer (40) located on the upper surface of the active layer (20), the first source (31) being in contact with the source region (21), the first drain (32) being in contact with the drain region (23), and the gate insulating layer (40) being in contact with the channel region (22); the front projection of the gate insulating layer (40) on the substrate (10) coincides with that of the channel region (22) on the substrate (10); and the distances from the first source electrode (31) and the first drain electrode (32) to the gate insulating layer (40) are both less than or equal to 1 μm. The described thin film transistor may reduce parasitic resistance between the first source (31), the first drain (32) and the channel region (22).

Description

Thin film transistor and preparation method thereof, array substrate, display device

Cross-reference to related applications

The present application is based on and claims the priority of the Chinese Patent Application No. JP PCT No.

Technical field

Embodiments of the present disclosure relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.

Background technique

In the preparation of a coplanar top-gate self-aligned thin film transistor, a high-resistance active layer is generally formed first, and then a region in contact with the source and drain in the active layer is electrically connected. Generally, those skilled in the art can perform plasma processing on the active layer by using a gas such as Ar (argon) or He (helium) to plasma-treat the region in contact with the source and the drain on the active layer, which is not only costly. And the effect of conductorization is not ideal.

Summary of the invention

According to a first aspect of the present disclosure, a thin film transistor including an active layer on a substrate, including a source region, a drain region, and a channel region, and a first source located on an upper surface of the active layer is provided a first drain and a gate insulating layer, the first source is in contact with the source region, the first drain is in contact with the drain region, and the gate insulating layer is in contact with the channel region Wherein an orthographic projection of the gate insulating layer on the substrate coincides with an orthographic projection of the channel region on the substrate; the first source and the first drain to the The distance of the gate insulating layer is less than or equal to 1 μm.

According to a second aspect of the present disclosure, there is provided a method of fabricating a thin film transistor, comprising: forming an active layer on a substrate, the active layer including a source region, a drain region, and a channel region; Forming a gate insulating layer on a substrate of the active layer, an orthographic projection of the gate insulating layer on the substrate coincides with an orthographic projection of the channel region on the substrate; Forming a first source and a first drain on the substrate of the layer, the first source and the first drain being in contact with the source region and the drain region, respectively, the first source And a distance from the first drain to the gate insulating layer is less than or equal to 1 μm.

According to a third aspect of the present disclosure, an array substrate including the above-described thin film transistor is provided.

According to a fourth aspect of the present disclosure, there is provided a display device comprising the above array substrate.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present disclosure, and are not to limit the disclosure. .

1 is a schematic structural view of a thin film transistor;

2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;

3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure;

4 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;

FIG. 11 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure;

12(a) to 12(b) are schematic diagrams showing the structure of forming a gate insulating layer in a method of fabricating a thin film transistor according to an embodiment of the present disclosure;

FIG. 13 is a schematic structural diagram of forming a gate in a method for fabricating a thin film transistor according to an embodiment of the present disclosure;

14(a) to 14(d) are schematic structural views showing a formation of a protective layer in a method of fabricating a thin film transistor according to an embodiment of the present disclosure;

FIG. 15 is a flowchart of a method for fabricating another thin film transistor according to an embodiment of the present disclosure;

16 is a schematic diagram of a process for fabricating a thin film transistor according to an embodiment of the present disclosure;

FIG. 17 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure.

detailed description

The technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It is apparent that the described embodiments are part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present disclosure without departing from the scope of the invention are within the scope of the disclosure.

Unless otherwise defined, technical terms or scientific terms used herein shall be taken to mean the ordinary meaning of the ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components. The words "including" or "comprising" or "comprises" or "comprises" or "an" Component or object. The words "connected" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.

The embodiment of the present disclosure refers to "above" in terms of the order in which the thin film transistors are formed. For any two layers, the subsequently formed layer is located above the previously formed layer.

As shown in FIG. 1, after forming the source and the drain, the contact resistance R _C between the active layer and the source and the drain, and the resistance R _{LDD of the} active layer low current drain region (LDD region) are both Larger, that is, there is a large parasitic resistance R _P between the source and drain and the channel region, where R _P = 2R _C + 2R _LDD .

An embodiment of the present disclosure provides a thin film transistor, as shown in FIG. 2, comprising an active layer 20 on a substrate 10, the active layer 20 including a source region 21, a drain region 23, and a channel region 22; a first source 31, a first drain 32, and a gate insulating layer 40 on the upper surface of the active layer 20 and in contact with the source region 21, the drain region 23, and the channel region 22, respectively; the gate insulating layer 40 is The orthographic projection on the substrate 10 coincides with the orthographic projection of the channel region 22 on the substrate 10; the distance from the first source 31 to the gate insulating layer 40 is less than or equal to 1 μm, and the first drain 32 to the gate insulating layer The distance of 40 is less than or equal to 1 μm.

In at least some embodiments, the material of the active layer 20 can be reasonably selected depending on the type of thin film transistor. The thin film transistor may be, for example, an amorphous silicon thin film transistor, a polysilicon thin film transistor, a metal oxide thin film transistor, an organic thin film transistor, or the like. The source region 21 and the drain region 23 of the active layer 20 may be subjected to a conductor treatment, or may not be subjected to a conductor treatment. The present disclosure does not limit the thickness of the active layer 20.

In at least some embodiments, the material of the substrate 10 can be a flexible substrate or a rigid substrate such as a glass or quartz substrate. When it is a flexible substrate, the flexible substrate needs to be on the carrier substrate. The present disclosure does not define the materials of the first source 31 and the first drain 32, and may be, for example, a conductive material having a high carrier concentration.

In at least some embodiments, the first source 31, the first drain 32, and the gate insulating layer 40 are located on the upper surface of the active layer 20, as shown in FIG. 2, in direct contact with the upper surface of the active layer 20. The pattern of the gate insulating layer 40 is the same as the pattern of the channel region 22.

In at least some embodiments, the distance between the first source 31 and the first drain 32 to the gate insulating layer 40 is less than or equal to 1 μm, that is, as shown in FIG. 2, taking the first insulating layer 31 as an example, referring to the first source. The distance between the edge of the electrode 31 close to the gate insulating layer 40 and the edge of the gate insulating layer 40 close to the first source 31 is less than or equal to 1 μm. The closer the first insulating layer 31 is to the edge of the gate insulating layer 40, the better.

In the thin film transistor provided by the embodiment of the present disclosure, by directly providing the first source 31 and the first drain 32 on the upper surface of the active layer 20, the orthographic projection of the gate insulating layer 40 on the substrate 10 is in the channel region 22 The orthographic projections on the substrate 10 are coincident, and the distance between the first source 31 and/or the first drain 32 to the gate insulating layer 40 is less than or equal to 1 μm, so that the length of the active layer 20LDD region can be reduced, thus The performance of the thin film transistor can be ensured without conducting the conductor treatment of the source region 21 and the drain region 23 of the active layer 20.

In addition, by reducing the length of the LDD region, the resistance R _{LDD of the} LDD region can be reduced, thereby achieving the effect of reducing the parasitic resistance R _P between the first source 31 and the first drain 32 and the channel region 22. Because R _P = 2R _C + 2R _LDD .

In at least some embodiments, as shown in FIG. 3, the first source 31 and the first drain 32 are in contact with the gate insulating layer 40, respectively. An end surface of the first source 31 is in contact with a side surface (for example, a left side surface) of the gate insulating layer 40, and an end surface of the first drain electrode 32 and another opposite side surface of the gate insulating layer 40 (for example, a right side) Face) contact.

The closer the first source 31 and the first drain 32 are to the channel region 22, the smaller the length of the LDD region, and the smaller the resistance R _{LDD of the} LDD region, the present disclosure by making the first source 31 and the first drain 32 Contacting the gate insulating layer 40, respectively, such that the length of the LDD region is zero, that is, R _LDD is zero, further reducing the parasitic resistance R _P between the first source 31 and the first drain 32 and the channel region 22.

In order to reduce the difficulty of the process in the preparation process, in some embodiments, as shown in FIG. 4, the distance d1 of the first source 31 to the gate insulating layer 40 is equal to the thickness t of the first source 31, and the first drain 32 The distance d2 to the gate insulating layer 40 is equal to the thickness t of the first source 31.

In at least some embodiments, as shown in FIG. 5, the thin film transistor further includes a gate 50 on an upper surface of the gate insulating layer 40, and a protective layer 60 covering an upper surface of the gate 50, wherein the gate insulating layer 40 On the opposite sides, the protective layer 60 is not in contact with the end surface of the first source 31 adjacent to the gate insulating layer 40 and the end surface of the first drain 32 close to the gate insulating layer 40. The protective layer 60 covers the upper surface of the gate 50, and is not in contact with the active layer 40 and has no overlapping regions.

The material of the gate insulating layer 40 is, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The material of the gate electrode 50 may be a metal such as molybdenum (Mo), aluminum (Al), Ti, gold (Au), Cu, hafnium (Hf), or tantalum (Ta).

In at least some embodiments, as shown in FIG. 6, the gate 50 is composed of three layers of metal, the upper and lower layers are MoNb (molybdenum-niobium alloy), and the intermediate layer is Cu, that is, the structure of the gate 50 is MoNb/Cu/MoNb. Optionally, the structure of the gate 50 may also be Cu+Mo/MoNb/Al/AlNb/MoTi.

In the embodiment of the present disclosure, by providing the protective layer 60 on the upper surface of the gate electrode 50, the thickness of the film layer covering the upper surface of the gate electrode 50 is increased (MoNb+protective layer film/other metal, or only one protective layer film is added). When the via is etched, the Cu metal exposure caused by over-Etch can be prevented, and the surface of the gate 50 is etched and oxidized, resulting in poor contact of the oxidized region, which is beneficial to improve BP (Back Panel). ) Yield.

In at least some embodiments, as shown in FIG. 7, protective layer 60 covers the outer surface of gate 50. That is, the protective layer 60 covers all surfaces except the bottom surface of the gate 50 in contact with the active layer 40, including the top surface and all sides. That is, the upper surface and the side surface of the gate 50 are covered with the protective layer 60.

By covering the upper surface and the side surface of the gate electrode 50 with the protective layer 60, it is possible to prevent the side surface of the gate electrode 50 from being oxidized during the process of preparing other film layers, resulting in poor contact of the oxidized region.

In at least some embodiments, the materials of the first source 31, the first drain 32, and the protective layer 60 are the same. Further, the thicknesses of the first source 31, the first drain 32, and the protective layer 60 are also the same. For example, the first source 31, the first drain 32, and the protective layer 60 are made of the same film layer, and for example, the first source 31, the first drain 32, and the protective layer 60 are the same film layer. A patterning process is prepared to form.

In the embodiment of the present disclosure, by setting the materials and thicknesses of the first source 31, the first drain 32, and the protective layer 60 to be the same, it is only necessary to perform a patterning process on a certain film layer to prepare the first source. 31. The first drain 32 and the protective layer 60 can simplify the fabrication process.

Optionally, the materials of the first source 31, the first drain 32, and the protective layer 60 are all transparent conductive materials. The transparent conductive material may be, for example, IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), AZO (Al Zinc Oxide), and IFO (Indium Fluorine Oxide). Indium oxide, etc.

Optionally, the materials of the first source 31, the first drain 32, and the protective layer 60 are all metal, and the thickness is 20-100 nm. The material of the protective layer 60 may be, for example, a metal such as Mo, Al, Ti, Ta, Hf, or Zr (zirconium).

In at least some embodiments, as shown in FIG. 8, when the first source 31, the first drain 32, and the protective layer 60 are both made of a conductive material, the first source 31 and the protective layer 60 are disposed between the first source 31 and the protective layer 60. An insulating portion 70a, a second insulating portion 70b is disposed between the first drain 32 and the protective layer 60, the first source 31, the first drain 32, the protective layer 60, and the first insulating portion 70a and the second insulating layer The portion 70b is provided in the same layer; wherein the material of the first insulating portion 70a and the second insulating portion 70b is composed of the oxide of the metal. For example, the material of the protective layer 60 may be a metal such as Al, Ti, Ta, Hf, or Zr. The material of the insulating portion 70 (including the first insulating portion 70a and the second insulating portion 70b) may be a high-resistance metal oxide such as alumina, titania, nitrogen oxide, cerium oxide or zirconium oxide.

In at least some embodiments, as illustrated in FIGS. 9 and 10, the thin film transistor further includes a passivation layer 80 over the first source 31 and the first drain 32, and a second source 91 and a second drain. The pole 92, the passivation layer package 80 includes a first via and a second via (not shown), the second source 91 is in contact with the first source 31 through the first via, and the second drain 92 is passed The second via is in contact with the first drain 32. For example, the material of the passivation layer 80 may be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride or the like.

By increasing the second source 91 and the second drain 92, the conductive performance of the thin film transistor can be further improved, thereby ensuring the performance of the thin film transistor.

The embodiment of the present disclosure further provides a method for preparing a thin film transistor, as shown in FIG. 11, the method includes:

S10. As shown in FIG. 12(a), an active layer 20 is formed on a substrate 10, and the active layer 20 includes a source region 21, a drain region 23, and a channel region 22.

For example, the material of the thin film forming the active layer 20 is a semiconductor material. After the active layer 20 is formed, the source region 21 and the drain region 23 may be subjected to a conductor treatment or may not be formed. For example, the material of the active layer 20 may include various commonly used materials such as a-IGZO, ZnON, IZTO, a-Si, and p-Si.

S20, as shown in FIG. 12(b), a gate insulating layer 40 is formed on the substrate 10 on which the active layer 20 is formed, the orthographic projection of the gate insulating layer 40 on the substrate 10 and the channel region 22 on the substrate 10. The orthographic projections coincide.

For example, an insulating film can be formed by PECVD (Plasma Enhanced Chemical Vapor Deposition), CVD (Chemical Vapor Deposition), or the like, and the insulating film can be patterned to form a gate insulating layer. 40. The material may be at least one of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

S30, as shown in FIG. 2, a first source 31 and a first drain 32 are formed on the substrate 10 on which the active layer 20 is formed, and the first source 31 and the first drain 32 are respectively connected to the source region 21 and The drain regions 23 are in contact with each other, and the distance between the first source 31 and the first drain 32 to the gate insulating layer 40 is less than or equal to 1 μm.

For example, when the first source 31 and the first drain 32 are formed, a metal thin film may be formed by magnetron sputtering, vapor deposition, or the like, and the material thereof may be Mo, Al, Ti, Au (gold), Cu, or the like. Hf, Ta, etc., which are easily oxidized. The transparent conductive film may also be formed by a method such as magnetron sputtering, and the material thereof may be IZO, ITO, AZO, IFO, or the like.

The method for fabricating a thin film transistor provided by the embodiment of the present disclosure, by directly forming the first source 31 and the first drain 32 on the upper surface of the active layer 20, the orthographic projection and channel of the gate insulating layer 40 on the substrate 10. The orthographic projection of the region 22 on the substrate 10 coincides, and the distance between the first source 31 and the first drain 32 to the gate insulating layer 40 is less than or equal to 1 μm, and the active layer 20LDD region can be reduced compared to the prior art. The length is such that the switching performance of the thin film transistor can be ensured without conducting the conductor treatment of the source region 21 and the drain region 23 of the active layer 20. The first source 31 and the first drain 32 of the high carrier concentration deposited in the source region 21 and the drain region 23 can form good ohmic contact with the source region 21 and the drain region 23, and are reduced. The contact resistance of the first source 31 and the first drain 32 is in direct contact with the active layer 20, and the contact resistance is not increased by the subsequent process, which is advantageous for increasing the on-state current of the thin film transistor (Ion ) and reliability.

In addition, by reducing the length of the LDD region, the resistance R _{LDD of the} LDD region can be reduced, thereby achieving the effect of reducing the parasitic resistance R _P between the first source 31 and the first drain 32 and the channel region 22. Because, R _P = 2R _C + 2R _LDD . And the parasitic resistance R _P does not increase with the subsequent increase in PECVD or high temperature processes.

In at least some embodiments, the method further comprises:

S21, as shown in FIG. 13, while the gate insulating layer 40 is formed on the substrate 10 on which the active layer 20 is formed, the gate 50 having the same pattern as that of the gate insulating layer 40 is formed by the same patterning process.

For example, a photoresist layer exposing the channel region 22 may be formed on the active layer 20, an insulating film and a metal film may be sequentially formed on the surface of the exposed channel region 22, and the remaining photoresist layer may be peeled off to form The same gate insulating layer 40 and gate 50 are patterned.

For example, an insulating film, a metal thin film, and a photoresist layer may be sequentially formed on the active layer 20, and the gate insulating layer 40 and the gate electrode 50 having the same pattern may be formed by a patterning process. The patterning process includes exposure, development, and removal of photoresist and the like. In the process of patterning, the metal film is wet etched, and the insulating film is dry etched. After the etching is completed, the plasma in the dry etching environment is used to etch the insulating film to the active layer. The source region 21 and the drain region 23 of 20 are subjected to a conductor treatment to remove the remaining photoresist.

In order to simplify the process difficulty and avoid the occurrence of interface trap defects in other regions during the process of conducting the source region 21 and the drain region 23, the process of conductorization can be omitted. At this time, the dry etching process only focuses on the insulating film. Patterning improves the climbing condition of the subsequent etching process film layer.

S31, as shown in FIG. 5-7, while the first source 31 and the first drain 32 are formed on the substrate 10 on which the active layer 20 is formed, the protection on the upper surface of the gate 50 is formed by the same patterning process. Layer 60.

For example, the first source 31, the first drain 32, and the protective layer 60 are formed by the same patterning process. The pattern of the protective layer 60 may be as shown in FIG. 5 and FIG. 6, or may be as shown in FIG.

In addition, the protective layer 60 is formed by the same patterning process as the first source 31 and the first drain 32, and the protective layer 60 is located on the upper surface of the gate 50. That is, the first source 31, the first drain 32, and the protective layer 60 are formed on the substrate 10 on which the gate 50 is formed.

Here, the protective layer 60 covering the pattern of the gate 50 can effectively prevent the Cu metal of the gate 50 from being oxidized in the subsequent formation of the interlayer insulating layer and the high-temperature annealing process of oxygen, thereby solving the problem of disconnection or short-circuit caused by Cu oxidation. risk.

In at least some embodiments, the steps of forming the first source 31, the first drain 32, and the protective layer 60 include:

S311, as shown in FIG. 14(a), a conductive film 30 is formed on the substrate 10 on which the gate electrode 50 is formed, and a photoresist covering the conductive film 30 is formed.

S312, as shown in FIG. 14(b), the photoresist is processed to form a photoresist layer 100 exposing a portion of the conductive film 30 on the side surface of the gate insulating layer 40.

S313, as shown in Fig. 14 (c) and Fig. 14 (d), the exposed portion of the conductive film 30 is insulated.

For example, the exposed portion of the conductive film may be removed by etching; or the exposed portion of the conductive film may be oxidized and oxidized to an insulating material; of course, other processing methods may be used to make the conductive film into an insulator.

S314, as shown in FIG. 7 and FIG. 8, the photoresist layer 100 is removed by a lift-off process.

Here, the exposed portion of the conductive film is treated by using the photoresist layer 100 as a mask to insulate the first source 31 and the first drain 32 from the protective layer 60 to avoid affecting the characteristics of the thin film transistor. .

In at least some embodiments, as shown in FIG. 11, the method further includes:

S40. As shown in FIG. 9, a passivation layer 80 including a first via and a second via is formed on the substrate 10 on which the first source 31 and the first drain 32 are formed.

S50, as shown in FIG. 9, a second source 91 and a second drain 92 are formed on the substrate 10 on which the passivation layer 80 is formed, and the second source 91 is in contact with the first source 31 through the first via. The second drain 92 is in contact with the first drain 32 through the second via.

Here, by increasing the second source 91 and the second drain 92, the conductivity of the thin film transistor can be further improved, thereby ensuring the performance of the thin film transistor.

Hereinafter, a method of preparing the thin film transistor provided by the present disclosure will be described by way of specific examples.

In some embodiments, a method of fabricating a thin film transistor is provided, as shown in FIG. 15, the method comprising:

S100. As shown in FIG. 12(a), an active layer 20 is formed on a substrate 10. The active layer 20 includes a source region 21, a drain region 23, and a channel region 22.

S110, as shown in FIG. 13, a gate insulating layer 40 and a gate electrode 50 having the same pattern are formed on the substrate 10 on which the active layer 20 is formed by one patterning process.

For example, the structure of the gate 50 may be composed of three layers of MoNb/Cu/MoNb.

S120, as shown in FIG. 14(a), a transparent conductive film is formed on the substrate 10 on which the gate electrode 50 is formed, and a photoresist PR covering the transparent conductive film is formed.

For example, the transparent conductive film may be formed by magnetron sputtering, deposition, or the like, and the material thereof may be IZO, ITO, AZO, IFO, or the like.

S130, as shown in FIG. 16, the photoresist is exposed by using a mask, and after the development, a completely retained portion of the photoresist and a completely removed portion of the photoresist are formed; the completely remaining portion of the photoresist corresponds at least to the first source to be formed. 31. A region where the first drain 32 is to be formed, and a region where the protective layer 60 is to be formed, the photoresist completely removed portion corresponds to exposing a portion of the conductive film 30 on the side of the gate insulating layer 40.

S140, as shown in FIG. 14(b), post-baking the completely remaining portion of the photoresist to make the photoresist completely remain partially softened and then flow to form a photoresist exposing a portion of the transparent conductive film on the side of the gate insulating layer 40. Layer 100. The post-baked photoresist becomes flowable and flows down to a portion of the side of the gate insulating layer 40.

For example, in order to increase the flow of the photoresist, the post-baking temperature in the step S130 can be appropriately increased.

For example, when the present disclosure performs post-baking of the fully retained portion of the photoresist in the step S140, the post-baking temperature can be controlled, for example, at 150 ° C to 200 ° C. The post-baking time can be, for example, 1-2 minutes.

S150, as shown in FIG. 14(d), the exposed partially transparent conductive film on the side of the gate insulating layer 40 is removed by etching.

For example, the exposed partial transparent conductive film may be etched by wet etching to form the first source 31, the first drain 32, and the protective layer 60, so that the first source 31 and the first drain 32 respectively Disconnected from the protective layer 60.

S160, as shown in FIG. 7, the photoresist layer 100 is removed by a lift-off process.

In some embodiments, a method of fabricating a thin film transistor is provided, as shown in FIG. 17, the method comprising:

S200, as shown in FIG. 12(a), an active layer 20 is formed on a substrate 10, and the active layer 20 includes a source region 21, a drain region 23, and a channel region 22.

S210, as shown in FIG. 13, a gate insulating layer 40 and a gate electrode 50 having the same pattern are formed on the substrate 10 on which the active layer 20 is formed by one patterning process.

S220, as shown in FIG. 14(a), a metal conductive film is formed on the substrate 10 on which the gate electrode 50 is formed, and a photoresist PR covering the metal conductive film is formed.

For example, the metal conductive film may be formed by magnetron sputtering, vapor deposition, or the like, and the material thereof may be a metal which is easily oxidized such as Mo, Al, Ti, Au, Cu, Hf, or Ta. The metal conductive film has a thickness of 20 to 100 nm.

S230, as shown in FIG. 16, the photoresist is exposed by a mask, and after development, a photoresist completely remaining portion and a photoresist completely removed portion are formed. The photoresist completely remaining portion corresponds at least to a region where the first source 31, the first drain 32 to be formed, and the protective layer 60 to be formed are to be formed.

S250, as shown in FIG. 14(c), the exposed portion of the metal conductive film is oxidized to oxidize it into a metal insulating film.

For example, the metal conductive film not covered by the photoresist is treated by high temperature oxygen annealing, anodization or O ₂ or N ₂ O plasma treatment to become an insulator. The first source 31, the first drain 32, and the protective layer 60 are formed such that the first source 31 and the first drain 32 are disconnected from the protective layer 60, respectively.

S260, as shown in FIG. 8, the photoresist layer 100 is removed by a lift-off process.

Embodiments of the present disclosure also provide an array substrate including the above thin film transistor. The beneficial effects of the array substrate provided by the embodiments of the present disclosure are the same as those of the thin film transistor described above, and are not described herein again.

In at least some embodiments, the array substrate further includes a gate line disposed in the same layer as the gate 50, and a conductive layer covering the surface of the gate line; the first source 31, the first drain 32, the protective layer 60, and The materials of the conductive layers are the same and are disposed in the same layer.

For example, the conductive layer covering the surface of the gate line is prepared by the same patterning process as the first source 31, the first drain 32, and the protective layer 60.

Here, by providing a conductive layer on the surface of the gate line, it is possible to prevent the gate line from being oxidized, thereby avoiding the occurrence of disconnection due to oxidation of the gate line, and improving the yield of the array substrate.

An embodiment of the present disclosure further provides a display device including the above array substrate. The display device can be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer. The beneficial effects of the display device provided by the embodiments of the present disclosure are the same as those of the above array substrate, and are not described herein again.

When the display device is a liquid crystal display (LCD), it includes an array substrate, a counter substrate, and a liquid crystal layer therebetween. The array substrate includes the above-mentioned thin film transistor, a pixel electrode electrically connected to the first drain 32 of the thin film transistor; further, a common electrode may be further included. The counter substrate may include a black matrix and a color film layer. Here, the color film layer may be located on the counter substrate or on the array substrate; the common electrode may be located on the array substrate or on the counter substrate.

When the display device is an Organic Light Emitting Diode (OLED) display, it includes an array substrate and a package substrate. Wherein, the array substrate comprises the above thin film transistor, an anode electrically connected to the first drain 32 of the thin film transistor, a cathode, and an organic material functional layer between the anode and the cathode.

Embodiments of the present disclosure provide a thin film transistor and a method for fabricating the same, an array substrate, and a display device. The anode and cathode of the gate insulating layer on the substrate are directly disposed on the upper surface of the active layer. The orthographic projection of the channel region on the substrate coincides and the distance between the first source and the first drain to the gate insulating layer is less than or equal to 1 μm. The above structure can reduce the length of the active layer LDD region, so that the performance of the thin film transistor can be ensured without conducting the conductor treatment of the source region and the drain region of the active layer.

In addition, by reducing the length of the LDD region, the resistance R _{LDD of the} LDD region can be reduced, thereby achieving the effect of reducing the parasitic resistance R _P between the first source and the first drain and the channel region, wherein R _P = 2R _C + 2R _LDD .

In this article, the following points need to be explained:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

(2) For the sake of clarity, in the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, the drawings are not drawn to actual scales.

(3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain a new embodiment.

The above description is only an exemplary embodiment of the present disclosure, and is not intended to limit the scope of the disclosure. The scope of the disclosure is determined by the appended claims.

Claims

A thin film transistor comprising:

An active layer on the substrate, including a source region, a drain region, and a channel region;

a first source, a first drain, and a gate insulating layer on an upper surface of the active layer, the first source is in contact with the source region, and the first drain is in contact with the drain region The gate insulating layer is in contact with the channel region;

Wherein an orthographic projection of the gate insulating layer on the substrate coincides with an orthographic projection of the channel region on the substrate; the first source and the first drain to the gate The distance of the insulating layer is less than or equal to 1 μm.
The thin film transistor according to claim 1, wherein an end surface of said first source is in contact with a side surface of said gate insulating layer, and an end surface of said first drain is in contact with another opposite side surface of said gate insulating layer.
The thin film transistor according to claim 1 or 2, further comprising a gate electrode on an upper surface of the gate insulating layer, and a protective layer covering an outer surface of the gate electrode, wherein two opposite sides of the gate insulating layer On the side surface, the protective layer is not in contact with an end surface of the first source adjacent to the gate insulating layer and an end surface of the first drain adjacent to the gate insulating layer.
The thin film transistor according to claim 3, wherein said protective layer covers an upper surface of said gate electrode, and is in contact with said active layer without overlapping regions.
The thin film transistor according to claim 3, wherein materials of said first source, said first drain, and said protective layer are the same.
The thin film transistor according to claim 5, wherein the materials of the first source, the first drain, and the protective layer are all transparent conductive materials; or

The materials of the first source, the first drain, and the protective layer are all metal and have a thickness of 20 nm to 100 nm.
The thin film transistor according to claim 6, wherein materials of said first source, said first drain, and said protective layer are both metal, and said first source and said protective layer are disposed a first insulating portion, a second insulating portion disposed between the first drain and the protective layer, the first source, the first drain, the protective layer, and the first insulation The portion and the second insulating portion are disposed in the same layer.
The thin film transistor according to claim 7, wherein the insulating portion is made of an oxide of the metal.
The thin film transistor according to any one of claims 1 to 8, further comprising a passivation layer over the first source and the first drain, and a second source and a second drain, The passivation layer includes a first via and a second via, the second source is in contact with the first source through the first via, and the second drain is through the second via The first drain contacts.
The thin film transistor of claim 1, wherein a distance between the first source and the first drain to the gate insulating layer is equal to a thickness of the first source.
A method of preparing a thin film transistor, comprising:

Forming an active layer on the substrate, the active layer including a source region, a drain region, and a channel region;

Forming a gate insulating layer on a substrate on which the active layer is formed, an orthographic projection of the gate insulating layer on the substrate coincides with an orthographic projection of the channel region on the substrate;

Forming a first source and a first drain on a substrate on which the active layer is formed, the first source and the first drain being in contact with the source region and the drain region, respectively The distance between the first source and the first drain to the gate insulating layer is less than or equal to 1 μm.
The preparation method according to claim 11, further comprising:

Forming a gate insulating layer on the substrate on which the active layer is formed, forming a gate electrode identical to the gate insulating layer pattern by the same patterning process;

A protective layer on the upper surface of the gate is formed by the same patterning process while the first source and the first drain are formed on the substrate on which the active layer is formed.
The preparation method according to claim 11, wherein the first source and the first drain are formed on the substrate on which the active layer is formed, and are formed on the gate by the same patterning process The protective layer of the surface includes:

Forming a conductive film on the substrate on which the gate electrode is formed, and forming a photoresist covering the conductive film;

Treating the photoresist to form a photoresist layer exposing a portion of the conductive film on the side of the gate insulating layer;

Insulating the exposed portion of the conductive film;

The photoresist layer is removed using a lift-off process.
The preparation method according to claim 13, wherein said processing said photoresist comprises:

Exposing the photoresist with a mask to form a fully-retained portion of the photoresist and a completely removed portion of the photoresist; the fully-retained portion of the photoresist at least corresponds to a first source to be formed, a first drain to be formed, And an area where a protective layer is to be formed;

The fully retained portion of the photoresist is post-baked to cause the photoresist to remain partially softened and then flow to form a photoresist layer exposing a portion of the conductive film on the side of the gate insulating layer.
The preparation method according to claim 13, wherein the conductive film is a transparent conductive film; and the insulating treatment of the exposed partial conductive film comprises: removing the exposed partial transparent conductive film by an etching process.
The preparation method according to claim 13, wherein the conductive film is a metal conductive film, the metal conductive film has a thickness of 20-100 nm;

Insulating the exposed portion of the conductive film includes:

A portion of the exposed metal conductive film is oxidized to form a metal insulating film.
The preparation method according to any one of claims 11 to 16, further comprising:

Forming a passivation layer including a first via and a second via on the substrate on which the first source and the first drain are formed;

Forming a second source and a second drain on the substrate on which the passivation layer is formed, the second source being in contact with the first source through the first via, the second drain The pole is in contact with the first drain through the second via.
An array substrate comprising the thin film transistor according to any one of claims 1 to 10.
The array substrate according to claim 18, further comprising a gate line disposed in the same layer as the gate, and a conductive layer covering the surface of the gate line;

The first source, the first drain, the protective layer, and the conductive layer are made of the same material and disposed in the same layer.
A display device comprising the array substrate of claim 18 or 19.