JP4447583B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4447583B2 JP4447583B2 JP2006200935A JP2006200935A JP4447583B2 JP 4447583 B2 JP4447583 B2 JP 4447583B2 JP 2006200935 A JP2006200935 A JP 2006200935A JP 2006200935 A JP2006200935 A JP 2006200935A JP 4447583 B2 JP4447583 B2 JP 4447583B2
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- JP
- Japan
- Prior art keywords
- signal
- delay
- circuit
- clock
- phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Memory System (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Dram (AREA)
Description
10 パッケージ
11 ロジックチップ
12 メモリチップ
13 外部端子
14 接続端子
15 I/O回路電源用端子
16 I/O回路電源線
17 端子
20 メモリ・ロジック間I/O部
21 高速I/O回路
22 I/O端子
23 I/O電源端子
24 接続端子
25 ワイヤボンディング
30 外部記憶装置用I/O部
31 外部記憶装置用I/O回路
32 外部記憶装置用端子
33 降圧回路
41 クロックバッファ
42 コマンドデコーダ
43 バンク選択バッファ
44 アドレスバッファ
45 データバッファ
46 メモリセルアレイ
47 ローデコーダ
48 センスアンプ・ライトアンプ
49 コラムデコーダ
50、50A バンク
51 シリアルアドレスカウンタ
52 シリアルデコーダ
53 シリアルアクセスメモリ
54 転送ゲート
55 転送制御回路
56 外部記憶装置用データバッファ
100 T−CLK発生回路
101 R−CLK発生回路
102 等長配線
103 データバッファ
111 DLL回路
112 位相シフト回路
113 ダミー等長配線
114 DLL回路
115 ダミー等長配線
116 ダミーデータバッファ
117 ダミーノード
128 データバッファ
120 クロックバッファ
121 DLL回路
122 位相シフト回路
123 ダミー等長配線
124 DLL回路
125 ダミー等長配線
126 ダミーデータバッファ
127 ダミーノード
128 データバッファ
401 ESD保護回路
402 ESD保護回路
501 ロジックデバイス
502 メモリデバイス
503 バス
Claims (7)
- チップの一辺に配置されたクロック受信用端子と、
該一辺に配置された複数の入出力端子と、
該クロック受信用端子で受信された受信クロック信号に基づいて入出力制御用クロック信号を生成する制御用クロック発生回路と、
該入出力制御用クロック信号に同期して該入出力端子を介して外部へのデータ出力及び外部からのデータ取り込みを行う複数の入出力回路と、
該制御用クロック発生回路と該複数の入出力回路の各々とを接続する同一長の複数の接続配線を含み、
前記制御用クロック発生回路は、データ取り込み用クロック信号を前記入出力制御用クロック信号として生成する第1のクロック発生回路を含み、
前記第1のクロック発生回路は、前記複数の接続配線の第1の遅延分と第2の遅延分との合計遅延分だけ前記受信クロック信号から位相がずれた信号を前記データ取り込み用クロック信号として出力し、
前記第1のクロック発生回路は、前記受信クロック信号の位相を調整して遅延信号を出力する位相調整回路と、該遅延信号より前記第1の遅延分だけ位相の遅れた第1の信号を出力する第1の手段と、該遅延信号を前記第2の遅延分だけ遅延させる第2の手段を含み、該位相調整手段は該第1の信号と該受信クロック信号とが同位相となるように該遅延信号の位相を調整して、該第2の手段は該遅延信号を該第2の遅延分だけ遅延させて前記データ取り込み用クロック信号として出力し、
前記第1のクロック発生回路は、1/N分周器を更に含み、前記受信クロック信号の周波数の1/Nの周波数で互いに位相が360度/Nずれた複数の分周クロック信号を生成し、前記複数の入出力回路の各々は、N個の入力回路を含み、該N個の入力回路は対応する該分周クロック信号を同期信号として用いることを特徴とする半導体装置。 - 前記制御用クロック発生回路は、データ出力用クロック信号を前記入出力制御用クロック信号として生成する第2のクロック発生回路を含むことを特徴とする請求項1記載の半導体装置。
- 前記第2のクロック発生回路は、前記複数の接続配線の第1の遅延分と前記複数の入出力回路の第2の遅延分との合計遅延分だけ前記受信クロック信号から位相がずれた信号を前記データ出力用クロック信号として出力することを特徴とする請求項2記載の半導体装置。
- 前記第2のクロック発生回路は、前記受信クロック信号の位相を調整して遅延信号を出力する位相調整回路と、該遅延信号より前記第1の遅延分だけ位相の遅れた第1の信号を出力する第1の手段と、該第1の信号より前記第2の遅延分だけ位相の遅れた第2の信号を出力する第2の手段を含み、該位相調整手段は該第2の信号と該受信クロック信号とが同位相となるように該遅延信号の位相を調整して該遅延信号を前記データ出力用クロック信号として出力することを特徴とする請求項3記載の半導体装置。
- 前記第2の手段は、前記遅延信号を位相180度分遅延させる位相シフト回路であることを特徴とする請求項1記載の半導体装置。
- 前記第2の手段は、前記遅延信号を所定の固定遅延量だけ遅延させる固定遅延回路であることを特徴とする請求項1記載の半導体装置。
- 前記クロック受信用端子に受信された前記受信クロック信号をそのまま出力する前記一辺に配置されたクロックリターン端子を更に含むことを特徴とする請求項1記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006200935A JP4447583B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2006200935A JP4447583B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24428597A Division JP3938617B2 (ja) | 1997-09-09 | 1997-09-09 | 半導体装置及び半導体システム |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009291016A Division JP5263144B2 (ja) | 2009-12-22 | 2009-12-22 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007036245A JP2007036245A (ja) | 2007-02-08 |
JP4447583B2 true JP4447583B2 (ja) | 2010-04-07 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006200935A Expired - Fee Related JP4447583B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
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JP (1) | JP4447583B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010080172A1 (en) * | 2009-01-12 | 2010-07-15 | Rambus Inc. | Clock-forwarding low-power signaling system |
KR102219296B1 (ko) | 2014-08-14 | 2021-02-23 | 삼성전자 주식회사 | 반도체 패키지 |
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- 2006-07-24 JP JP2006200935A patent/JP4447583B2/ja not_active Expired - Fee Related
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JP2007036245A (ja) | 2007-02-08 |
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