JP4424698B2 - 電界効果トランジスタ・パッケージ - Google Patents

電界効果トランジスタ・パッケージ Download PDF

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Publication number
JP4424698B2
JP4424698B2 JP02679799A JP2679799A JP4424698B2 JP 4424698 B2 JP4424698 B2 JP 4424698B2 JP 02679799 A JP02679799 A JP 02679799A JP 2679799 A JP2679799 A JP 2679799A JP 4424698 B2 JP4424698 B2 JP 4424698B2
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JP
Japan
Prior art keywords
fet
gate
fets
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP02679799A
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English (en)
Japanese (ja)
Other versions
JPH11274370A5 (https=
JPH11274370A (ja
Inventor
チャールズ・スティーブン・コーマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JPH11274370A publication Critical patent/JPH11274370A/ja
Publication of JPH11274370A5 publication Critical patent/JPH11274370A5/ja
Application granted granted Critical
Publication of JP4424698B2 publication Critical patent/JP4424698B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
JP02679799A 1998-02-17 1999-02-04 電界効果トランジスタ・パッケージ Expired - Fee Related JP4424698B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/024,485 US5959357A (en) 1998-02-17 1998-02-17 Fet array for operation at different power levels
US09/024485 1998-02-17

Publications (3)

Publication Number Publication Date
JPH11274370A JPH11274370A (ja) 1999-10-08
JPH11274370A5 JPH11274370A5 (https=) 2008-07-17
JP4424698B2 true JP4424698B2 (ja) 2010-03-03

Family

ID=21820831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02679799A Expired - Fee Related JP4424698B2 (ja) 1998-02-17 1999-02-04 電界効果トランジスタ・パッケージ

Country Status (3)

Country Link
US (1) US5959357A (https=)
EP (1) EP0938138A3 (https=)
JP (1) JP4424698B2 (https=)

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KR100230428B1 (ko) * 1997-06-24 1999-11-15 윤종용 다층 도전성 패드를 구비하는 반도체장치 및 그 제조방법
US6057779A (en) 1997-08-14 2000-05-02 Micron Technology, Inc. Method of controlling access to a movable container and to a compartment of a vehicle, and a secure cargo transportation system
US6356535B1 (en) * 1998-02-04 2002-03-12 Micron Technology, Inc. Communication systems and methods of communicating
EP1129480A1 (en) * 1998-10-05 2001-09-05 Kulicke & Soffa Investments, Inc Semiconductor copper bond pad surface protection
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6936531B2 (en) * 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US8636648B2 (en) 1999-03-01 2014-01-28 West View Research, Llc Endoscopic smart probe
US10973397B2 (en) 1999-03-01 2021-04-13 West View Research, Llc Computerized information collection and processing apparatus
JP4094174B2 (ja) * 1999-06-04 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法
US8065155B1 (en) 1999-06-10 2011-11-22 Gazdzinski Robert F Adaptive advertising apparatus and methods
US7710273B2 (en) * 1999-09-02 2010-05-04 Round Rock Research, Llc Remote communication devices, radio frequency identification devices, wireless communication systems, wireless communication methods, radio frequency identification device communication methods, and methods of forming a remote communication device
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP3616605B2 (ja) * 2002-04-03 2005-02-02 沖電気工業株式会社 半導体装置
EP1513195A4 (en) * 2002-06-13 2009-06-24 Panasonic Corp SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US7119437B2 (en) * 2002-12-26 2006-10-10 Yamaha Hatsudoki Kabushiki Kaisha Electronic substrate, power module and motor driver
US7427024B1 (en) 2003-12-17 2008-09-23 Gazdzinski Mark J Chattel management apparatus and methods
DE102004019447A1 (de) * 2004-04-19 2005-11-10 Siemens Ag Vorrichtung, insbesondere intelligentes Leistungsmodul, mit planarer Verbindungstechnik
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US20090015407A1 (en) * 2007-07-13 2009-01-15 Micron Technology, Inc. Rifid tags and methods of designing rfid tags
US7777630B2 (en) * 2007-07-26 2010-08-17 Round Rock Research, Llc Methods and systems of RFID tags using RFID circuits and antennas having unmatched frequency ranges
US8179232B2 (en) * 2008-05-05 2012-05-15 Round Rock Research, Llc RFID interrogator with adjustable signal characteristics
US7852221B2 (en) * 2008-05-08 2010-12-14 Round Rock Research, Llc RFID devices using RFID circuits and antennas having unmatched frequency ranges
US8712334B2 (en) * 2008-05-20 2014-04-29 Micron Technology, Inc. RFID device using single antenna for multiple resonant frequency ranges
US8053898B2 (en) * 2009-10-05 2011-11-08 Samsung Electronics Co., Ltd. Connection for off-chip electrostatic discharge protection
US8847293B2 (en) * 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US9337163B2 (en) * 2012-11-13 2016-05-10 General Electric Company Low profile surface mount package with isolated tab
US9006584B2 (en) * 2013-08-06 2015-04-14 Texas Instruments Incorporated High voltage polymer dielectric capacitor isolation device
US9899484B1 (en) * 2016-12-30 2018-02-20 Texas Instruments Incorporated Transistor with source field plates under gate runner layers
JP2025030915A (ja) * 2023-08-24 2025-03-07 新光電気工業株式会社 半導体装置

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US4182023A (en) * 1977-10-21 1980-01-08 Ncr Corporation Process for minimum overlap silicon gate devices
US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4343078A (en) * 1979-03-05 1982-08-10 Nippon Electric Co., Ltd. IGFET Forming method
US4471524A (en) * 1982-06-01 1984-09-18 At&T Bell Laboratories Method for manufacturing an insulated gate field effect transistor device
CA1198226A (en) * 1982-06-01 1985-12-17 Eliezer Kinsbron Method for manufacturing a semiconductor device
JPH06101652B2 (ja) * 1987-02-12 1994-12-12 三菱電機株式会社 バイアス回路
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
US5696403A (en) * 1993-10-25 1997-12-09 Lsi Logic Corporation System having input-output drive reduction
US5455442A (en) * 1993-11-17 1995-10-03 Harris Corporation COMFET switch and method
US5498556A (en) * 1995-01-10 1996-03-12 United Microelectronics Corp. Metal-oxide-semiconductor field-effect transistor and its method of fabrication

Also Published As

Publication number Publication date
EP0938138A2 (en) 1999-08-25
EP0938138A3 (en) 2003-08-20
JPH11274370A (ja) 1999-10-08
US5959357A (en) 1999-09-28

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