JP4403009B2 - Microprocessor - Google Patents

Description

  The present invention relates to a microprocessor that performs predetermined arithmetic processing in parallel with a simple configuration without any problem even if any of a plurality of processor elements constituting a SIMD type processor is defective, and is also suitable for scaling processing. .

In recent years, the degree of integration of LSIs has been increasing due to miniaturization of manufacturing processes, and it has become possible to increase the number of arithmetic units (processor elements) even in SIMD (Single Instruction Stream, Multiple Data Stream) type processors.
In the SIMD type processor, a plurality of processor elements (hereinafter referred to as PE) can simultaneously execute the same arithmetic processing on a plurality of data with one instruction. The plurality of PEs are frequently used in applications related to processing (for example, image processing in a digital copier, etc.) that has the same calculation but a very large amount of data.
In normal image processing in a SIMD type processor, a plurality of PEs are arranged in the main scanning direction, and high-speed arithmetic processing is possible by executing the same operation on a plurality of data simultaneously.
Even in a SIMD type processor configured to perform parallel processing with a plurality of PEs, if one of the plurality of PEs fails, the whole processor will fail. The technique of relieving the whole processor by replacing with PE has been taken.

  That is, as a technique for relieving the entire processor, for example, first, when there is a failed basic element processor, a failure occurs when reconfiguring the basic array coupling structure instead of the spare element processor. There is known a redundant configuration method for a highly parallel processor in which a spare processor is connected to a basic element processor adjacent to the basic element processor (see, for example, Patent Document 1).

  Second, there is provided a redundant switching device that allocates a replacement PE without allocating a signal line for controlling movement / stop provided for each of the plurality of PEs to the defective PE, thereby including the defective PE. 2. Description of the Related Art A redundancy switching device for a parallel processor that operates the parallel processor normally is known (see, for example, Patent Document 2).

  Thirdly, when a large number of PEs are coupled to each other for parallel processing, a combination of one PE and a plurality of connection switching means having a function of allowing the PE to connect or disconnect to a circuit and pass a signal. It consists of these processing modules that have the same structure and one or more wires that connect adjacent processing modules, and performs failure PE avoidance processing in units of PM. A parallel machine that reproduces the previous topology is known (for example, see Patent Document 3).

  Fourth, n + 1 storage devices, n arithmetic devices, n registers that hold information indicating whether or not the storage device is defective, and when the register information indicates a storage device failure or When a switching signal from the previous stage is received at a high level, a switching signal generation circuit that outputs the switching signal of the high level to the next stage circuit and the switching circuit of the same stage, and data of the arithmetic unit when the switching signal is at a low level Connect the input / output line and the input / output terminal of the storage device, and switch the data input / output line of the computing device from the input / output terminal of the storage device to the input / output terminal of the next storage device when the switching signal switches to high level. There has been known a data processing device provided with a switching circuit (see, for example, Patent Document 4).

  Fifth, a first communication path connecting one processor unit and another processor unit adjacent to the first side of the processor unit, and another adjacent to the processor unit and the second side of the processor unit A second data communication path for connecting the processor, and the processor unit performs the first data communication at the time of invalidation of the processor unit invalidation control circuit and a faulty processor unit due to the operation of the invalidation control circuit. A semiconductor device having a bypass circuit that outputs data input from a path to a second data communication path is known (see, for example, Patent Document 5).

  Sixth, another same additional configuration group is assigned to one or more configuration groups, and a multiplexer is pre-connected to the input side of the configuration group, and the multiplexer connects the input bus of one configuration group to the subsequent configuration Can be connected to a group, and a multiplexer is post-connected to the output side of the configuration group, the multiplexer can receive the output bus of one of the subsequent configuration groups, and one of the configuration groups fails In such a case, a method of repairing an integrated circuit is known in which a failed configuration group is replaced by a subsequent configuration group and a last configuration group is replaced by an additional configuration group (see, for example, Patent Document 6).

Japanese Patent Laid-Open No. 9-22400 Japanese Patent Application Laid-Open No. 9-288652 Japanese Patent No. 3005243 JP 2000-148998 A JP 2002-169787 A JP-T-2001-527218

As described above, in the conventional examples described in JP-A-9-22400, JP-A-9-288852, and Japanese Patent No. 3005243, a redundant PE for replacing a defective processor is provided and a failure occurs. When there is a PE, the parallel processor is relieved by assigning a signal for specifying the PE to the redundant PE. In particular, in the conventional example described in Japanese Patent Laid-Open No. 9-288652, data from outside the processor is saved. Is transferred to the external output bus by a three-state buffer, and the buffer output enable signal itself is configured to be switched between a faulty PE and a redundant PE.
These are effective methods when the number of PEs is small, but redundant PEs are required in advance, so when the number of PEs is large, the number of control lines that need to be switched becomes very large and the configuration area is increased. However, there is a drawback that the manufacturing cost, the manufacturing complexity, and the manufacturing cost are inevitably increased.

Further, in the conventional examples described in the respective publications such as JP 2000-148998, JP 2002-169787, and JP 2001-527218, an output signal from an adjacent PE and a signal output by itself are used. Each PE has a shared multiplexer, and the faulty PE rescues the parallel processor by bypassing and outputting the output signal from the adjacent PE. In particular, Japanese Patent Laid-Open No. 2002-169787 does not Although not described, in the conventional example described in Japanese Patent Laid-Open No. 2000-148998, data transfer with the outside of the processor is handled by adopting a shift register configuration.
These are simple in structure, but use a shift register. Therefore, even when data transfer is performed only for a PE larger than a specific PE, data must be shifted even for a PE smaller than the specific PE. As a result, there is a drawback in that the time required for transfer increases.

  SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a microprocessor that can always perform rescue and normal and quick data transfer with a simple configuration even if there is a defective PE in a SIMD type processor. It is a second object of the present invention to provide a microprocessor that can simultaneously perform a scaling process as well as a repair of a processor in image processing.

In order to achieve the above object, the present invention provides a microprocessor including a SIMD type processor having a plurality of processor elements for processing a plurality of data, and a register different from general-purpose registers provided in advance for each processor element. As a failure flag indicating whether or not there is a defect in its own processor element, it is possible to set individual data for each processor element by an instruction instruction, and to indicate data indicating the number of its own processor element A data transfer port for storing and providing an ID register for storing the incremented number except for the processor element of the defective flag when the defective flag is found, and accessing the general purpose register and the defective flag from the outside Set up , Wherein the data transfer port is connected to the data transfer device for performing data transfer between the general-purpose register and an external memory of each processor element, the data transfer apparatus, the defective flag and the ID register value To suppress the data transfer.

  The individual data set for each processor element is a scaling control bit in image processing.

The value of the defect flag is set based on a result of a self test of each processor element in the SIMD type processor.

According to the present invention, even if any one of the processor elements is defective, the entire SIMD type processor can be relieved except for the adverse effect of the defective processor element. Even if there is, it is always possible to perform normal data processing (transmission or reception) by performing the same arithmetic processing.
Further, according to the present invention, even if any of the processor elements is defective, it is possible to rescue the SIMD type processor and perform the scaling process (or scaling process at an arbitrary scaling ratio) with certainty. There is also a functional improvement.

  First, with reference to FIG. 1 and FIG. 2, the technology which is the premise of the present invention will be described. FIG. 1 is a block diagram showing a schematic configuration of a technology as a premise of the present invention, and FIG. 2 is a block diagram showing a partial detailed configuration of the technology as a premise of the present invention.

  As shown in FIG. 1, the technology which is the premise of the present invention is a global processor (hereinafter referred to as GP) 13 which is a single instruction stream single data stream (SISD) type processor, and a single instruction stream multiple data SIMD. stream) type processor (see FIG. 2) 11 and a processor element group 15 and a microprocessor including an external interface 17 connected to a memory controller 21 as a data transfer device.

  The GP 13 controls the memory controller 21 and the processor element group 15. Specifically, the GP 13 activates the memory controller 21 to read image data and the like from the external memory 23, and at the same time, a predetermined general-purpose register (described later) in the register file 31 of the processor element group 15 via the external interface 17. And the arithmetic array 33 is controlled to perform the same arithmetic processing on the image data and the like and stored in another general-purpose register (R register) in the register file 31. Then, the GP 13 activates the memory controller 21, causes the image data after the arithmetic processing to be taken in via the external interface 17, and writes it into the external memory 23.

  Note that the GP 13 does not necessarily control the same memory controller 21 to read / write image data or the like with respect to the same external memory 23. In some cases, image data or the like is written to another external memory.

  In general, the memory controller 21 controls the external interface 17 based on a predetermined command from the GP 13 and also includes a memory (single-unit) provided in an image input system including a CCD sensor such as a digital copying machine or a facsimile. Image data and the like to be calculated are sequentially read out from the port memory (RAM) 23, and a register file (R register described later) 31 of each processor element (hereinafter referred to as PE) in the processor element group 15 via the external interface 17. And temporarily storing the result of the arithmetic processing (image data or the like) by the arithmetic array 33 such as image data after the temporary storage in the memory 23 via the external interface 17. The calculated image data and the like stored in the memory 23 are output to an image forming system or the like that performs electrostatic latent image formation, development, transfer to paper, etc., such as a digital copying machine or a facsimile.

  That is, the memory controller 21 is provided for each external interface 17 provided for each R register. Specifically, as shown in FIG. 4, when writing image data to the memory (RAM) 23. The write buffer 71 used for reading, the read buffer 73 used when reading image data from the memory 23, the external I / F control unit 75 for controlling the external interface 17 to access the register file 31 of the PE, and the memory 23 A RAM control unit 77 that controls recording, reading, and calculation of image data after image data is recorded, and a sequence unit (hereinafter referred to as SCU) 79 that controls the entire image data.

  The memory controller 21 is connected to the register file 31 of the processor element group 15 constituting the SIMD type processor via a data transfer port (not shown: provided with an output port and an input port) in the external interface 17. Data transfer from the file 31 to the memory 23 and data transfer from the memory 23 to the register file 31 are controlled. The registers controlled by the memory controller 21 are mapped in the I / O space, and read and write can be controlled according to a request from the GP 13.

  The output port of the external interface 17 of the SIMD processor 11 is connected to the write buffer 71, and the input port of the external interface 17 is connected to the read buffer 73. Each data transfer port has an input port and an output port for even and odd PEs independently, and can be configured to access data for one set of even and odd PEs at a time in one cycle. Has been.

  The data buses between the write buffer 71, the read buffer 73, and the memory 23 are each configured with a data width of 4 PEs, and data of 4 PEs can be accessed at a time in one cycle. The data for 1 PE is 8 bits, and the bit width of the data bus between the external interface 17 and the write buffer 71 and the read buffer 73 is 16 bits. Therefore, the bit width between the memory controller 21 and the memory 23 is 32 bits.

  As a result, the data transfer between the memory 23 and the memory controller 21 may be performed once while the data transfer between the data transfer port of the external interface 17 and the memory controller 21 is performed twice. The write buffer 71 of the memory controller 21 performs an operation of fetching data output from the external interface 17 of each PE twice and transferring the data to the memory 23 after the data for four PEs are stored. The read buffer 73 performs an operation of dividing the data for four PEs read from the memory 23 into two times and transferring the data to the external interface 17 of each PE.

  On the other hand, the control bit port (not shown) of the external interface 17 is connected to the SCU 79, and the transfer suppression data is read at the time of data transfer via the control bit port to control the data transfer. Do.

  Next, with reference to FIG. 2, the specific configuration of the GP 13 and the PEs constituting the SIMD type processor will be described. As shown in FIG. 2, the GP 13 specifically includes a program RAM 41 for storing a program for controlling each PE 40 and a data RAM 43 for storing operation data.

  Second, the GP 13 is a program counter PC that holds a program address, general-purpose registers G0, G1, G2, and G3 for storing data for arithmetic processing, and a stack pointer that holds a save destination address of the data RAM 43 at the time of register saving and restoration. SP, a link register LS that holds a call source address at the time of a subroutine call, registers LI and LN that hold branch source addresses at the time of IRQ (interrupt signal input) and NMI (high priority interrupt processing), and GP13 The processor status register P for holding the state is incorporated.

  Third, although not shown in detail, the GP 13 is an instruction decoder for executing a predetermined instruction, an ALU (arithmetic logic unit), a memory control circuit, an interrupt control circuit, an external I / O control circuit, and a GP calculation. A control circuit is built-in.

  Although not shown, the GP 13 controls the register file 31 of each PE 40 in the processor element group 15 and controls each PE 40 using an instruction decoder, a register file control circuit, and a PE operation control circuit, although not shown. Control of an arithmetic array (including an arithmetic logic unit described later) 33 and control of a 7to1 multiplexer (hereinafter referred to as 7to1MUX) 35 of each PE 40 are performed.

  On the other hand, each PE 40, as shown in FIG. 2, first, for example, 24 8-bit registers (hereinafter referred to as R) that selectively store, for example, one-pixel image data (Data) read from the memory 23. R0 to R23 (referred to as registers) and, for example, eight 8-bit registers (hereinafter referred to as R registers) R24 to R31 that selectively and temporarily store image data of one pixel after the calculation described later.

  Each of the R registers R0 to R31 has one read port and one write port for the arithmetic logic unit 47 described later, and is accessed from an arithmetic array described later via an 8-bit read / write bus B1. The Among the R registers R0 to R31, in particular, the R registers R0 to R23 have a data transfer port for external access, and an image is exchanged with the external memory controllers 21 to 23 via the external interface 17. Data transfer such as data can be performed.

  In particular, the memory controller 21 can read and write any R register R0 to R23 by outputting an address signal (Address), a clock signal (CLK), and a read / write control signal (RWB). Street.

  Each PE 40 includes the aforementioned R registers R0 to R31, and has an array configuration of, for example, 256 sets. In this case, the total number of R registers is 8192. However, PE40 has an aspect which employs an array configuration of 1024 sets, for example.

  Second, each PE 40 includes a 7 to 1 MUX 35, a shift and expansion circuit (ShiftExpand: hereinafter referred to as SE) 45, a 16-bit arithmetic logic unit (hereinafter referred to as ALU) 47, an A register 48, and an F register 49. . Further, although not shown in detail, each PE 40 includes an 8-bit condition register, and the execution / invalidation control of the operation execution can be performed for each PE 40. Thereby, specific PE40 can be selected as a calculation target.

  In this example, an accumulator method is used as the arithmetic array, but a general-purpose register method or the like may be used.

  The 7 to 1 MUX 35 is connected to the bus B1 connecting the R registers R0 to R31 and also connected to the bus B1 of each of the three PEs 40 adjacent to each other. Access to the register R0 or the like or access to the R register R24 or the like is selected. That is, the 7to1 MUX 35 outputs image data or the like temporarily stored in the R register R0 or the like selected based on the selection command from the GP 13 to the SE 45, and the calculated image data or the like to the R register R24 or the like. One of the processes for temporarily storing is performed. As a result, the 7to1 MUX 35 makes it possible to cause the ALU 47 to perform arithmetic processing using any of the image data held in the R registers R0 to R23 of the seven PEs 40 including the three PEs 40 adjacent to each other. Increase.

  The SE 45 performs either processing of shifting the image data from the 7to1 MUX 35 by a predetermined bit and outputting it to the ALU 47 or shifting the image data after the calculation from the ALU 47 by a predetermined bit and outputting it to the 7to1 MUX 35. It should be noted that the processing of SE45 includes a case where image data or the like is subjected to zero extension or a predetermined constant multiple.

  The ALU 47 performs a predetermined arithmetic logic operation based on the image data from the SE 45 and the data held in the A register 48. The ALU 47 can handle 16-bit image data and the like. The calculated data is stored in the A register 48 and the data is stored in the F register (temporary register) 49. These are controlled by GP13.

  Next, an outline of the operation of the memory controller 21 and each PE 40 will be described. Assume that the external memory 23 stores, for example, image data before image processing (arithmetic processing) for one line captured from a scanner or the like. Based on the request from the GP 13, the memory controller 21 reads the image data in the memory 23 and transfers it to, for example, the R register R 0 of each PE 40 and temporarily stores it.

  Subsequently, each PE 40 performs image processing (predetermined calculation processing) on, for example, image data of 256 pixels as a whole. In the calculation process, for example, an output image is formed through several hundred calculations. The calculated image data is temporarily stored in the R register R1 of each PE 40, for example, in response to a request from the GP 13. A predetermined memory controller (for example, another memory controller) is activated in response to a request from the GP 13, and the post-computation image data stored in each R register R1 is stored in an external memory (for example, another memory).

  If the horizontal width (the number of pixels in the main scanning direction) of the image data to be subjected to image processing is within 256, the processing for one line is completed by performing the above operation. If the horizontal width of the image data is 256 or more, the processing for one line is completed by performing the above processing in a plurality of times. After that, the image processing (arithmetic processing) is completed by repeating this for the number of pixels in the vertical direction (number of pixels in the sub-scanning direction) times.

  The microprocessor according to the first embodiment of the present invention will be described below with reference to FIGS. The microprocessor of this embodiment is also applied to the SIMD type processor. FIG. 3 is a block diagram showing a detailed configuration of the SIMD type processor and GP 13 of the present embodiment. In FIG. 3, the same parts as those shown in FIG.

  As shown in FIG. 3, the SIMD type processor 51 of this example newly includes a defect flag 53, an ID register 55, a T register 57, two MPXs 59 and 61, and a PE selection unit 63 for each PE 40. It is a thing.

  Each failure flag 53 is a 1-bit register, and as a result of self-testing whether or not the own PE 40 operates normally in accordance with the execution of the self-test program stored in the program RAM 41 of the GP 13, Information indicating whether or not it is defective is set. Each failure flag 53 is set to ‘0’, for example, when its own PE 40 is normal, and is set to ‘1’ when it is defective. Each defect flag 53 is configured by a shift register, and it is possible to set whether each value is “0” or “1” from the GP 13.

  The defect flag 53 is connected to a data transfer port (not shown) for connection to the external interface 17 that relays access from the outside (memory controller 21). It is possible to prevent data transfer for 23 and the like. Data transfer mainly includes data transfer such as image data before or after calculation.

  The value of the defect flag 53 can be output from the transfer port to the external memory controller 21 or the like via the external interface 17 so that the memory controller 21 can recognize the defective PE 40. As for the value of the defect flag 53, the access from the external memory controller 21 is performed as one data by one set of the even-numbered PE 40 and the odd-numbered PE 40. Therefore, 2 bits for the even-numbered PE 40 and the odd-numbered PE 40 are used once. The data is transmitted to the external memory controller 21 by access.

  The ID register 55 stores data indicating the number of PEs counted from, for example, the leftmost (first) PE 40 in the figure. That is, the number incremented in order from “0” is stored except for the defective PE 40 that was found in the self-test described later. The value in the ID register 55 is input to the ALU (16-bit ALU) 47 via the data bus, and the result of comparison with the immediate data from the GP 13 in the ALU 47 is reflected in the T register 57.

  In image processing, for example, processing such as loading the same value to every fourth PE 40 may be required, such as loading a dither table. Even if there is, it becomes possible to cope.

  More specifically, as shown in FIG. 5, the T register 57 performs an AND operation between the multiplexer 64, a plurality of 1-bit registers T7 to T0 as a flag, the multiplexer 65, and the inverted input of the defective flag 53 and the output of the multiplexer 65. An AND circuit 67 is provided. The multiplexer 64 inputs the value of an operation flag (not shown) output from the ALU 47 of each PE 40 and the data from the data bus in order to initialize the registers T7 to T0, and the register T7 according to the operation result. Any of ~ T0 can be set. The multiplexer 65 is provided for selecting one of the eight registers T7 to T0 as a condition for the operation type. In the AND circuit 67, the selected result is always negated (negative) in the defective PE 40, and the calculation is not performed in the defective PE. That is, the AND circuit 67 inputs the output of the multiplexer 65 and inverts the output of the failure flag 53, and when the operation execution selected by the multiplexer 65 is affirmed, the AND circuit 67 outputs an output indicating that to the A register 48, F It is reflected in the register 49 and the MPX 59, and the invalidation / validity of the 16-bit ALU 47 operation execution is always controlled.

  The MPX 59 inputs the immediate data from the immediate data 1 data bus in the GP 13, while inputting the image data from the shifter (that is, the same as SE shown in FIG. 2; hereinafter referred to as a shifter) 45, and converts the image data and the like into the ALU 47. Forward to. The immediate data is used when data is commonly set for all PEs 40, and is a value described in the command.

  The MPX 61 inputs the immediate data from the immediate 2 data bus in the GP 13 while inputting the data from the A register 48 and transfers the data from the A register 48 to the ALU 47. Note that the immediate data in this case is also used when data is commonly set in all the PEs 40, and is a value described in the instruction.

For example, when processing such as loading the same value into every fourth PE 40 is required, such as loading the dither table, the value of the ID register and the supply from the GP in the ALU of each PE 40 AND operation with the immediate data “3” to be performed is performed, and the operation result is stored in the A register (Step 1).
Next, the value of the A register is compared with the immediate data “0” supplied from the GP, and the operation flag value of the comparison result (Z flag (a flag that becomes “1” when the operation results are equal)) is stored in the T register. Is stored in the T1 flag (Step 2).
Similarly, the value of the Z flag as a comparison result between the value of the A register and the immediate data “1” supplied from the GP is stored in the T2 flag (Step 3).
Similarly, the value of the Z flag as a comparison result between the value of the A register and the immediate data “2” supplied from the GP is stored in the T3 flag (Step 4).
Similarly, the value of the Z flag as a comparison result between the value of the A register and the immediate data “3” supplied from the GP is stored in the T4 flag (Step 5).
In this way, the PE with the PE number (4n) is “1” at T1, the PE with the PE number (4n + 1) is “1” at T2, and the PE with the PE number (4n + 2) is “1” at T3. ", And PE with the PE number (4n + 3) stores" 1 "in T4. If these four flags (T1 to T4 flags) are used, the same value is loaded for every fourth PE. It turns out that it is possible to do.

  As described above, the ALU 47 performs a predetermined arithmetic logic operation based on the image data from the shifter 45 and the data from the A register 48. The ALU 47 can handle 16-bit image data and the like. In addition to being stored in the A register 48, the data after the calculation may be stored in the F register (temporary register) 49. These are controlled by GP13.

  The PE selection unit 63 is first connected to the bus B1 connected to the R registers R0 to R31 in its own PE40, and secondly, three adjacent points in front of the arrangement direction of the PEs 40 (left direction in the drawing). , And the fourth PE40 adjacent to each other, individually connected to each bus B1 connected to the R registers R0 to R31, and thirdly, three in the rear (right direction in the drawing) with respect to the arrangement direction of each PE40. A total of nine wiring paths 68 individually connected to each bus B1 connected to the R registers R0 to R31 in each of the PE40 of the adjacent and fourth adjacent portions are provided, and the R register of any one of the PE40 A configuration as a so-called 9to1 multiplexer that enables selective access to R0 to R31 is included.

  That is, the PE selection unit 63 selects access to the R registers R0 to R31 of one PE45 among all nine PEs 40 related to itself by a selection command from the GP 13, for example. It should be noted that the PE 40 that is adjacent to each of the fourth front and rear PEs is handled as a relief or a spare for a case where any of the three adjacent PEs 40 is defective.

  Each PE selection unit 63 is input with the value of the failure flag 53 (particularly, a value of “1” indicating a case of failure) of the PE 40 corresponding to itself and three adjacent PEs among all nine PEs 40 related to the PE. For example, when there is a defect in the next PE 40 in front of itself, the access to the R registers R0 to R31 of the next PE 40 in front is selected. Similarly, when there is a defective PE 40 as well, access to the R registers R0 to R31 of the next adjacent PE 40 is selected.

  As shown in FIG. 6, the PE selection unit 63 includes a logic circuit as an example, and an input (instruction input) first includes an output indicating a defect from the defect flag 53 for each of the three neighbors (i.e., an instruction). In addition, there are the following seven control signal inputs from, for example, the GP 13 indicating which PE 40 stores the image data stored in the currently executed instruction. That is, C_en is a control signal that becomes active when a reference instruction of its own PE 40 is issued, L1_en is a control signal that becomes active when a reference instruction of the previous PE 40 is issued, and L2_en is two L3_en is a control signal that becomes active when the previous PE40 reference instruction is issued, L3_en is a control signal that becomes active when the three previous PE40 reference instructions are issued, and U1_en is the next PE40. It is a control signal that becomes active when a reference instruction is issued, U2_en is a control signal that becomes active when a reference instruction for the next PE40 is issued, and U3_en is issued by a reference instruction for the next PE40 This is a control signal that becomes active when activated.

  In addition, the control signal of the logic circuit determines the route 9 that determines the route that is actually opened by each PE 40 (that is, the route that is connected to the bus B1 leading to the R register of each PE 40). There are street control signals. That is, C_enable is a control signal that opens a gate that refers to its own PE 40 (that is, R register R0, etc .; hereinafter omitted), and L1_enable is a control signal that opens a gate of a path that references the previous PE 40. L2_enable is a control signal for opening the gate of the path referring to the previous PE40, L3_enable is a control signal for opening the gate of the path referring to the previous PE40, and L4_enable refers to the four previous PE40. This is a control signal that opens the gate of the path. U1_enable is a control signal for opening the gate of the path referring to the next PE40, U2_enable is a control signal for opening the gate of the path referring to the next PE40, and U3_enable refers to the PE40 after the third. A control signal for opening the gate of the path, and U4_enable is a control signal for opening the gate of the path referring to the PE40 that is four times later.

  On the other hand, the configuration of the logic circuit of the PE selection unit 63 has the configuration shown in FIG. 6 and is clear from the drawing, and thus detailed description thereof is omitted.

  As described above, when the PE selection unit 63 includes the above-described logic circuit configuration, out of all nine PEs 40 related to the PE, the adjacent PE 40 to be accessed by the PE based on a command from the GP 13 is defective. Then, it is possible to access the R register R0 and the like of the next adjacent PE 40, thereby relieving the entire SIMD type processor 51 and performing good processing and normal data transfer.

  If the number of spare wiring paths is increased, even if there are two or more failures, it is possible to cope with them, but when considering an increase in circuit scale and failure frequency, the degree shown in this embodiment is optimal.

  Next, the main points of the operation of the present embodiment after the self test will be described. FIG. 7 is a conceptual diagram showing a data flow when, for example, write control and read control are performed using the memory controller 21.

  7 is synchronized with the data transfer, the value of the defect flag 53 of each PE 40 is read through the control bit port of the external interface 17, and the data transfer is suppressed for the faulty PE. Used to do. As the transfer inhibition data, “0” is read for a normal PE 40 and “1” is read for a defective PE 40.

  When the memory controller 21 performs write control (transfer from the R register R0 etc. of the PE 40 to the memory 23), only the data D0, D2, D4 etc. of the PE 40 whose transfer inhibition data is “0” are controlled by the SCU 79 and the RAM. Based on the control of the unit 77, it is stored in the memory 23. That is, the data D1, D3, etc. of the PE 40 whose transfer inhibition data is “1” are not stored in the memory 23 but are thinned out under the control of the SCU 79.

  In addition, when the memory controller 21 performs read control (transfer from the memory 23 to the R register R0 of the PE 40, etc.), the data from the memory 23 is not updated for the PE 40 whose transfer suppression data is “1”. The same data as the transferred data D0, D1, etc. is transferred to the PE 40 having one PE number with a small number.

  According to such a configuration, even if there is a defective PE 40, it is possible to correctly transfer data between the memory 23 and the R register R 0 or the like built in each PE 40, and the SIMD type processor 51 is made effective. It is possible to rescue.

  The self-test program is downloaded to the program RAM 41 from, for example, an upper host processor.

  On the other hand, as shown in FIG. 4, the memory controller 21 can recognize a defective PE 40 when the SCU 79 inputs an output of control data from the external interface 17 based on each defect flag 53. Except for the processing related to this processing, the relationship between the memory controller 21 and the SIMD processor 51 is the same as the relationship between the memory controller 21 and the SIMD processor 11 shown in FIG.

  By the way, as shown in FIG. 8, the register controller 69 that controls the R register through the external interface is provided in each R register R0 shown as a register in FIG. 6 and FIG. However, it is provided individually. The operation of the register controller 69 is the same as in the above example. Specifically, first, when the address of a predetermined PE 40 to which the memory controller accesses through the external interface 17 is input, and a write control signal is input Outputs a write instruction signal to the port W1 such as the R register R0, for example, and causes the R register R0 or the like to fetch the image data transferred via the external interface 17 from the port D1 and temporarily store it. Second, when a read control signal is input via the external interface 17, for example, a read instruction signal is output to the port R1 such as the R register R0. For example, the read instruction signal is output to the external interface 17 via the port D1 to the R register R0. On the other hand, post-computed image data and the like that have been temporarily stored are transferred.

  On the other hand, for example, when the read signal from GP13 is input from port R2, for example, the R register R0 or the like transfers the stored image data to the PE selection unit 63 through the port D2. For example, when a write control signal from the GP 13 is input from the port W2, the R register R0 and the like fetch the image data after the calculation from the PE selection unit 63 from the port D2 and temporarily store it. It should be noted that the image data after the calculation after storage is transferred to the external memory controller 21 via the external interface 17 in accordance with the second control of the register controller 69.

  Next, the processing operation of the GP 13 when performing the self test will be described with reference to the flowchart shown in FIG. First, after power is turned on in step 801, a self-inspection program is downloaded from, for example, a host computer or the like in step 802, and inspection of GP13 is started in step 803. In step 804, it is determined whether the inspection result of GP13 is OK.

  When the inspection result of GP13 is NG, GP13 is recognized as a defective product and, for example, maintenance is performed. However, if the inspection result of GP13 is OK, in order to start the inspection of all PEs 40 in step 805, first, the inspection of the PE 40 with the address of PE = 0 is selected as the target PE. In step 806, the selected PE 40 is inspected. When inspecting PEs, for example, the same image data (test data) or the like is sequentially transferred to all the PEs 40 to perform the same arithmetic processing on each PE 40. Arbitrary inspections can be performed at any time, for example, when searching, or when sequentially transferring image data (test data) having predetermined characteristics that can be different individually and checking the results of each operation. .

  Subsequently, in step 807, it is determined whether or not the inspection result of the selected PE 40 is OK. If the inspection result is OK, in step 808, the address of the PE 40 to be inspected is incremented, and it is determined whether the final PE 40 has been inspected. If the final PE 40 has not been inspected, the process returns to step 806 to inspect the next selected PE 40. Thus, when the inspection up to the final PE 40 is completed, the process proceeds to step 819 to download the main program, and in step 820, the main program is executed.

  However, if it is determined in step 807 that the PE 40 whose inspection result is NG is found, the address of the PE 40 to be inspected is incremented in step 809 and it is determined whether or not the final PE 40 has been inspected. If the final PE 40 has not been inspected, the process proceeds to step 810. However, when the inspection up to the final PE 40 is completed, the process proceeds to step 819 to download the main program, and in step 820, the main program is executed.

  On the other hand, in step 810, the PE 40 next to the NG PE 40 is inspected, and in step 811 it is determined whether or not the inspection result is OK. As a result of the inspection, when the PE 40 that is NG is confirmed, the PE selection circuit 63 shown in FIG. 6 has a configuration that can cope with a case where only one of the three adjacent PEs is defective. If there are two or more defective PEs among the three adjacent PEs, the repair cannot be performed, and the entire SIMD type processor 51 is treated as a defective product. However, if the inspection result is OK, the process proceeds to step 812.

  In step 812, the address of the PE 40 to be inspected is incremented, and it is determined whether or not the final PE 40 has been inspected. If the final PE 40 has been inspected, the process proceeds to step 819. If the final PE 40 has not been inspected, the next selected PE 40 is inspected in step 813 and then the inspection result in step 814. It is determined whether or not is OK. As a result of the inspection, if the PE 40 that is NG is confirmed, the entire SIMD type processor 51 is handled as a defective product for the same reason as described above. However, if the result of the inspection is OK, the process proceeds to step 815.

  In step 815, the address of the PE 40 to be inspected is incremented, and it is determined whether or not the final PE 40 has been inspected. If the final PE 40 has been inspected, the process proceeds to step 819. If the final PE 40 has not been inspected, the next selected PE 40 is inspected in step 816, and then the inspection result in step 817. It is determined whether or not is OK. As a result of the inspection, if the PE 40 that is NG is confirmed, the entire SIMD type processor 51 is handled as a defective product for the same reason as described above. However, if the result of the inspection is OK, the process proceeds to step 818.

  In step 818, the address of the PE 40 to be inspected is incremented, and it is determined whether or not the final PE 40 has been inspected. If the final PE 40 has been inspected, the process proceeds to step 819. If the final PE 40 has not been inspected, the process proceeds to step 806.

  As described above, when a defective PE is detected in step 807, the inspection result is OK in step 811 after the next PE inspection in step 810, and the inspection result of the next PE is similarly detected in step 814. If it is OK and the inspection result of the next PE is OK in step 817 as well, the SIMD processor 51 can be relieved, and an inspection for this is performed.

  Next, a microprocessor according to a second embodiment of the present invention will be described with reference to FIGS. The microprocessor of this embodiment is also applied to the SIMD type processor. FIG. 10 is a block diagram showing a detailed configuration of the SIMD type processor according to the present embodiment. In FIG. 10, the same parts as those shown in FIG.

  As shown in FIG. 10, the SIMD type processor 111 of this embodiment is provided with a scaling flag 113 for each PE 40.

  As shown in FIG. 11, specifically, the scaling flag 113 includes a failure flag 53 similar to that shown in the second embodiment, a scaling flag 113 connected to the data bus of each PE 40, and The OR circuit 115 is configured to be active when the output of the defective flag 53 or the output of the scaling flag 113 is input and provides an output to a PE general-purpose register (such as the R register R0) of the PE 40.

  That is, a value input from the data bus by the write control signal output from the GP 13 is written in the scaling flag 113. The value of the scaling flag 113 is logically ORed with the value of the defect flag 53 and supplied to a PE general register (R register R0, etc.).

  The scaling flag 113 is connected to a data transfer port (not shown) for connection to the external interface 17 that controls access from the outside (memory controller 21). The data transfer can be inhibited by the memory controller 21 or the like by the value. Data transfer mainly includes data transfer such as image data before or after calculation. Further, the read / write control mode of the external memory controller 21 or the like can be changed to an enlargement / reduction mode according to the value of the scaling flag 113.

  The upper side of FIG. 12 illustrates the thinning write operation for realizing reduction in the scaling process often performed in digital copy, facsimile, or the like. The value of the scaling flag 113 of each PE 40 is, for example, 1-bit data of “0” or “1”. Here, as an example, PE1, PE4, and PE7 are used to construct correct thinning control data based on the setting from the GP 13. The value of the variable magnification flag 113 is set to “1”. As a result, the RAM control unit 77 (see FIG. 4) 77 based on the control of the SCU 79 thins out the image data of PE1, PE4, PE7, etc. as the address example among the PEs 40, and PE0, PE2, PE3, PE5, PE6. Data of general-purpose registers (R register R0, etc.) of PE40 such as PE8, PE9, etc. is written to the memory (RAM) 23.

  The lower side of FIG. 12 illustrates the operation of the scaling process when there is a defective PE. Here, the value of the scaling flag 113 of PE1 and PE6 is set to '1' as an example in order to configure correct decimation control data based on the setting from GP13, and PE2, PE4, and PE8 are examples of addresses. The failure flag 53 of PE 40 outputs “1” indicating failure. In this case, the decimation control data (transfer inhibition data) includes “1” indicating decimation in PE1, PE2, PE4, PE6, PE8, and the like. As a result, the RAM control unit 77 (see FIG. 4) 77 based on the control of the SCU 79 uses the general-purpose registers (R registers R0, etc.) of the PEs 40 such as PE0, PE3, PE5, PE7, PE9, etc., as address examples. Data is written to the memory (RAM) 23. That is, since the SIMD processor is reconfigured by skipping a defective PE, the write control data and the image data are stored as shown in the lower part of FIG. If the logical sum of the write control data and the failure PE information is the transfer inhibition data, the data of PE1, PE2, PE4, PE6, and PE8 are thinned as shown in the figure, and the data stored in the memory 23 or the like is It can be seen that it is exactly the same as the case of data without failure.

  The upper side of FIG. 13 illustrates an overlapping read operation for realizing enlargement among the scaling processes often performed in digital copying, facsimile, and the like. Here, as image data read from the memory 23 or the like, as address examples, the image data such as PE1, PE4, and PE7 has the same value as the data stored in the immediately preceding PEs PE0, PE3, and PE6. . Accordingly, PE1, PE4, and PE7 are skipped, and the image data read from the memory 23 or the like is stored in PE0, PE2, PE3, PE5, PE6, PE8, and PE9.

  The lower side of FIG. 13 illustrates the operation of enlargement processing when there is a defective PE. Here, as an example of an address, a case where PE2, PE4, PE8, etc. are defective is illustrated. If there is a defective PE, the SIMD processor 111 is reconfigured by skipping the defective PE, so the read control data is stored as shown in the figure. Similarly, the image data is stored as shown in the figure. If the logical sum of the read control data and the faulty PE information is the transfer inhibition data, the data stored in PE1, PE2, PE4, PE6, and PE8 overlaps with the data of the previous PE as shown in the figure. It can be seen that the data stored in the PE register file is exactly the same when there is no data. Data is stored in order by skipping faulty PEs. That is, according to the configuration of the present embodiment, it can be seen that zooming can be performed correctly even if there is a faulty PE.

  According to such a configuration, even when the PE 40 is defective, by performing a logical sum with the value of the scaling flag 113, it is possible to perform normal scaling processing on image data or the like regardless of the defective PE. There is an advantage that the SIMD type processor 111 is relieved and the scaling process can be performed, and the function is excellent.

  Next, a microprocessor according to a third embodiment of the present invention will be described with reference to FIG. The microprocessor according to the present embodiment is also applied to the SIMD type processor, and FIG. 14 is a block diagram showing the detailed configuration of the SIMD type processor according to the present embodiment. In FIG. 14, the same parts as those shown in FIG.

  As shown in FIG. 14, the SIMD type processor 211 of the present embodiment is different from the general-purpose register (R register R0, etc.) of each PE 40 in the second embodiment. Instead of the double flag 113, a variable magnification flag 213 provided independently for each general-purpose register R register of each PE 40 is newly provided. When the write control signal from the GP 13 is input to the port W1, for example, the zoom ratio data is input from the D1 port, for example, and when the read control signal is input to the port R1, for example, the zoom ratio flag 213 The data is output to a register (R register R0, etc.) and an OR circuit 215. The scaling flag 213 can set scaling data of an arbitrary scaling ratio based on the GP13 program.

  The scaling flag 213 is connected to the data bus B1 at a terminal D1, and data can be set by being controlled by the GP 13. When the write control signal is asserted to the port W1, data is written from the data bus B1 to the scaling flag 213. When the read control signal is asserted to R1, the contents of the scaling flag 213 are output to the data bus B1. The value of the scaling flag 213 is always output to the OR circuit 215.

  In the second embodiment, since only one scaling flag 113 is provided for each PE 40, a plurality of memories connected to the R register via the external interface 17 in the entire image processing. A plurality of memory controllers 21 can simultaneously perform scaling using a common scaling ratio with respect to the controller 21, but a scaling process using a different scaling ratio for each memory controller 21 is performed. Even when a common scaling factor is used, it is not possible to deal with the case where each memory controller 21 performs scaling not asynchronously but asynchronously.

  However, in this embodiment, each general-purpose register (R register R0, etc.) has a scaling factor 213 that can change the scaling factor one by one, and each of the individual OR circuits 215 sets the failure flag 53 of its own PE 40. A logical sum with the value is taken and supplied to the memory controller 21 via the external interface 17. The memory controller 21 can cope with the scaling process at the scaling factor indicated by the scaling flag 213 by the operation of the RAM control unit 77 via the control of the SCU 79.

  According to this configuration, it is possible to set an independent scaling factor for each of the plurality of memory controllers 21 by the scaling flag 213 for each of the plurality of general-purpose registers. In the image processing, it is possible to cope with a scaling process when there are a plurality of scaling ratios, and the plurality of memory controllers 21 can operate independently and asynchronously even when the scaling process is performed. Therefore, the degree of freedom as the system configuration of the image processing apparatus using the SIMD type processor 211 of the present embodiment is improved.

It is a block diagram which shows schematic structure of the technique used as the premise of this invention. It is a block diagram which shows the partial detailed structure of the technique used as the premise of this invention. It is a block diagram which shows the structure of the SIMD type | mold processor of the 1st Embodiment of this invention. 1 is a block diagram illustrating a configuration of a memory controller according to a first embodiment. FIG. It is a block diagram which shows the structure of T register of 1st Embodiment. It is a circuit block diagram which shows the structure of the PE selection part of 1st Embodiment. It is explanatory drawing explaining the data flow at the time of performing read / write control of 1st Embodiment. FIG. 2 is an enlarged view of a main part showing an enlarged main part of the SIMD type processor according to the first embodiment. It is a flowchart which shows the processing operation at the time of performing the self test of 1st Embodiment. It is a block diagram which shows the structure of the SIMD type | mold processor of the 2nd Embodiment of this invention. It is a circuit block diagram which shows the structure of the scaling flag of 2nd Embodiment. It is explanatory drawing explaining the flow of data at the time of performing the scaling process of reduction of 2nd Embodiment. It is explanatory drawing explaining the flow of data at the time of performing the scaling process of expansion of 2nd Embodiment. It is a block diagram which expands and shows the principal part structure of the SIMD type | mold processor of the 3rd Embodiment of this invention.

Explanation of symbols

11, 51, 111, 211 SIMD type processor 13 GP (global processor)
15 Processor Element Group 17 External Interface 21 Memory Controller 23 Memory 31 Register File 33 Arithmetic Array 35 7to1MUX
41 Program RAM
43 Data RAM
45 SE (Shift Expand: Shifter)
47 ALU
48 A register 49 F register B1 Bus R0 to R23, R24 to R31 General-purpose register (R register)
53 Defect flag 55 ID register 58 T register 59, 61 MPX
63 PE selector 64, 65 Multiplexer 67 AND circuit T7 to T0 Register 68 Wiring path 69 Register controller 71 Write buffer 73 Read buffer 75 External I / F controller 77 RAM controller 79 SCU (sequencer unit)
92 Buffer 113, 213 Scaling flag 115, 215 OR circuit

Claims (3)

In a microprocessor comprising a SIMD type processor having a plurality of processor elements for processing a plurality of data,
A defect flag indicating whether or not there is a defect in its own processor element is provided as a register different from the general-purpose register provided in advance for each processor element, and the defect flag sets individual data for each processor element by an instruction instruction. Is possible,
An ID register that stores data indicating the number of its own processor element and stores an incremented number except for the processor element of the defective flag when a defective flag is found,
A data transfer port for accessing the general-purpose register and the failure flag from the outside is provided,
A data transfer device for transferring data between the general-purpose register of each processor element and an external memory is connected to the data transfer port;
The microprocessor according to claim 1, wherein the data transfer device suppresses the data transfer according to the value of the defect flag and the ID register . 2. The microprocessor according to claim 1, wherein the individual data set for each processor element is a scaling control bit in image processing. 3. The microprocessor according to claim 1, wherein the value of the defect flag is set based on a result of a self-test of each processor element in the SIMD type processor.

Images