JP2004252825A - Simd type microprocessor capable of transferring data even when fault is occurred in pe - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SIMD type microprocessor capable of transferring data even in the case that a fault PE is occurred. <P>SOLUTION: In the SIMD type microprocessor having a plurality of processor elements for processing two or more pieces of data, a data transfer device is connected to a data transfer port for accessing a general purpose register incorporated in each processor element from the outside. The data transfer device is provided with a storage part for indicating whether or not each processor element is a fault, and the data transfer device performs control so as to suppress data transfer to the fault processor element by the contents of the data in the storage part. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a microprocessor, and more particularly, to a SIMD (Single Instruction-Stream Multiple Data-stream) microprocessor.
[0002]
[Prior art]
In the SIMD type microprocessor, the same arithmetic processing can be simultaneously performed on a plurality of data with one instruction. With this structure, the calculation is frequently used in applications related to processing that is the same but has a very large amount of data (for example, image processing in a digital copier or the like).
[0003]
In ordinary image processing in a SIMD microprocessor, high-speed processing is performed by arranging a plurality of processing units (Processor Elements [PE]; processor elements) in the main scanning direction and simultaneously executing the same calculation on a plurality of data. Calculation processing is possible.
[0004]
By the way, in recent years, the degree of integration of LSIs has been increasing due to the miniaturization of the manufacturing process, and the number of PEs can be increased even in SIMD type microprocessors. However, in a processor adopting a parallel processor configuration, such as an SIMD type, if even one of the plurality of arithmetic units has failed, it may not be possible to use the entire processor. Therefore, in the conventional SIMD type microprocessor, for example, a method of providing a redundant PE and replacing it with a faulty PE has been used.
[0005]
Patent Literature 1, Patent Literature 2, Patent Literature 3 and the like below show a technique of providing a redundant PE for replacing a defective processor. In this technique, when there is a failed PE, the parallel processor is rescued by allocating a signal specifying the PE to the redundant PE instead of the failed PE. Further, the processor disclosed in Patent Document 2 uses a mode in which data is transferred to and from the outside of the processor by outputting the data to an external output bus using a three-state buffer. Is configured. These techniques are effective when the number of PEs is small. However, when the number of PEs is large, the number of control lines that need to be set becomes large (assuming switching). There are drawbacks such as the need.
[0006]
In the prior arts shown in Patent Literatures 4, 5, and 6, each PE has a multiplexer of an output signal from an adjacent PE and a signal output by itself. The parallel processor is saved by bypassing and outputting the output signal from the PE. Further, in the processor of Patent Document 4, data transfer with the outside of the processor is performed by a shift register configuration. These configurations are relatively simple. However, since a shift register is used, for example, even when data transfer is performed in some PEs, it may be necessary to shift data in all PEs. Therefore, the time required for the transfer may increase.
[0007]
[Patent Document 1]
JP-A-9-22400
[Patent Document 2]
JP-A-9-288652
[Patent Document 3]
Patent No. 3005243
[Patent Document 4]
JP 2000-148998
[Patent Document 5]
JP-A-2002-169787
[Patent Document 6]
Special table 2001-527218
[0008]
[Problems to be solved by the invention]
An object of the present invention is to enable a SIMD microprocessor to perform data transfer even when a faulty PE occurs.
[0009]
[Means for Solving the Problems]
The present invention has been made to achieve the above object. The SIMD type microprocessor according to claim 1 according to the present invention,
It is a SIMD type microprocessor having a plurality of processor elements for processing a plurality of data. In the SIMD type microprocessor,
A data transfer device is connected to a data transfer port for externally accessing a general-purpose register included in each processor element,
The data transfer device has a storage unit that indicates whether each processor element has failed,
The data transfer device controls the data transfer to the failed processor element based on the content of the data in the storage unit.
[0010]
The SIMD type microprocessor according to claim 2 according to the present invention,
A self-test for checking whether or not each processor element operates normally is automatically executed in a timely manner.
The inspection result is automatically stored in the storage unit of the data transfer device.
An SIMD type microprocessor according to claim 1.
[0011]
The SIMD type microprocessor according to claim 3 according to the present invention,
The data transfer device is:
A first register for setting, as data, an address of a processor element from which transfer is to be started at the time of data transfer;
A first counter that counts up when an address of a processor element that has not failed has been issued,
Inhibiting data transfer until the value of the first counter is equal to the value of the first register;
An SIMD type microprocessor according to claim 1.
[0012]
The SIMD type microprocessor according to claim 4 according to the present invention,
When the value of the first counter becomes equal to the value of the first register, the value of the address of the processor element at that time is held,
When the data transfer is completed for all processor elements, the value of the address is set in the first register.
An SIMD microprocessor according to claim 3.
[0013]
The SIMD type microprocessor according to claim 5 according to the present invention,
The data transfer device is:
A second register for setting, as data, an address of a processor element whose transfer is to be terminated at the time of data transfer;
A first counter that counts up when an address of a processor element that has not failed has been issued,
When the value of the first counter becomes equal to the value of the second register, the value of the address of the external memory connected to the data transfer device at that time is held,
When the data transfer is completed for all processor elements, the value of the address of the external memory is set in the second register.
An SIMD type microprocessor according to claim 1.
[0014]
The SIMD type microprocessor according to claim 6 according to the present invention,
The data transfer device is configured to perform data transfer in synchronization with another data transfer device,
By the logical OR of the data being transferred by another data transfer device and the data of the storage unit indicating whether or not each processor element has failed,
Suppression of data transfer is controlled,
An SIMD type microprocessor according to claim 1.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
First, as a premise for describing a preferred embodiment according to the present invention, a schematic configuration of a SIMD type microprocessor 2, a memory 4, and a memory controller 6 will be described with reference to FIGS.
[0016]
FIG. 1 is a schematic block diagram of a SIMD microprocessor 2, a memory 4, and a memory controller 6 according to the present invention.
[0017]
<Global processor>
This block is a so-called SISD (Single Instruction Stream, Single Data Stream) type processor, has a built-in program RAM and data RAM, and decodes a program to generate various control signals (see FIG. 2). This control signal is supplied to the register file 16, the operation array 14, and the memory controller 6 in addition to the control of various built-in blocks. When a GP (global processor) instruction is executed, various arithmetic processing and program control processing are performed using a built-in general-purpose register, an ALU (arithmetic logic operation unit), and the like.
[0018]
<Register file>
It holds data processed by PE (processor element) instructions. The PE instruction is a SIMD (Single Instruction Stream, Multiple Data Stream) type instruction, and performs the same processing on a plurality of data held in the register file 16 simultaneously. The reading / writing of data from the register file 16 is controlled by the global processor 10. The read data is sent to the operation array 14 and is written into the register file 16 after the operation processing in the operation array 14.
[0019]
The register file 16 can be accessed from the memory controller 6 outside the processor via the external interface 8, and a specific register is read / written from outside independently of the control of the global processor 10.
[0020]
<Calculation array>
Operation processing of the PE instruction is performed. All control of the processing is performed by the global processor 10.
[0021]
<Memory controller>
By outputting a clock, an address, and read / write control to an external port and outputting a clock, an address, and read / write control to the memory 4, data transfer is performed between the register 20 of an arbitrary PE and the memory 4. All control of the processing is performed by the global processor 10.
[0022]
FIG. 2 is a block diagram of the SIMD type microprocessor 2 according to the present invention.
[0023]
The global processor 10 has a built-in program RAM for storing a program of the present processor and a data RAM for storing operation data. Further, a program counter (PC) for holding a program address, G0 to G3 registers which are general-purpose registers for storing data for arithmetic processing, a stack pointer (for holding an address of a save destination data RAM at the time of register saving and returning). SP), a link register (LS) for holding a call source address at the time of a subroutine call, an LI and LN register for holding a branch source address for IRQ and NMI, and a processor status register (P for holding a processor state). ) Is built-in.
[0024]
The GP instruction is executed using these registers and an unillustrated instruction decoder, ALU, memory control circuit, interrupt control circuit, external I / O control circuit, and GP operation control circuit.
[0025]
When the PE instruction is executed, the control of the register file 16 and the control of the operation array 14 are performed using an instruction decoder, a register file control circuit (not shown), and a PE operation control circuit.
[0026]
The register file 16 contains 32 8-bit registers 20 for each PE unit, and sets of 256 PEs are arranged in an array. The registers 20 are called R0, R1, R2,... R31 in the same PE. Each register 20 has one read port and one write port for the operation array 14, and is accessed from the operation array by an 8-bit read / write bus. Of the 32 registers, 24 (R0 to R23) can be accessed from outside the processor via the external interface 8, and read / write an arbitrary register 20 by inputting a clock, address, and read / write control from outside. it can.
[0027]
In access from outside the register 20, one register of each PE can be accessed by one external port. In that case, the number of the PE (0 to 255) is specified by the address input from the outside. Therefore, a total of 24 sets of external ports for register access are mounted.
[0028]
The numbers 0 to 255 are assigned to the PEs in order (for example, from the left in FIG. 2). The direction in which the PE number is smaller is referred to as “front”, and the direction in which the PE number is higher is referred to as “back”.
[0029]
The above-mentioned external access is made simultaneously to two (same) registers 20 by a pair of adjacent even-numbered PEs and odd-numbered PEs. That is, 16-bit data is accessed by one access.
[0030]
The operation array 14 includes a 16-bit ALU 18, a 16-bit A register 22, and an F register 24. In the operation by the PE instruction, the data read from the register 20 or the data given from the global processor 10 is used as an input on one side of the ALU 18 and the content of the A register 22 is used as an input on the other side. The result is stored in the A register 22. That is, the operation of the data of the A register 22 and the data given from the R0 to R31 registers 20 or the global processor 10 is performed.
[0031]
A 7-to-1 multiplexer 26 is placed at the connection between the register 20 and the ALU (arithmetic unit) 18. Regarding the parallel PEs, the data of the register 20 of the PE 1, 2, or 3 away from the front, the data of the register 20 of the PE 1, 2, or 3 away behind, or the center (that is, the ALU 18 The data of the register 20 of the PE is selected as the operation target. The 8-bit data of the register 20 is input to the ALU 18 by shifting the arbitrary bits to the left by a shift & extension circuit. Further, the execution / invalidation of the execution of the operation is controlled for each PE by an 8-bit condition register (T) (see FIG. 3) not shown in FIG. 2, so that only a specific PE can be selected as an operation target.
[0032]
<< 1st Embodiment >>
FIG. 3 is a partial block diagram of the SIMD type microprocessor 2 according to the first embodiment of the present invention. The processor 2 in FIG. 3 can reconfigure the processor element block 12 except for the failed PEs when some of the PEs have a failure, so that the entire processor can be rescued.
[0033]
Each of the PEs is subjected to a self-test by the global processor 10 at the time of power-on or at the time of system initialization to determine whether or not it operates normally. As a result of the self-test, the fault flag 30 (described later) is set to “0” for a normal PE, and the fault flag 30 is set to “1” for a faulty PE. Is performed. Thereafter, the actual program is downloaded to the program RAM and the program is executed. The program for the self-test is built in the ROM or downloaded from an upper host processor.
[0034]
Each PE has a built-in 1-bit register called a defective flag 30. The result of the self test is set in the failure flag 30. The failure flag 30 is formed of a shift register, and a value can be set by the global processor 10. The value of the failure flag 30 is input to the above-mentioned condition register (T register) 32, and is controlled such that the execution of the operation is always invalidated in the PE that has failed as shown in FIG.
[0035]
Each PE is associated with the data of the register 20 of the PE which is located one, two or three places forward, the data of the register 20 of the PE which is located one, two or three places backward, or the center ( That is, a path is provided so that the data in the register 20 of the PE of the ALU 18) can be selected as an operation target. Further, each PE has one spare wiring path in the front and one in the rear in order to ignore any failed one of the seven PEs to be targeted, if any.
[0036]
That is, if there is no faulty PE, each of the PEs is located ahead (abbreviated as L1), 2 (abbreviated as L2), 3 (abbreviated as L3), 4 (abbreviated as L4) with respect to the parallel PEs. The data related to the PEs separated by only 1 (abbreviated as U1), 2 (abbreviated as U2), 3 (abbreviated as U3), and 4 (abbreviated as U4) are referred to functionally. It is possible.
[0037]
The multiplexer (PE selection unit) 26 for selecting the PE to be referred to refers not only to the path for referring to the data of the register of the PE itself but also to the data from the registers of the PEs up to four in the forward and backward directions. A path from the failure flag 30 of the PE, which is not shown, but one, two, and three ahead of the own PE, and a path from the failure flag 30 of the PE one, two, and three behind. Is entered. Further, a control signal is input from the global processor 10 indicating whether the instruction currently being executed is an instruction referring to data of a register in front of, behind, or of itself as viewed from its own PE.
[0038]
In the PE selection unit 26, control is performed based on the preceding and following failure flags 30 and the control signal so as to open the wiring path avoiding the faulty PE. For example, if the PE immediately preceding the own PE has failed, and if an instruction that refers to the immediately preceding PE has been issued, a path from the immediately preceding PE is opened. When an instruction that refers to the two-preceding PE is issued, control is performed to open the path from the three-preceding PE.
[0039]
FIG. 4 is a schematic circuit diagram for control performed when a failure occurs in three PEs in front of or behind a certain PE.
[0040]
C_en, L1_en to L3_en, and U1_en to U3_en indicate which instruction the currently executing instruction refers to data stored in which PE. In this order, C_en (refer to own PE) and L1_en (one forward) , L2_en (see two PEs ahead), L3_en (see three PEs ahead), U1_en (see one PE behind), U2_en (see two PEs behind), U3_en (see three PE behind) PE).
[0041]
C_enable, L1_enable to L4_enable, and U1_enable to U4_enable indicate which wiring path is actually opened in each PE, and C_enable (the gate that refers to the own PE is open) and L1_enable (the previous PE). L2_enable (the gate that refers to the two previous PEs is open), L3_enable (the gate that refers to the three previous PEs is open), L4_enable (the gate that references the fourth PE is U1_enable (opens the gate that refers to the next PE), U2_enable (opens the gate that references the second PE), U3_enable (opens the gate that refers to the third PE), U4_enable (opens) A gate that refers to the next four PEs It is open).
[0042]
Referring back to FIG. Each PE further has an ID register 34 indicating the number of the PE itself. The value of the ID register 34 is input to the ALU 18 via the data bus, and the result of comparison with the immediate data supplied to the second immediate data bus 36 (FIG. 3) in the ALU 18 is reflected in the T register 32. It is possible to do.
[0043]
As the value of the ID register 34, a number that is sequentially incremented from 0 is stored except for the PE determined to have failed during the self-test. In image processing, processing such as loading the same value into every fourth PE, such as loading a dither table, is required. It is possible to deal with it. In such a configuration, if there are no more than two faults in four consecutive PEs, the entire processor can function. Although it is possible to cope with the case where there are two or more faults by adding a spare wiring route, it is possible to cope with the increase in the circuit scale and the frequency of the faults. It is thought. FIG. 6 shows a flow of the self-test.
[0044]
Further, in the processor 2 of the present embodiment, data can be transferred between the memory controller 6 outside the processor and the register file 16 of the PE via the external interface 8, but an address for specifying the PE is used. For the signals such as read / write control and clock, it is not necessary to consider the faulty PE by appropriate setting of the memory controller 6 described later. For example, an operation such as providing a redundant PE and exchanging address control is completely unnecessary.
[0045]
FIG. 7 shows a configuration of the memory controller 6 according to the first embodiment of the present invention. The memory controller 6 includes a write buffer unit 40 for writing data to the memory 4, a read buffer unit 42 for reading data from the memory 4, an external interface control unit 44 for controlling the PE register file 16, a memory, 4 includes a RAM control unit 46 for controlling the control unit 4 and a sequence unit (SCU) 48. The memory controller 6 is connected to the register file 16 of the SIMD type microprocessor 2 via a data transfer port in the external interface 8, transfers data from the register file 16 to the memory 4, and transfers data from the memory 4 to the register file 16. Transferring. The data transfer port has an output port and an input port. The registers controlled by the memory controller 6 are mapped in the I / O space, and are readable and writable in accordance with an instruction from the global processor 10.
[0046]
The output port of the external interface 8 is connected to the write buffer unit 40, and the input port of the external interface 8 is connected to the read buffer unit 42. The data transfer ports have independent input and output ports for even PEs (in PE numbers) and odd PEs, respectively. One cycle of even and odd (immediately after) one at a time in one cycle. The data of the set of PEs can be accessed. On the other hand, the data bus between the write buffer unit 40 / read buffer unit 42 and the memory 4 has a data width of 4 PEs each, and can access data of 4 PEs at a time in one cycle. In this embodiment, the data for one PE is 8 bits. Therefore, the bit width of the data bus between the external interface 8 and the write buffer unit 40 and the read buffer unit 42 is 16 bits. The data bus between the memory controller 6 and the memory 4 has a bit width of 32 bits.
[0047]
As a result, the transfer between the memory 4 and the memory controller 6 only needs to be performed once while the transfer between the data transfer port of the external interface 8 and the memory controller 6 is performed twice.
[0048]
The write buffer unit 40 of the memory controller 6 takes in the data output from the external interface 8 twice, shapes it into data for four PEs, and transfers the data to the memory 4. Further, the read buffer unit 42 performs an operation of transferring the data for four PEs read from the memory 4 to the external interface 8 twice.
[0049]
FIG. 8 shows the case of write transfer (transfer from a PE register file to a memory) and the case of read transfer (transfer from a memory to a PE register file) using the memory controller 6 of the first embodiment. Shows how data is transferred.
[0050]
When performing data transfer, the memory controller 6 performs data transfer using transfer inhibition data indicating whether each PE has failed. The transfer inhibit data is read from a failure register described later in synchronization with the data transfer, and is used to inhibit the data transfer for the failed PE. As the transfer inhibition data, “0” is read for a normal PE and “1” is read for a faulty PE. At the time of the write transfer, only the data of the PE whose transfer inhibition data is "0" is stored in the memory 4, and the data of the PE whose transfer inhibition data is "1" is thinned out without being stored in the memory 4. At the time of read transfer, the same data as the data transferred to the PE with one less PE number is sent to the PE whose transfer inhibition data is “1”, and the data from the memory 4 is not updated. (Do not proceed).
[0051]
FIG. 9 is a schematic block diagram of the memory controller 6 according to the first embodiment of the present invention. The write buffer unit 40 and the read buffer unit 42 have dedicated ports for even-numbered PEs and odd-numbered PEs, and each access data for 2 PEs in one cycle.
[0052]
The write buffer unit 40 is configured to perform a write access to the memory 4 when data for 4 PE is stored in the buffer. The data for 2 PEs supplied from the transfer port of the external interface 8 to the write buffer unit 40 is first stored in the first-stage flip-flop 402 and then transferred to the next-stage flip-flop 404. Subsequently, the provided data for 2PE is stored in the flip-flop 402 of the first stage. Then, the data for 4 PEs stored in the flip-flops (402, 404) are stored in the latch 406, respectively. When the data for 4 PEs is stored in the latch 406, the write buffer unit 40 performs a write access to the memory.
[0053]
The read buffer unit 42 stores the data read for 4 PEs from the memory 4 in the flip-flop 422 as a buffer. The multiplexer 424 selects two PEs out of the four PEs and stores them in the latch 426. The data stored in the latch 426 is transferred to the register file 16 of the SIMD type microprocessor 2 via the external interface 8. When the transfer of data for 4 PEs is completed, read access to the memory 4 is performed again. Since the memory 4 can access data for 4 PEs at a time, an interface with the SIMD type microprocessor 2 can be obtained if access can be made once in two cycles, and the access time limit of the memory 4 can be relaxed.
[0054]
The RAM control unit 46 is controlled by a control line from a sequence unit 48 described later, and outputs a clock, address, read / write control, and byte select to the memory 4. The RAM control unit 46 includes blocks such as a RAM address adder / subtractor 462, a write pointer register 464, a read pointer register 466, and a multiplexer 460. Each block is connected via an address setting bus (hereinafter abbreviated as AB) 468.
[0055]
The write pointer register 464 is a register storing a pointer to be written to the memory 4 next, and the read pointer register 466 is a register storing a pointer to be read from the memory 4 next. After the access of the memory 4 to the write pointer register 464 and the read pointer register 466, the pointer updated by the RAM address adjuster 462 is input from the AB 468 and stored. The RAM address adder / subtractor 462 adds a value corresponding to the RAM access size to the value of the write pointer register 464 at the time of write access and the value corresponding to the RAM access size at the time of read access, and subtracts a value obtained by subtracting the value at the time of LIFO operation mode. Output to AB468.
[0056]
The external interface control section 44 outputs the address, clock, and read / write control signal of the PE to the external interface 8 as shown in FIG. 7, and outputs the data of the register 20 of each PE in the SIMD type microprocessor 2. It is possible to read and write. The external interface control unit 44 includes a PE address counter 4402, a transfer number counter 4404, a valid data number counter 4406, and a failure register unit 4408. The PE address counter 4402 is an up counter that is initially loaded with a value stored in the transfer start PE address register 4414 at the start of data transfer, and generates an address of a PE to which data is transferred. The transfer number counter 4404 is a down counter that can initially load the number of data to be transferred, and is used to manage the number of transfers. The transfer number counter 4404 is initially loaded with the value of the write number register 4410 in the case of a write transfer, and initially loaded with the value of the read number register 4412 in the case of a read transfer.
[0057]
The valid data number counter 4406 is a counter for managing the number of valid data stored in the memory 4. When data is transferred from the memory 4 to the PE register file 16, the number of valid data is larger than the number of transferred data. Only transfer is performed. With this configuration, data loss is prevented.
[0058]
The failure register unit 4408 stores a failure register that records whether each PE has failed. In the present embodiment, it is composed of 16 registers (failure register 0 to failure register 15) having a 16-bit width, and the result of testing each PE at the time of power-on or system initialization is written from the GP. That is, in the fault register 0, bit 0 is the fault information of PE0 (normal: 0, fault: 1), bit 1 is the fault information of PE1 (normal: 0, fault: 1),. ,...,..., Bit 15 stores failure information (normal: 0, failure: 1) of PE 15. Similarly, the failure register 1 stores failure information of the PEs 16 to 31. ... (Omitted)..., The failure register 15 stores failure information of the PEs 240 to 255.
[0059]
The value of the fault register is extracted as shown in FIG. 10 based on the value of the PE address counter 4402, and fault information for the currently accessed 2PE is output to the sequence unit 48 as transfer inhibition data. At this time, it is also used to determine an increment (decrement) value of the values of the transfer number counter 4404 and the valid data number counter 4406.
[0060]
The sequence unit 48 includes an address decoder and a control register. The global processor 10 can control the entire memory controller 6 and monitor the internal state of the memory controller 6 by accessing a control register mapped in the I / O space. At the time of the write transfer, the sequence unit 48 detects the value of the transfer suppression data, and when the transfer suppression data is “0”, causes the data to be written to the buffer in the write buffer unit. When the transfer suppression data is “1”, the data is prevented from being stored in the buffer in the write buffer unit. The write buffer unit 40 does not output a transfer request to the memory 4 to the RAM control unit 46 until data for 4 PEs is stored, except for the exceptions at the start and end of the transfer. Update, clock, read / write control, and byte select output to the memory 4 are not performed until data for 4 PEs is stored in the write buffer unit 40. The data read from the data transfer port of the SIMD type microprocessor 2 continues irrespective of the transfer inhibition data. At the time of read transfer, the sequence unit 48 detects the value of the transfer inhibition data, and when “1” is set, controls the multiplexer 424 of the read buffer unit 42 to change the immediately preceding PE address. The data to be transferred to the register of the owning PE can be output again. The read buffer unit 42 transfers the read data to the memory 4 to the RAM control unit 46 until all the data of 4 PEs read from the memory 4 becomes unnecessary, except for the exceptions at the start and end of the transfer. Since the request is not output (for example, if the transfer inhibition data is always “0” until the access to the data transfer port is performed twice, on the other hand, while the transfer inhibition data is “1”, The data will not be unnecessary), the updating of the read pointer register 466, the clock to the memory 4, the read / write control, and the output of the byte select will not be performed until all the data for 4 PEs are unnecessary. The data writing to the external interface 8 of the SIMD type microprocessor 2 continues irrespective of the transfer inhibition data.
[0061]
In the present embodiment, the fault registers are incorporated in the external interface control unit 44. However, when there are a plurality of memory controllers 6, the fault registers can be referred to by the plurality of memory controllers 6, thereby reducing the number of registers. Can be reduced.
[0062]
According to the configuration according to the present embodiment, even if there is a faulty PE, the address between the register file 16 and the read / write control signal are correctly reconstructed between the register file 16 and the memory 4 without reconfiguring. Data transfer can be performed.
[0063]
<< 2nd Embodiment >>
FIG. 11 is a schematic block diagram of the external interface control unit 44 of the memory controller 6 according to the second embodiment of the present invention.
[0064]
The external interface unit 44 is provided with an effective address counter 4418 and a comparator 4416 in addition to the configuration of the first embodiment shown in FIG. The effective address counter 4418 is an up counter that counts up only when accessing a normal PE. The comparator 4416 is configured to compare the value of the effective address counter 4418 with the transfer start PE address register 4414 and output a transfer inhibition control signal to the fault register unit 4408 until they match. The transfer inhibition control signal is ORed with data selected (extracted) from the fault register to generate transfer inhibition data. Further, the transfer suppression control signal is used for stopping the count-up and count-down of the transfer number counter 4404 and the valid data number counter 4406. The circuit configuration for that is shown in FIG. The PE address counter 4402 is composed of an up counter that is initially loaded with “0” at the start of data transfer.
[0065]
In the configuration of the first embodiment shown in FIG. 9, a value with an offset equal to the number of failed PEs needs to be set as the transfer start PE address. Since the effective address counter 4418 which is counted up when accessing a PE having no failure is set, the transfer start address can be set without considering the failure related to the PE. However, even when the transfer start PE address register 4414 is not “0”, the transfer starts slightly from the PE number “0”, so that the time required for the transfer slightly increases.
[0066]
<< 3rd Embodiment >>
FIG. 12 is a schematic block diagram of the external interface control unit 44 of the memory controller 6 according to the third embodiment of the present invention.
[0067]
The external interface control unit 44 includes a multiplexer 4420 that can select either “0” or the value of the transfer start PE address register 4414 as the initial load value of the PE address counter 4402. When the value of the effective address counter 4418 is equal to (compared with) the value of the transfer start PE address register 4414, the value of the PE address counter 4402 is reloaded (reloaded) into the transfer start PE address register 4414. Has become.
[0068]
At the time of data transfer, in the first data transfer, a predetermined value is set in the transfer start PE address register 4414, and the initial load value “0” is set in the PE address counter 4402. Thereafter, when the value of the transfer start PE address register 4414 becomes equal to the value of the effective address counter 4418, the value of the PE address counter 4402 is reloaded. In other words, a value with an offset equal to the number of failed PEs is stored in the transfer start PE address register 4414. Therefore, in the second data transfer, the initial load value of the PE address counter 4402 may be used as the value of the transfer start PE address, and the reload of the transfer start PE address register 4414 may be prevented from being executed.
[0069]
In the third embodiment, the time required for the transfer is slightly increased only at the start of the data transfer repeated a plurality of times, and the time required for the data transfer in the second and subsequent transfers is different from that in the first embodiment. It is similarly shortened.
[0070]
Here, a method of transferring pixel data when using the SIMD type microprocessor 2 having a smaller number of PEs than the number of pixels in the main scanning direction will be described. A third embodiment is used.
[0071]
FIG. 13 is an explanatory diagram of a method of transferring pixel data when using a SIMD microprocessor 2 having a smaller number of PEs than the number of pixels in the main scanning direction.
[0072]
When the number of PEs is smaller than the number of pixels in the main scanning direction, the pixel data in the main scanning direction is appropriately divided, and the SIMD microprocessor 2 repeats the arithmetic processing as necessary. The memory controller 6 supplies the divided pixel data from the memory 4 to the register file 16 of the PE of the SIMD type microprocessor 2.
[0073]
Normally, in the image processing using the SIMD type microprocessor 2, if processing including a process of referring to pixel data before and after the pixel of interest, such as a filtering process, is performed, the “SIMD” (that is, a row of all the parallel PEs) is obtained. Invalid data will be stored in the PEs at both ends. Therefore, when storing data from the register file 16 of the PE to the memory 4, it is necessary to store the data excluding data at both ends. On the other hand, when transferring data from the memory 4 to the register file 16 of the PE, it is necessary to transfer reference pixel data before and after the pixel of interest as well. That is, the transfer of the pixel data in the weighting process such as the filter process is performed in the following order. Here, the number of reference pixels is a.
[0074]
(1) Transfer unprocessed pixel data from the memory 4 to the corresponding register file 16 of the PE of the SIMD microprocessor 2.
(2) Image processing by the SIMD type microprocessor 2 is performed. At this time, the data of the both ends a of “SIMD” (the arrangement of all the parallel PEs) becomes invalid due to the absence of the reference pixel. That is, the shaded portion in FIG. 13 is the number of effective pixels.
(3) The processed pixel data is transferred from the SIMD microprocessor 2 to the memory 4. At this time, the effective pixels excluding the pixels at both ends a are transferred to the memory 4.
[0075]
With reference to FIG. 13, transfer of pixel data between the memory 4 and the SIMD type microprocessor 2 will be described. The SIMD type microprocessor 2 includes n PEs, that is, PE0 to PEn-1, and sends pixel data from the memory 4 to these PEs. After performing image processing, the pixel data is transferred from these PEs to the memory 4. Is done.
[0076]
It is assumed that the memory 4 stores pixel data before image processing in order from address 0. First, in the first transfer, that is, in the first “SIMD” transfer in the figure, a-ends at both ends of the PE array of the SIMD microprocessor 2 are transferred as reference pixels.
[0077]
When the processed pixel data is transferred to the memory 4, the pixel data to be transferred are a to (na−1) out of the n pixels from PE 0 to PEn−1, because the a pixel data before and after are invalid. Up to (n−2 × a) pixels.
[0078]
In the 2nd “SIMD” transfer, since the pixels from (na) to (2n−3 × a−1) are processed as the pixel of interest, (n−2 × a) to (n−) are used as reference pixels. a-1) and (2n−3 × a) to (2n−2 × a−1) pixel data. After the data processing, (n−2 × a) pixels (n−a) to (2n−3 × a−1) are stored in the memory 4.
[0079]
Even when the number of divisions in the main scanning direction is large, the same processing is simply repeated. To implement the above processing, in the case of data writing to the memory 4, the external interface control unit 44 of the PE of this embodiment sets “a” in the transfer start PE address register 4414, and What is necessary is just to set “(n−2 × a)” in the counter 4404.
[0080]
Since the above setting numbers are all based on the PE address, there is no need to change the setting for each “SIMD”. In the case of reading data from the memory 4, an operation of returning the read pointer register 466 after the transfer is completed is necessary. In the above example, the value is returned to (n−2 × a). In the RAM control unit 46 according to the first embodiment, the value of the read pointer register 466 needs to be set from the global processor 10 after the transfer is completed. In the case of writing data to the memory 4, it is not necessary to perform an operation on the write pointer register 464.
[0081]
<< 4th Embodiment >>
FIG. 14 is a schematic block diagram of the external interface control unit 44 of the memory controller 6 according to the fourth embodiment of the present invention. FIG. 15 is a schematic block diagram of the RAM control unit 46 of the memory controller 6 according to the fourth embodiment of the present invention.
[0082]
The external interface control unit 44 has the same configuration as that of the third embodiment, but is configured to output the PE address and the effective address to the RAM control unit 46. The RAM control unit 46 shown in FIG. 15 is obtained by further adding a read offset generator 4610 to the RAM control unit 46 shown in FIG. In the data transfer from the memory 4 to each register file 16 of the PE of the SIMD type microprocessor 2 by the read offset generator 4610, the RAM control unit 46 returns the value of the read pointer register 466 after the transfer to the PE is completed. Is set to be able to.
[0083]
The read offset generator 4610 monitors the effective address selected by the multiplexer 4614 at the time of the first transfer, and when the effective address becomes equal to the set value, reloads the effective address value into the read offset value register 4612. Then, the value of the read pointer register 466 at that time is held, and the transfer is continued until the set number of transfers is completed. When the transfer is completed, the stored value is reloaded into the read pointer register 466. In the second and subsequent transfers, the PE address is selected by the multiplexer 4614 (instead of the effective address) and input to the read offset generator 4610. It is preferable to control so that the reload of the read offset value register 4612 itself is not performed. In the example shown in FIG. 13, “(n−2 × a−1)” is set. Since all the setting values are based on the PE address, there is no need to change the setting for each “SIMD” as in the RAM control unit 46 of the first embodiment.
[0084]
According to the fourth embodiment, as in the case of the second embodiment of FIG. 11, only “0” needs to be selected as the initial load value of the PE address counter 4402 only at the time of the first transfer. When it is necessary to use the read offset function (that is, when there is a process of referencing left and right pixels such as filter processing, it is necessary to process image data in an overlapping manner for each "SIMD") Also, the processing can be performed without considering the faulty PE.
[0085]
<< 5th Embodiment >>
FIG. 17 is a schematic block diagram of the fault register unit 4408 of the memory controller 6 according to the fifth embodiment of the present invention.
[0086]
The memory controller 6 has two external write control signals for determining whether to thin out the data of the adjacent even-numbered PEs and odd-numbered PEs during the write transfer, and the adjacent even-numbered PEs during the read transfer. Two external read control signals for determining whether or not to write the same data as before when writing the data of the PEs of the number and the odd-numbered PEs are input.
[0087]
When scaling is performed in the write transfer, the thinning write signal is enabled, and the logical sum of the data selected (extracted) from the fault register and the external write control signal input from outside the memory controller 6 is used to inhibit the transfer. Output as data. When scaling is performed in the read transfer, the overlapping read signal is enabled, and the logical sum of the data selected (extracted) from the fault register and the external read control signal input from outside the memory controller 6 is transferred. Output as suppression data.
[0088]
Although not shown, the memory controller 6 has an external terminal for setting a timing to start transfer in order to synchronize with an external write control signal and an external read control signal. An external synchronization signal for starting transfer is input to the sequence unit 48, and when the synchronization signal is asserted, the sequence unit 48 starts transfer.
[0089]
According to the fifth embodiment, even if there is a faulty PE, it is possible to perform a scaling process often performed in a digital copier, a facsimile, or the like.
[0090]
The upper part of FIG. 18 illustrates a thinning-out write operation for realizing reduction among the scaling processes often performed in a digital copier or a facsimile. In the upper part of FIG. 18, the pixel data such as PE0, PE2, PE3, PE5, PE6,... Is stored in the memory 4 as it is, and the pixel data such as PE1, PE4, PE7,. Have been thinned out.
[0091]
The lower side of FIG. 18 illustrates the operation when there is a faulty PE. The figure shows a case where there is a failure in PE2, PE4, PE8,... If there is a faulty PE, the SIMD microprocessor skips the faulty PE and is reconfigured, so that the write control data is stored as shown in the figure. The image data is also stored as shown in the figure.
[0092]
Assuming that the logical sum of the write control data and the fault PE information is transfer inhibition data, the data of PE1, PE2, PE4, PE6, and PE8 is thinned out as shown in the figure, and the data stored in the memory 4 is faulty. It can be seen that the data is completely the same as the case without the data.
[0093]
The upper part of FIG. 19 illustrates an overlapping read operation for realizing enlargement, out of scaling processing often performed in a digital copier, a facsimile, or the like. In the upper part of FIG. 19, the pixel data such as PE1, PE4, PE7,... Have the same value as the data stored in the immediately preceding PEs PE0, PE3, and PE6.
[0094]
The lower side of FIG. 19 illustrates the operation when there is a faulty PE. The figure shows a case where there is a failure in PE2, PE4, PE8,... If there is a faulty PE, the SIMD microprocessor skips the faulty PE and is reconfigured, so that the read control data is stored as shown in the figure. The image data is also stored as shown in the figure.
[0095]
Assuming that the logical sum of the read control data and the fault PE information is the transfer inhibition data, the data stored in PE1, PE2, PE4, PE6, and PE8 overlap the data of the immediately preceding PE as shown in FIG. It can be seen that when there is no data, the data is exactly the same as the data stored in the register file of the PE. (Data is stored in order, skipping faulty PEs.)
[0096]
That is, according to the fifth embodiment, it can be understood that scaling can be performed correctly even if there is a faulty PE.
[0097]
【The invention's effect】
By utilizing the present invention, the following effects can be obtained.
[0098]
Diagnosis of PE failure is performed, and data transfer can be performed except for the PE that has failed. Therefore, even if there is a faulty PE, the SIMD type microprocessor can operate normally.
[0099]
Also, when performing data transfer, it is possible to specify a PE for starting data transfer or a PE for ending data transfer. Therefore, when the number of PEs is smaller than the pixel data to be processed, a data joint is considered. Data transfer can be performed. In that case, in the second and subsequent data transfers, the address of the PE that starts the transfer can be specified, so that the number of cycles required for the data transfer can be reduced.
[0100]
In the SIMD type microprocessor, it is possible to perform the scaling process of the image processing even if there is a faulty PE.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a SIMD microprocessor, a memory, and a memory controller according to the present invention.
FIG. 2 is a block diagram of a SIMD type microprocessor according to the present invention.
FIG. 3 is a partial block diagram of the SIMD type microprocessor according to the first embodiment of the present invention.
FIG. 4 is a schematic diagram of control for a SIMD microprocessor according to the first embodiment of the present invention which is performed when a failure occurs in three PEs in front of or behind a certain PE; It is a circuit diagram.
FIG. 5 is a circuit of a T register in a portion where a failure flag is input.
FIG. 6 is a flowchart of a self-test for determining a defective flag.
FIG. 7 is a block diagram of a memory controller according to the first embodiment of the present invention.
FIG. 8 shows the case of write transfer (transfer from a PE register file to a memory) and read transfer (transfer from a memory to a PE register file) using the memory controller of the first embodiment. FIG. 4 is a schematic diagram showing how data is transferred.
FIG. 9 is a schematic block diagram of a memory controller according to the first embodiment of the present invention.
FIG. 10 is a circuit for generating transfer suppression data.
FIG. 11 is a schematic block diagram of an external interface control unit of a memory controller according to a second embodiment of the present invention.
FIG. 12 is a schematic block diagram of an external interface control unit of a memory controller according to a third embodiment of the present invention.
FIG. 13 is an explanatory diagram of a method of transferring pixel data when using a SIMD microprocessor having a smaller number of PEs than the number of pixels in the main scanning direction.
FIG. 14 is a schematic block diagram of an external interface control unit of a memory controller according to a fourth embodiment of the present invention.
FIG. 15 is a schematic block diagram of a RAM control unit of a memory controller according to a fourth embodiment of the present invention.
FIG. 16 shows a configuration of a circuit that uses a transfer inhibition control signal to stop counting up and counting down of a transfer number counter and a valid data number counter.
FIG. 17 is a schematic block diagram of a fault register unit of a memory controller according to a fifth embodiment of the present invention.
FIG. 18 is a schematic diagram of a thinning-out write operation for realizing reduction in a scaling process performed by a digital copier or a facsimile.
FIG. 19 is a schematic diagram of an overlapping read operation for realizing enlargement in a scaling process performed by a digital copier or a facsimile.
[Explanation of symbols]
2 SIMD microprocessor, 4 memory, 6 memory controller, 8 external interface, 16 register file, 20 register, 40 write buffer unit 42 read buffer unit, 44 external interface control unit, 46 RAM control unit, 48 sequence unit.

Claims (6)

In a SIMD type microprocessor having a plurality of processor elements for processing a plurality of data,
A data transfer device is connected to a data transfer port for externally accessing a general-purpose register included in each processor element,
The data transfer device has a storage unit that indicates whether each processor element has failed,
The data transfer device controls the data transfer to the failed processor element based on the content of the data in the storage unit.
SIMD type microprocessor. A self-test for checking whether or not each processor element operates normally is automatically executed in a timely manner.
The inspection result is automatically stored in the storage unit of the data transfer device.
The SIMD type microprocessor according to claim 1. The data transfer device is:
A first register for setting, as data, an address of a processor element from which transfer is to be started at the time of data transfer;
A first counter that counts up when an address of a processor element that has not failed has been issued,
Inhibiting data transfer until the value of the first counter is equal to the value of the first register;
The SIMD type microprocessor according to claim 1. When the value of the first counter becomes equal to the value of the first register, the value of the address of the processor element at that time is held,
When the data transfer is completed for all processor elements, the value of the address is set in the first register.
The SIMD type microprocessor according to claim 3. The data transfer device is:
A second register for setting, as data, an address of a processor element whose transfer is to be terminated at the time of data transfer;
A first counter that counts up when an address of a processor element that has not failed has been issued,
When the value of the first counter becomes equal to the value of the second register, the value of the address of the external memory connected to the data transfer device at that time is held,
When the data transfer is completed for all processor elements, the value of the address of the external memory is set in the second register.
The SIMD type microprocessor according to claim 1. The data transfer device is configured to perform data transfer in synchronization with another data transfer device,
By the logical OR of the data being transferred by another data transfer device and the data of the storage unit indicating whether or not each processor element has failed,
Suppression of data transfer is controlled,
The SIMD type microprocessor according to claim 1.

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