JP4234612B2 - SIMD type processor - Google Patents

Description

  The present invention relates to a microprocessor, and more particularly to a SIMD (Single Instruction-stream Multiple Data-stream) type microprocessor.

  In the SIMD type microprocessor, the same arithmetic processing can be executed simultaneously on a plurality of data with one instruction. Due to this structure, the calculation is the same but the data amount is very large, for example, in the application related to the image processing in the digital copier, etc.

  In normal image processing in a SIMD type microprocessor, a plurality of arithmetic units (Processor Element [PE]; processor elements) are arranged in the main scanning direction, and high-speed arithmetic is performed by simultaneously executing the same arithmetic on a plurality of data. Processing is possible.

  In recent years, the degree of integration of LSIs has been increasing due to miniaturization of the manufacturing process, and it has become possible to increase the number of PEs even in SIMD type processors. However, in a processor adopting a parallel processor configuration such as SIMD type, if even one of a plurality of installed processors fails, the entire processor will fail. A technique has been adopted in which a PE is provided and replaced with a faulty PE (see, for example, Patent Documents 1 to 3).

  As shown in Patent Documents 1 to 3 and the like, conventionally, a redundant PE for replacing a defective processor is provided, and when there is a faulty PE, a PE that has a faulty signal for specifying the PE Instead, the parallel processor is rescued by assigning it to a redundant PE.

In addition, each PE has a multiplexer of the output signal from the adjacent PE and the signal output by itself, and in the case of a faulty PE, the output signal from the adjacent PE is bypassed and output to output the parallel processor. There has also been proposed a relief (see, for example, Patent Documents 4 to 6).
Japanese Patent Laid-Open No. 9-22400 Japanese Patent Application Laid-Open No. 9-288652 Japanese Patent No. 3005243 JP 2000-148998 A JP 2002-169787 A JP-T-2001-527218

  In each of the above patent documents, there is no description of how to inspect PE. By the way, considering the mechanism of the PE self-test in the processor of these configurations, first, test data is input to an arbitrary PE in the process of inspection, and the data stored in the register of the arbitrary PE is used as a test device. There are two methods: a method of checking the test data, and inputting the test data and the expected value of the test result accompanying the test data to all PEs, and comparing the test result and the expected value with the ALU included in each PE. . However, in the latter method, since the correct inspection cannot be performed unless the ALU included in each PE is normal, the probability that a failed PE cannot be detected is higher than that in the former method.

  Further, the processors disclosed in the above-mentioned Patent Documents 1 to 3 and the like are premised on having a control line for selecting each PE, so this control line is also used in the self-test. It is conceivable to use each PE to select and test each PE. However, when the number of PEs provided in the processor increases, there arises a problem that the number of control lines for switching to redundant PEs becomes very large.

  On the other hand, in the processors disclosed in Patent Documents 4 to 6, etc., each PE has a shift register as a storage device that can access the external storage device or the external control device. However, although it is possible to write test data and read test results for each PE using this register, there is a problem that the circuit scale becomes large because the shift register is used.

  The present invention has been made in view of the above, and is based on a method for performing a self-test of each PE by adding a small number of circuits in a SIMD type processor equipped with a method for relieving a faulty PE, and a result of the self-test. The purpose of this is to stop the operation of the faulty PE and to reconfigure the parallel processor so that the entire processor can operate normally even if there is a faulty PE.

  According to the first aspect of the present invention, in the SIMD type processor having a configuration in which each PE has a flag register that can determine whether each PE is activated or stopped, each PE is selected using this flag register. Provides a mechanism that enables testing of each PE and avoiding the faulty PE by adding a small number of circuits by using a method of stopping the operation of the faulty PE based on the test results. To do. That is, in the SIMD type processor according to the first aspect of the present invention, each PE includes a flag register, and the processor includes a function unit that performs a self test, and the operation of each PE is activated or stopped according to the value of the flag register. The function unit that performs the self-test sets the value of the flag register so that only a predetermined number of PEs are in an operating state, performs a test only on the PEs that are in an operating state, and It is determined whether it is normal or faulty, and when the test for a predetermined number of PEs is completed, the value of the flag register is shifted by a predetermined number to bring the next predetermined number of PEs into operation and the predetermined number of PEs are set. It is configured to perform tests for all PEs by repeating the testing process, and when the tests for all PEs are completed, based on the results. There determines the value of the flag register of each PE, characterized in that it stops the operation of the PE that has failed.

  In the invention according to claim 2, in addition to claim 1, in the SIMD type processor having an ID register for storing a number for identifying itself among a plurality of PEs, the self-test of each PE By presenting a method that can set the value of the ID register while avoiding the faulty PE at the time of execution, it is not necessary to have an initial value in the ID register of each PE at the time of executing the self test. It provides a mechanism that can suppress the increase in circuit accompanying the test as much as possible. That is, the SIMD type processor according to the second aspect of the present invention has a function in which each PE has a flag register and an ID register for storing a number for identifying itself among a plurality of PEs, and performs a self test on the processor. A function unit for performing a self-test so that only a predetermined number of PEs are in an operating state. Set and test only the PEs that are in the operating state to determine whether the PE is normal or faulty. If the PE is normal, set a unique number in the ID register. When the test for the PE is completed, the value of the flag register is shifted by a predetermined number, the next predetermined number of PEs are put into operation, and the predetermined number of PEs are tested. It is configured to perform the process for all the PEs and the process of setting the ID register values by repeating the process, and when the tests for all the PEs are completed, the flag register of each PE is based on the result. The value is determined and the operation of the faulty PE is stopped.

  In the invention according to claim 1, since it is possible to determine the operation / stop of each PE using a flag register including, for example, a 1-bit shift register included in each PE, In addition, the operation of the failed PE can be stopped. In addition, when testing each PE, if only the flag register is normal, the test can be performed correctly. Therefore, it is possible to detect a faulty PE and stop the operation of the faulty PE with a high probability.

  According to the second aspect of the present invention, when the self-test of each PE is executed, the value of the ID register can be set while avoiding the faulty PE, and it is not necessary to have an initial value in the ID register. It is possible to suppress the increase of the circuit accompanying the self test as much as possible. In addition, by using this ID register, a predetermined PE is selected from a plurality of PEs to perform processing, or each PE is connected to a general-purpose register having a communication path with an external interface included in each PE. Data can be written / read every time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the overall configuration of a SIMD type processor to which the present invention is applied will be described with reference to FIG.

  The SIMD type processor of the present invention comprises a processor element block including a global processor (GP) 1, a register file 2, and an arithmetic array 3. The global processor 1 is a so-called SISD (Single Instruction-stream, Single Data-stream) type processor, which includes a program RAM and a data RAM, decodes the program, and generates various control signals.

  This control signal is supplied to the register file 2 and the arithmetic array 3 in addition to the control of various built-in blocks. When a GP (global processor) instruction is executed, various arithmetic processes and program control processes are performed using a built-in general-purpose register, an ALU (arithmetic logic unit), and the like.

  The register file 2 holds data processed by a PE (processor element) instruction. The PE instruction is a SIMD type instruction, and simultaneously performs the same processing on a plurality of data held in the register file 2. Control of reading / writing data from the register file 2 is performed by control from the GP 1. The read data is sent to the arithmetic array 3 and written to the register file 2 after arithmetic processing in the arithmetic array 3. The register file 2 can be accessed from the outside of the processor, and a specific register is read / written from the outside separately from the control of the GP1.

  The arithmetic array 3 performs PE instruction arithmetic processing. All processing control is performed from GP1.

  FIG. 2 is a block diagram showing a detailed configuration of a SIMD type processor to which the present invention is applied. GP1 includes a program RAM for storing the program of this processor and a data RAM for storing operation data. Furthermore, a program counter (PC) that holds the address of the program, G0 to G3 registers that are general-purpose registers for storing data for arithmetic processing, and a stack pointer that holds the address of the save destination data RAM at the time of register saving and restoration SP), a link register (LS) that holds the address of the caller at the time of the subroutine call, LI and LN registers that hold the branch source addresses at the time of IRQ and NMI, and a processor status register (P) that holds the state of the processor ) Is built-in. The GP instruction is executed using these registers and an instruction decoder, ALU, memory control circuit, interrupt control circuit, external I / O control circuit, and GP operation control circuit (not shown). When executing the PE instruction, the register decoder 2, the register file control circuit (not shown), and the PE operation control circuit are used to control the register file 2 and the operation array 3.

  In this embodiment, the register file 2 includes 32 8-bit registers 20 in one PE unit, and a set of 256 PEs has an array configuration. Register 20 is R0, R1, R2,. . . It is called R31. Each register 20 has one read port and one write port for the arithmetic array 3, and is accessed from the arithmetic array 3 via an 8-bit read / write bus 21.

  Of the 32 registers 20, 24 can be accessed from outside the processor, and any register can be read and written by inputting a clock, an address, and read / write control from the outside. Access from the outside of the register 20 is such that one register of each PE can be accessed by one external port, and the PE number (0 to 255) is designated by an address input from the outside. Therefore, a total of 24 external ports for register access are installed. Access from the outside is a set of even-numbered PEs and odd-numbered PEs, which are 16-bit data, and two registers are simultaneously accessed by one access.

  The arithmetic array 3 includes a 16-bit ALU 31, a 16-bit A register 32, and an F register 33.

  In the operation by the PE instruction, basically, data read from the register file 2 is input to one side of the ALU 31 and the contents of the A register 32 are input to the other side, and the result is stored in the A register 32. Therefore, the operation between the A register 32 and the R0 to R31 registers is performed. A PE selection unit 40 consisting of a 7 to 1 multiplexer is placed in the connection between the register file 2 and the operation unit 3, and the data is 1, 2, 3 away from the left in the PE direction and 1, 2, 3 away from the right. Data and center data are selected for calculation. The 8-bit data of the register file 2 is shifted to the left by an arbitrary bit by the shift & extension circuit 41 and input to the ALU 31. Furthermore, the execution / invalidation control of each PE is controlled by an 8-bit condition register (T) not shown, and only a specific PE can be selected as a calculation target.

  FIG. 3 is a block diagram showing the configuration of the first embodiment of the present invention. As described above, 24 of the register file 2 can be accessed from outside the processor, and the clock, address, and read / write are given from the outside via the external interface 4, and the clock, address, and read / write are stored in the register. An arbitrary register given to the controller 22 and accessed from the outside by the register controller 22 can be read and written. Access from the outside is a set of even-numbered PEs and odd-numbered PEs, which are 16-bit data, and two registers are simultaneously accessed by one access.

  The processor according to the present embodiment has a built-in ROM in which a program for self-testing the PE is written. The test program is transferred to a program RAM included in the GP 1 and the GP performs a self-test of each PE. The GP 1 has the immediate data buses 11 and 12 shown in FIG. 3 as a write path to each PE, and the test data bus 13 constituted by, for example, an open drain bus as a read path. The test data can be written to each register 20 of each PE, and the test result can be read from the A register 32.

  In this embodiment, each PE has a flag register 34 consisting of a 1-bit shift register, and the PE flag register 34 closest to GP1 among the PEs arranged in an array is capable of transferring data from GP1. It has a possible communication path. The flag register 34 has a shift register configuration, and has a communication path through which data can be written to the flag register 34 of the PE that is further away from the GP 1 by the adjacent PE.

  Further, the value of the flag register 34 is inputted to the A register 32, F register 33, T register (not shown), and R0 to R31 registers 20 of its own PE as shown in FIG. Data from the ALU 31 or the data bus 13 is selected by the multiplexer 35 and supplied to the A register 32. An inverted output from the flag register 34 and an A register write enable signal are supplied to the AND circuit 36, and an output of the circuit 36 is supplied as a latch signal of the A register 32. The output of the A register 32 is given to the three gate buffers 37 and 38, and is output from the three gate buffer 37 to the data bus 13. The output of the flag register 34 is given as a control signal for the three gate buffers 37 and 38.

  With this configuration, when the value of the flag register 34 is 0, the output signal from each register 20 to the data bus 13 is negated on the read side, and the write enable signal of each register 20 is negated on the write side. Since it can, the operation of the PE can be stopped. When the value of the flag register 34 is 1, each register 20 can perform both reading and writing of data, so that the PE operates normally. That is, the flag register 34 can be used as a selection flag or enable / disable flag for each PE.

  In the above configuration, when power is turned on or the system is initialized, 1 is stored in the value of the flag register (shift register) 34 in order from the PE with the closest distance to GP1, and the PE is selected one by one for testing. The flow of processing until the operation of the faulty PE is stopped based on the result is shown below.

Step (Step) 1: The test program is transferred from the ROM to the program RAM built in the GP.
Step (Step) 2: 0 is stored in the flag registers 34 of all PEs, and all PEs are set in a non-selected state.
Step (Step) 3-1: 1 is stored in the flag register 34 of the PE (PE0) having the shortest distance to GP1, and only that PE0 is selected.
Step (Step) 3-2: A test is performed on the selected PE0 to determine whether the PE0 is normal or faulty.
Step (Step) 3-3: The test result of PE0 is stored in the data RAM.
Step (Step) 4-1: The value of the flag register 34 is shifted by 1 PE, and the next PE (PE 1) is selected.
Step (Step) 4-2: The selected PE1 is tested to determine whether the PE1 is normal or faulty.
Step (Step) 4-3: The test result of PE1 is stored in the data RAM.
Step (Step) 4-4: The same processing as Step 4-1 to Step 4-3 is repeated until the test for all PEs is completed.
Step 5: Based on the test result stored in the data RAM, 0 is stored in the flag register 34 of the PE determined to be faulty, and 1 is stored in the flag register 34 of the PE determined to be normal. Store.

  Next, an example in which the parallel processor operates while avoiding the failure PE in the configuration illustrated in FIG. 3 will be described.

  Each PE is routed so that the multiplexer 40 can select 1, 2, 3 forward data, 1, 2, 3 backward data, and central data as computation targets in the PE direction. However, one spare wiring path is provided at the front and one at the rear so that data can be correctly referred to even if there is a faulty PE. That is, if there is no faulty PE, each PE has data up to 1 (abbreviated as L1), 2 (abbreviated as L2), 3 (abbreviated as L3), and 4 (abbreviated as L4) in the PE direction. The data up to 1 (abbreviated as U1), 2 (abbreviated as U2), 3 (abbreviated as U3), and 4 (abbreviated as U4) can be referred to.

  In addition to its own register, the multiplexer (PE selection unit) 40 for selecting a PE to be referred to includes a path for referring to data from the above-mentioned PE registers that are separated forward and backward by up to four. However, the value of the flag register 34 of the PE ahead by 1, 2, and 3 from the own PE and the value of the flag register 34 of the PE behind by 1, 2, 3 are input.

  Further, a control signal indicating whether the instruction currently being executed from GP1 is an instruction for referring to data of which register in front, rearward, or its own with respect to its own PE is input.

  The PE selection unit 40 is controlled so as to avoid the faulty PE and open the wiring path based on the front and rear flag registers 34 and the control signal. For example, in the case where the previous PE of its own PE is out of order, when a command referring to the previous PE is issued, the path from the previous PE is opened. When an instruction referring to the previous PE is issued, a path from the previous PE is opened.

  FIG. 5 illustrates how control is performed when a failure occurs in three PEs in front of or behind a certain PE.

  C_en, L1_en to L3_en, and U1_en to U3_en indicate which PE is currently executing an instruction for referring to data stored in PE, and in order C_en (own PE reference instruction) , L1_en (one forward PE reference instruction), L2_en (two forward PE reference instructions), L3_en (three forward PE reference instructions), U1_en (one backward PE reference instruction), U2_en (two backwards) PE reference instruction), U3_en (three backward PE reference instructions).

  C_enable, L1_enable to L4_enable, U1_enable to U4_enable indicate which wiring path is actually opened in each PE, and C_enable (a gate that references its own PE is opened), L1_enable (the previous PE) L2_enable (the gate referring to the previous PE is opened), L3_enable (the gate referring to the previous PE is opened), L4_enable (the gate referring to the previous PE is opened) U1_enable (a gate that references the next PE is opened), U2_enable (a gate that references the next PE is opened), U3_enable (a gate that references the next PE is opened), U4_enable ( Gate referring to PE after 4 We are open).

  With this configuration, the entire processor can be relieved if there are no two or more failures in the four consecutive PEs.

  In the above-described embodiment, the method of selecting and testing one PE at a time has been described. However, a plurality of PEs are tested simultaneously, for example, two PEs are tested simultaneously to verify the presence or absence of a PE failure. It can also be configured as follows. By configuring in this way, the time required for the test can be shortened. However, in this case, if there is at least one failed PE among the simultaneously tested PEs, all the simultaneously tested PEs must be processed as failures.

  FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention. In the processor of the second embodiment, in addition to the configuration of the processor disclosed in FIG. 3, each PE has an ID register 39 for storing a number for identifying itself from a plurality of PEs. Adopt the configuration. The ID register 39 has a path for outputting its own value to the data bus of each PE and an input path for changing its own value from GP1. For example, when processing is performed by selecting a specific PE, the ALU 31 of each PE compares the value of the ID register 39 of each PE with the data given from GP1, and these two values are equal. At this time, the comparison result is reflected in the T register (not shown) of each PE. Further, the value of the flag register 34 is input to the ID register 39 in the same manner as in FIG. 4, and writing to the ID register 39 can be performed only when the value of the flag register 34 is 1. That is, the value of the ID register 39 can be changed only in the PE selected during the self test.

  In the above configuration, when power is turned on or the system is initialized, 1 is stored in the value of the flag register (shift register) 34 in order from the PE with the closest distance to GP1, and the PE is selected one by one for testing. Based on the result, the operation of the faulty PE is stopped, the faulty PE is avoided, and the ID number for specifying the PE only in the normal PE ID register 39 is set in ascending order, for example. The flow of processing is shown below.

Step (Step) 1: The test program is transferred from the ROM to the program RAM built in the GP.
Step (Step) 2: 0 is stored in the flag registers 34 of all PEs, and all PEs are set in a non-selected state.
Step (Step) 3-1: 1 is stored in the flag register 34 of the PE (PE0) closest to GP1, and only PE0 is selected.
Step (Step) 3-2: A test is performed on the selected PE0 to determine whether the PE0 is normal or faulty.
Step (Step) 3-3: If the test result PE0 is normal, 0 is stored in the ID register 39.
Step (Step) 3-4: The test result of PE0 is transferred to the data RAM.
Step (Step) 4-1: The value of the flag register 34 is shifted by 1 PE, and the next PE (PE 1) is selected.
Step (Step) 4-2: The selected PE1 is tested to determine whether the PE1 is normal or faulty.
Step (Step) 4-3: If PE1 fails, no value is set in the ID register 39 of PE1. If PE1 is normal, if PE0 is also normal, 1 is stored in the ID register of PE1. If PE0 has failed, 0 is stored in the ID register of PE1.
Step (Step) 4-4: The same processing as Step 4-1 to Step 4-3 is repeated until the test for all PEs is completed.
Step 5: Based on the test result stored in the data RAM, 0 is stored in the flag register 34 of the PE determined to be faulty, and 1 is stored in the flag register 34 of the PE determined to be normal. Store.

  As described above, when a unique value is set in the ID register 39 of each PE, a predetermined PE can be selected using the value of the ID register 39. The general-purpose register 20 having a communication path with the external interface 4 included in each PE has a configuration in which data can be read / written with the external interface 4 for each PE. In each PE, the value of the ID register 39 can be input to the register controller 22 which is a control device for the general-purpose registers 20. And a value for specifying a predetermined PE input from the external interface 4, and if they match, a write enable signal or a read enable signal is input to each register 20, and the data This is realized by enabling writing or reading.

It is a block diagram which shows the whole structure of the SIMD type processor to which this invention is applied. It is a block diagram which shows the detailed structure of the SIMD type processor to which this invention is applied. It is a block diagram which shows the structure of 1st Embodiment of this invention. It is a block diagram which shows the structure of the flag register and A register part in 1st Embodiment of this invention. In the configuration of the first embodiment of the present invention, it is a block diagram showing how control is performed when a failure occurs in three PEs in front or behind a certain PE. FIG. It is a block diagram which shows the structure of 2nd Embodiment of this invention.

Explanation of symbols

1 Global processor (GP)
2 Register file 3 Arithmetic array 4 External interface 31 ALU
32 A register 33 F register 34 Flag register 39 ID register

Claims (2)

A SIMD type processor having a plurality of processor elements for processing a plurality of data, each processor element including a flag register and a function unit for performing a self-test on the processor, and each processor element depending on a value of the flag register The function unit that performs the self-test sets the value of the flag register so that only a predetermined number of processor elements are in an operating state, and the processor element that is in an operating state Only when the test is performed for a predetermined number of processor elements, the value of the flag register is shifted by a predetermined number and the next predetermined number of processors are determined. Put the element in operation and It is configured to perform a test for all the processor elements by repeating the process of testing a predetermined number of processor elements. When the test for all the processor elements is completed, the flag register of each processor element is based on the result. The SIMD type processor characterized by determining the value of the processor and stopping the operation of the failed processor element. A SIMD type processor having a plurality of processor elements for processing a plurality of data, each processor element including a flag register and an ID register for storing a number for identifying itself among the plurality of processor elements, The processor includes a function unit that performs a self-test, and can determine whether the operation of each processor element is activated or stopped according to the value of the flag register. The function unit that performs the self-test sets the value of the flag register to a predetermined number of processors. Set so that only the element is in the operating state, and test only the processor element that is in the operating state to determine whether the processor element is normal or faulty. If the processor element is normal, the ID A unique number for the register When the test is completed for a predetermined number of processor elements, the value of the flag register is shifted by a predetermined number, the next predetermined number of processor elements are put into operation, and the predetermined number of processor elements are tested. It is configured to repeat the test for all the processor elements and the process of setting the ID register values. When the test for all the processor elements is completed, the flag register of each processor element is based on the result. A SIMD type processor characterized by determining a value and stopping the operation of a faulty processor element.

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