JPS62210547A - Diagnosing method for error detection circuit - Google Patents

Abstract

PURPOSE:To generate an error data intentionally, to facilitate the diagnosis of an error detection circuit, and to realize exactness, by writing data independently on a data memory and a redundancy bit memory. CONSTITUTION:Generally, other than an address 101, virtual addresses 103 and 104 having the same address ranges as that of the address 101, and another address areas, are provided. When the address 103 is inputted to a memory selector 1, a data RAM cell 107 is outputted, and when the address 104 is inputted to the selector 1, a parity RAM cell 106 is outputted. In this way, a switching between a normal mode and a diagnostic mode can be performed by using those addresses in a diagnostic mode time, and a RAM can be accessed individually by providing plural virtual addresses.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention intentionally generates erroneous data by writing data into the data memory and the redundant bit memory independently, thereby facilitating diagnosis of the error detection circuit. The present invention also relates to a method for accurately diagnosing an error detection circuit.

[Conventional technology]

As described in Japanese Unexamined Patent Publication No. 55-83946, the conventional device includes a redundant bit register for one test and a selection circuit for switching between this and the normal redundant bit. In this case, a dedicated circuit for diagnosing the detection circuit is required, which increases the amount of hardware. Furthermore, there was no discussion of how to handle failures in the dedicated circuit itself.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has the problem of how to deal with an increase in the number of hardware and failures of the hardware itself.

SUMMARY OF THE INVENTION An object of the present invention is to provide a diagnostic method that generates a memory error and diagnoses an error detection circuit without increasing hardware.

[Means for solving problems]

The above purpose is to separate the memory selector output for selecting memory into a data memory output line and a redundant bit memory select line, and each select@ has a second address having a different address area in the same address space as the normal address,
Allocation of the third address is accomplished by independently operating the data memory and redundant bit memory.

[Effect]

Although two types of addresses have been used above, there is a method of simplifying the virtual address to one type as another implementation sequence. One way to do this is to use the data RAM when reading from a virtual address.
There is a method of generating a parity error by selecting only one of the parity RAMs and fixing the output of the unselected RAM.

According to this implementation column, it can be realized with only a memory selector and a select line for selecting memories individually, and when the selector is configured with a programmable element,
By adding virtual address logic to this element, it is possible to diagnose the parity error detection circuit without increasing the hardware and by essentially increasing only the select lines.

Furthermore, the present invention can also be applied to diagnosis of a memory error detection and correction circuit using redundant bits such as ECC.

〔Example〕

Next, an embodiment of a diagnostic method for an error detection and correction circuit according to the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a programmable controller that is one implementation of the system.

The main components are a data RAM 2 for storing data, a parity RAM 3 for parity checking, a memory selector 1 that can select memory individually, a parity generator 4 that generates parity from data, and a data RAM 2.
The output 105 of the parity RAM 3, the output 109 of the parity RAM 3, and a parity checker 5 for determining parity errors can be applied to the data 102, the data RAM 2, and the parity RAM 3 to generate a parity error.

The configuration and operation of each part will be explained below.

There are two modes of operation: normal mode and diagnostic mode. First, the normal mode will be explained.

During a write operation, an address is input from the processing device 6 to the memory selector 1 through the address bus 101. At that time,
The memory selector 1 simultaneously outputs the data RAM output 107 and the parity RAM cell 106, leaves each ordinary person M in an operating state, and writes data 102 to the data ordinary person M2.
For parity AM3, data 102t is input to parity generator 4, and this parity generator 4
The parity data 108 generated by The parity generator 4 determines the number of 1's in each bit of the data 102, and if it is a parsimonious number, @O'' is output, and if it is an even number, @1'' is output from the parity generator 108.
Output as .

When reading, RAM 710 is selected from memory selector IK.
The data RAM output 105 and the parity-ordinary M output 109 are simultaneously output to the parity checker 5. The parity generator 4 determines whether the sum of "l" of each bit of these two outputs is a parity or an even number, and outputs a parity error 110 if it is a parity number and a parity error 110 if it is an even number.

In this way, in the normal mode, parity bit generation and read checking are performed on hardware, and memory error detection is automatically performed.

(2) Next, a diagnosis mode for parity error occurrence according to the present invention will be explained.

First, FIG. 2 shows the diagnostic mode and allocation of individual addresses using selectors. Normally, in addition to the address 101, a second address 103 and a third address 104 (hereinafter referred to as virtual addresses) having the same address range and a different address area are provided, and the virtual address 103 When input to memory selector 1, M cell 107 is output to data selector 1, and when virtual address 104 is input to memory selector 1, parity selector M cell 1 is output.
06 is output. By using this virtual address during diagnostic mode, it is possible to switch between normal mode and diagnostic mode using only the address image, and by providing multiple virtual addresses, l(, AM
can be accessed individually.

The case where two-ring virtual addresses are provided will be described below with reference to FIG.

The operation when virtual address 103 is selected will be explained as case 1, and the operation when virtual address 104 is selected will be explained as case 2.

(Case 1) Write data 102 to data RAM2. At this time, the parity RAM cell output 106 is not output, and the parity RAM 3 is not selected.

(Case 2) As the data 102, the parity generator 4 is given data that predicts the parity generation result in advance,
Write the parity generator output 10B to the parity RAM3. At this time, the data RAM cell output 107 is not output (and the data cell AM2 is not selected).

If Case 1 and Case 2 are used together, arbitrary data can be set in the data ordinary person M2 and the parity RAM 3. Next, by performing successive output in the 1 normal mode, it can be diagnosed whether the error detection circuit performs a predetermined operation.

〔Effect of the invention〕

According to the present invention, the objective can be achieved by simply adding a select line to the conventional hardware, and error diagnosis can be easily and accurately performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory device according to one embodiment of the present invention, and FIG. 2 is an operational diagram of a memory selector.

Claims (1)

[Claims] 1. In a memory device in which redundant bits are provided in data bits and errors in memory contents are detected using the redundant bits during reading, the data memory select line and the redundant bit memory select line are separated, and in normal mode, A method for diagnosing an error detection circuit, characterized by selecting both at the same time, selecting them independently in a diagnostic mode, and intentionally generating erroneous data and redundant bits by writing data. 2. In claim 1, switching to the diagnostic mode is provided by having, in addition to the real address, a second address having an address area different from the real address as a switching means between the normal mode and the diagnostic mode. A method for diagnosing an error detection circuit characterized by: