JPH06110853A - Parallel computer system and processor - Google Patents

Abstract

PURPOSE:To improve the working rate and to attain the automatic scheduling of a pre-reading function by storing plural programs (estimated processing) having the (later) contribution of their execution results is not knows separately from a main program. CONSTITUTION:A local storage device 140, an instruction wait memory IWM 175 which shown the assurance of plural information (programs, etc.) stored in the storage device 140, and a connection wait memory CWM 170 which shown the inter-processor connection intensity are used in addition to a computing element group 130 as the component elements of a processor 120 that constructs a processor array 110. Then one of plural estimated processing programs is specified in addition to a main program, and each element processor computes the specified estimated processing program in place of the main program in a NOP state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a parallel computer system such as a massively parallel computer including a plurality of processors. More specifically, the present invention relates to a method of using a massively parallel computer and a configuration of an element processor for dealing with complicated information processing.

The present invention is also applicable to neurocomputers. It can also be used as a single microprocessor.

[0003]

BACKGROUND OF THE INVENTION Traditional computer systems consist of a single processor that inputs a single instruction stream from program memory and executes one instruction at a time. This is known as a sequential uniprocessor architecture (von Neumann architecture).

As one method of increasing the speed in the sequential single processor architecture, for example, 68000 microcomputer (Maruzen, published in March 1983, P.
19-20), an instruction prefetch (instruction prefetch) function is described. FIG. 18 shows a simple register configuration for realizing this function.

In FIG. 18, the instruction code currently being executed is IR (Instruction Register) 8
Signal line 8 after it is set to 20 and the instruction is decoded
21 via IRD (Instruction Dec)
eder) 810. When the instruction is moved to the IRD 810, the next instruction to be executed is IRC (Inst-ru).
From the action cache 830 to the IR 820 via the signal line 831 and waits for the start of decoding. In principle, the first word of the next instruction to be executed is set in each of IR820 and IRC830. The extension part from the second word of the instruction is EDB (Entry Data).
Bus) 840 is set. In this way, by having a special register for prefetch, it is possible to prefetch (read from memory) all or part of the next instruction to be executed, and to save the instruction fetch time by execution. .

However, the calculation speed and processing power desired by the user cannot be obtained only by improving the performance of the single processor in the traditional computer system. As a countermeasure against this, a parallel computer (massively parallel computer) system, which realizes high speed by executing many element processors in parallel, has been attracting attention. As an example,
FIG. 17 shows an outline of the system configuration of the connection machine of Thinking Machines Co., Ltd., which is described in JP-A-60-84661.

In FIG. 17, 110 is a processor array, and 120 is a processor that constitutes the processor array. Reference numeral 200 is a microcontroller that controls the processor array, 300 is an external storage device that stores data necessary for calculation, and 400 is a host computer that controls the microcontroller 200.

The host computer 400 is, for example, a DE
A commercially available general-purpose computer such as a VAX computer manufactured by C (Digital Equipment Corp.).
Instruct the start and end of the operation. Further, data is transmitted / received to / from the external storage device 300 or the processor array 110 by the signal line 420 via the microcontroller 200.

The microcontroller 200 controls the processor array 110 by a parallel bus 210.
For example, one line in bus 210 could be RES to array 110.
The ET signal is given, three lines output timing signals, and the remaining lines are used for command transmission. The target chip and processor are connected to the signal line 220. Address information for reading / writing to the external storage device is performed by the address signal 240. Transmission / reception of data between the micro controller 200 and the processor array 110 and notification of status information from the processor array 110 to the micro controller 200 are performed by a signal line 230.

The buses 210 and 230 are connected in parallel to each processor element 120. As a result, the signals from the microcontroller 200 are simultaneously provided to each element processor 120 in the array 110. That is, each element processor 120 executes the same instruction at once. If you do not need all the processors, the extra processor 1
25 becomes a NOP (No OPeration) state.

An increase in the number of processors in the NOP state leads to a reduction in cost performance. Therefore, a task (load) allocating technique for reducing the number of processors in the NOP state as much as possible, for example, a technique for allocating a load when NOP continues for a certain period or longer, is described in Japanese Patent Laid-Open No. 3-191488.

[0012]

Generally, in order to cope with a larger scale problem or more complicated information processing, it is necessary to increase the number of element processors constituting a massively parallel computer system.

Even when the parallelism is increased to achieve high speed,
It is necessary to increase the number of processors. However, some application programs do not necessarily require all processors in the system. Further, when executing the subprograms (tasks) constituting the main program, only a part of the element processors required by the main program are used.
That is, the above-mentioned conventional technique has a problem that the operating rate decreases (the ratio of the processors in the NOP state increases) as the number of processors constituting the system increases. This tendency is due to SIMD (Single Instruction stream Multi Data) in which all processors execute the same instruction at a time.
This is especially noticeable on a parallel computer with a stream) architecture.

Further, in order to cope with more complicated information processing, for example, a look-ahead function of a human being (a function of predicting a previous movement or a prospective process in advance for the future (may be useless, but maybe later Function that executes a process that may be useful) is effective, but the above-mentioned conventional technique (for example, the instruction prefetch function) only reads the next instruction to be executed from the memory in the already determined processing algorithm (processing Is not executed), and it cannot fully support the look-ahead function that humans have. In order to realize the read-ahead function in the above-mentioned conventional technique, it is necessary for a person to write a main program in consideration of when and what kind of read-ahead function is executed. That is, it is necessary to consider an algorithm including scheduling of the prefetching function, which imposes a heavy burden. In addition, it is necessary to reexamine the above scheduling for each application program, which causes a problem that the number of man-hours for creating a program is significantly increased and the probability of bug occurrence is also increased.

In order to solve the above problems of the prior art,
The present invention aims at the following (1) to (4).

(1) Improving the operation rate of a massively parallel computer (especially SIMD type architecture) (2) Automating the scheduling of the above-mentioned read-ahead function (when and what kind of read-ahead function is executed) (self-formation) (3) Self-acquisition of new expected process from minimum required expected process (4) In addition to (1) to (3) above, provide added value such as shortening TAT

[0017]

In order to achieve the above object, the following solution means are provided.

(1) A means for storing a plurality of programs (probability processing) whose execution result is not useful (later) is stored separately from the main program.

(2) 1 out of the plurality of expected processing targets
It has a means to specify one program. For example, with respect to the above-mentioned prospect processing, each external condition (execution condition) has information (weight value) indicating the likelihood of each prospect processing, and one program is specified according to the weight value information. Alternatively,
Use a random number table to identify one program.

(3) It has a calculating means for executing the above-mentioned specified prospect processing program.

(4) It has means for evaluating the execution result of the above-mentioned prospective processing according to a specific standard.

(5) NOP (No OPer) for each element processor or for each group composed of a plurality of element processors
ation) has a means for judging the state.

(6) According to the NOP state determination result, the main program is replaced with a means for executing the specified prospect processing program.

(7) A means is provided for updating the weight value information online (in operation) according to the evaluation result of the prospective processing.

(8) A means for repeating the above-mentioned (same or different) forecast processing a plurality of times is provided.

(9) A means for storing the history of the above-described repeated prospective processing is provided.

(10) A means for storing a combination of a plurality of prospective processes as a new prospective process is provided.

[0028]

By the above means for solving the problem, the following operation is obtained.

(1) According to the present invention, apart from the main program, a plurality of prospect processing programs are stored in the system, one of the prospect processing programs is specified, and then each element processor In, in the NOP state, it is possible to calculate the specified prospect processing program instead of the main program.

Therefore, the utilization rate is improved by utilizing the processor in the NOP state for executing the expected process. Execution of an appropriate expected process leads to shortening of TAT in, for example, a search process. Further, even if the invalid expected process is executed, the performance is not deteriorated because the processor which is originally in the NOP state is used.

(2) According to the present invention, the execution result of the prospective process is evaluated according to a specific criterion, and according to the evaluation result, information indicating the certainty of each prospective process for each external condition (execution condition) ( (Weight value) is updated online.

Therefore, the more it is used (through experience), the more self-growth can be made so that an appropriate expected process is selected according to the external condition (execution condition).

(3) According to the present invention, when an effective solution (convergent solution) is obtained as a result of repeating the predictive processing a plurality of times, a series of predictive processing executed until the effective solution (convergent solution) is obtained. Can be used as a new prospective process.

Therefore, a combination of the prospective processes (genetic elements) given by humans in advance is used to create a new prospective process (a certain initial state, a series of prospective processes that gives an effective solution (convergent solution) to certain input data). The flow (combination) can be self-acquired.

[0035]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows an SI for showing an embodiment of the present invention.
MD (Single Instruction stream Multi Data stream)
FIG. 1 is a system configuration diagram of a massively parallel computer having a type architecture.

In FIG. 1, 110 is a processor array, and 120 is a processor that constitutes the processor array. Reference numeral 200 is a microcontroller that controls the processor array, 300 is an external storage device that stores data necessary for calculation, and 400 is a host computer that controls the microcontroller 200.

The host computer 400 gives an instruction to start / end the operation of the microcontroller 200 by, for example, a control signal 410. In addition, the microcontroller 20
The signal line 420 transmits / receives data to / from the external storage device 300 or the processor array 110 via 0.

The micro controller 200 controls the processor array 110 (for example, specifies the arithmetic function) by the micro instruction 210. The target chip (processor array or a part of the processor array) and the processor perform the chip select signal CS and the processor select signal PS220 (in FIG. 1, a part of the processor select signal PS (for example, several high-order bits) is a chip select signal. Since it is assumed to be used as CS, CS and NS are represented by the same signal 220.
It can also be realized as a separate signal. ). Address information for reading / writing to the external storage device is performed by the address signal 240. Data transmission / reception between the microcontroller 200 and the processor array 110 is performed by Din / D
It is performed by the out signal 230.

In FIG. 1, the conventional SIMD shown in FIG.
The difference from the massively parallel computer is that, in addition to the arithmetic unit group 130, the local storage device 1 is an element that constitutes the processor 120.
40, an instruction weight memory (IWM) 175 indicating the certainty factor of a plurality of pieces of information (for example, programs) stored in the local storage device 140, a connection weight memory (CW) indicating the coupling strength between processors.
M) 170. The Cond 250 is an external condition (or execution condition) and serves as a pointer of the IWM 175.

The features of the present invention will be described below with reference to FIGS.

FIG. 2 shows the element processor 12 shown in FIG.
It is an example of the block block diagram of 0.

In FIG. 2, reference numerals 130, 140 and 175 denote the arithmetic unit group, local storage device and IWM shown in FIG. 1, respectively.
Is. In FIG. 2, the local storage device 140 stores a plurality of programs (probable processes) whose execution results are not always (later) useful. IWM175 has
Information (weight value) indicating the probability of each prospective process is stored for each external condition (execution condition). 166 is NOP
(No OPeration) decision logic, 165 (logic based on information from NOP decision logic, local storage device and IWM) to generate control signals for the arithmetic unit group 130, 190 decides the validity of the executed instruction It is logic.

The characteristic operation of the processor shown in FIG. 2 will be described below based on the flow chart shown in FIG.

The NOP judgment logic is the CS / PS 220 input from the microcontroller 200, the micro instruction 2
10 and flag information 16 input from the arithmetic unit group 130
From 2, the NOP determination is performed. In addition, the determination result 163 is I
NST. Output to decision logic 165.

INST. The decision logic 165 determines the decision result 1
If 63 is not a NOP instruction, the microcontroller 20
The microinstruction 210 input from 0 is output as the instruction 161 for controlling the arithmetic unit group. (That is, the computing unit group 13
At 0, the main process is executed. ) When the determination result 163 is a NOP instruction, one is selected from among a plurality of (four in FIG. 2, 141-1 to 141-4) expected processes stored in the local storage device 140 to control the computing unit group. Is output as a command 161. In addition, the information of the selected instruction is output to the selection success / failure determination logic 190. In FIG. 2, weight value information (1 that indicates the probability of each prospective process read from the IWM
76 to 179) to determine which prospective process is selected. The maximum weight value is obtained, for example, by inputting each weight value information to the computing unit group 130 via the signal line 169. IW
The initial value of M is given (randomly) by a random number table, for example. Alternatively, it has an intention and is decided by a person. The external condition (execution condition) 250 input from the microcontroller 200 is used as the IWM pointer.

The computing unit group 130 includes INST. Decision logic 1
The calculation is executed in accordance with the instruction 161 input from 65, and the result (and the selected expected processing information) is stored in a storage device such as a register. The data required for the calculation is previously sent to the microcontroller 200 via the Din 230, for example.
Alternatively, it is input from the external memory 300 and stored in the storage device in the arithmetic unit group 130.

In the selection success / failure decision logic 190, for example,
The validity of the operation result 131 is determined from the instruction information 230 that should have been originally executed and the selected instruction 164. When it is valid, the calculation result is transmitted to another processor or the like via the signal line 192 and used in the main process. Further, the success / failure determination result 191 of the selected instruction is output to the arithmetic unit group 130.

The computing unit group 130 updates the weight value information corresponding to the selected instruction according to the success / failure determination result 191. For example, if the selection is correct, the weight value is increased. If the selection is wrong, the weight value is decreased.
The updated weight value is stored in the IWM 175 via the signal line 132.

The details of the constituent elements of the element processor shown in FIG. 2 will be described below with reference to Table 1 and FIGS.

Table 1 is a truth table showing details of the NOP judgment logic.

[0052]

[Table 1]

The CS / PS signal is selected when the signal value is "1" and not selected when the signal value is "0". When the flag signal is "1", NOP instruction is given. The NOP determination result signal means that the instruction 210 from the microcontroller 200 is instructed to be selected when it is '0', and the prospective processing is instructed to be selected when it is '1'.

FIG. 4 shows a block configuration example of the arithmetic unit group 130. In FIG. 4, reference numeral 121 is an input buffer, and 122 is an output buffer, each having a function of temporarily storing data input from another element processor and data output to another element processor. 131 is an arithmetic logic operation unit with shifter function, 132 is a multiplier, 133 is a general-purpose register, 134 is a flag register, 136-1 to 136-1.
136-2 is a parameter register. Also, 170
Is a rewritable memory for storing weight value information indicating the coupling strength between processors. 136-1 ~ 13
It is also possible to assign 6-2 and 170 to a part of the general-purpose register 133. Reference numerals 137 to 139 are internal buses. 230-1, 169, and 191 are D shown in the drawing, respectively.
In / Dout, weight value information, and selection success / failure result. 230
-2, 131, 132 and 162 are D shown in FIG.
These are in / Dout, calculation results, updated weight value information, and flag information.

In FIG. 5, the INST. An example of decision logic 165 is shown. INST. The decision logic 165 outputs the microinstruction 210 input from the microcontroller 200 when the NOP determination result signal 163 is “0” as the instruction 161 for controlling the arithmetic unit group 130.

When the NOP judgment result signal 163 is "1", the expected processing program 141-
One is selected from 1 to 141-4 and output as an instruction 161 for controlling the arithmetic unit group 130. In addition, the information 164 of the selected instruction is output to the selection success / failure determination logic 190.
In FIG. 5, the instruction 161 for controlling the arithmetic unit group 130 is used as it is as the information 164 of the selected instruction. In FIG. 5, which prospect process is selected is determined from the weight value information 176 to 179 which is read from the IWM 175 and indicates the probability of each prospect process. The maximum weight value is the signal line 1
Each piece of weight value information is input to the arithmetic unit group 130 via 69 and obtained. For example, the difference between the two weight values is obtained by using the ALU in the arithmetic unit group shown in FIG. 4, and the magnitude is determined depending on whether the result is positive or negative. When the maximum value among the weight value information 176 to 179 is obtained, the result is registered in the maximum value register 168. In FIG. 5, "1" is set in the register corresponding to the maximum value.

FIG. 6 shows an example of the selection success / failure determination logic 190. In FIG. 6, reference numeral 195 is a comparator, which is the information 230 of the instruction that should have been originally executed and the selected instruction 1
64 are compared, and if they match, the value "1" is output to the signal line 191. If they do not match, '0' is output. The value of the signal line 191 is output to the computing unit group 130 as a success / failure result. Further, it is used as a signal for controlling whether to transmit the calculation result 131 to another element processor via the signal line 192. An ALU can be used instead of the comparator 195. The selection success / failure determination logic 190 (comparator 195) can also be realized using the arithmetic unit group 130.

FIG. 7 shows an example of the weight value (IWM) updating process. In FIG. 7, the multiplier 1 which is a part of the arithmetic unit group 130
32 shows an example of updating the weight value using 32 and the parameter registers 136-1 to 136-2. Register 136
The values a and b that satisfy 0 <a <1 and 1 <b are stored in -1 and 136-2, respectively. When the value of the success / failure result 191 input from the selection success / failure determination logic 190 is “0”, the value a stored in the parameter register 136-1 and the weight value Wi corresponding to the selected expected process are respectively set to the internal bus 138. And 137 to the multiplier 132, and the calculation result is stored in the IWM 175 via the bus 139. When the value of the success / failure result 191 is “1”, the value b and the weight value Wi stored in the register 136-2 are input to the multiplier 132 via the internal buses 138 and 137, respectively, and the calculation result is input to the bus 139. Via the IWM 175.

Next, a second embodiment will be described with reference to FIGS.

FIG. 8 is an example of a block diagram for executing processing almost independent of the main program.

In FIG. 8, 130 is a group of arithmetic units, 140
Is a local storage device for storing the expected processing, and 165 is I
nst. The decision logic 1133 is a rewritable storage device for temporarily storing the calculation result.

Inst. When the NOP determination result 163 is a NOP instruction, the decision logic 165 executes the expected process input from the local storage device 140 instead of the microinstruction 210 input from the microcontroller 200. Figure 2
And the difference from the processing shown in FIG. 3 is that the expected processing that is almost independent of the main program is assumed.
Weight value information (IWM) 1 indicating the likelihood of each prospective process
The point is that the expected process to be executed is randomly selected by using, for example, a random number table or a pseudo-random binary sequence counter without 75.

The result of the expected processing processed by the arithmetic unit group 130 is stored in the visionary register 1133 and retrieved at an appropriate timing. If valid information is found by search, it will be used in the main process. vi
When the sionary register 1133 is full, the old information is deleted (forgotten). Alternatively, the information having a low access frequency is deleted (forgotten). visionary register11
33 is effective for high-speed search if labeled with, for example, the selected prospective processing information as a search key.

FIG. 9 shows a model in which a new forecast process is autonomously acquired by repeating the forecast process a plurality of times. Hereinafter, the autonomous prospective process acquisition shown in FIG. 9 will be described based on the flowchart shown in FIG.

In FIG. 9, reference numeral 910 is a main process, which normally performs a routine process (a program whose algorithm is fixed) based on an input 911, and outputs a result 912.
Is output.

In the case of NOP, one is randomly selected from a plurality of prospect processes in the local storage device 140, and the selected prospect process 951 is executed while using the input data 911 as needed ( 930). The execution result and the selected expected processing information 931 are stored in the Visionary Memory 970.

If the execution result stored in the Visionary Memory 970 is not a steady solution or a valid solution, this solution is used as new input data 971 to randomly select and execute a new prospective process from the local storage device 140. Alternatively, the previously selected prospect processing is executed again. The above processing is repeated for a fixed period. When a steady solution or an effective solution happens to be obtained during repetition for a certain period, that solution is used in the main process. Further, the sequence 972 of the prospect processing until the steady solution (or the valid solution) is obtained is registered in the local storage device 140 as a new prospect processing.

FIG. 11 shows an example of autonomous prospective process acquisition. In FIG. 11, a character is given as the initial value of the prospective processing,
It shows that the knowledge acquired in the main process is used as an evaluation function to gradually acquire words from letters and sentences from words as new prospective processing.

As a similar application example, protein synthesis can be considered. It is possible to obtain a combination of amino acids that forms a protein that meets the purpose (the evaluation function given from the outside) by performing a process of considering amino acids as a prospective treatment and repeating the prospective treatment (combining amino acids). It can be considered as a kind of self-organization.

FIG. 9 can also be considered as a model for narrowing down prospective processing. For example, consider genes as a prospective process. Repeat the expected process (recombining / combining genes) and leave only the expected process (gene or combination of genes) that matches the purpose (e.g., evaluation criteria for resistance to pests, high nutrition, safety, etc.) (narrow down) )be able to. It is considered as a kind of Genetic Algorithm.

Next, referring to FIG. 12 and Table 2, Visionary
An example of the information stored in Memory is shown. Figure 12 shows Vision
An example of transition of ary Process is shown. In FIG. 12, only two of s1 and s2 are considered as the prospective process, and after the input i1 is given to the initial state S, s1 or s2 is repeated three times, and then the convergent solutions of r1 to r4 are obtained. Shows.

Table 2 corresponds to FIG. 12 and corresponds to Visionar
An example of the information stored in yMemory is shown.

[0073]

[Table 2]

For example, in the first row of Table 2, after the input i1 is given to the initial state S, the transition 000 (that is, the prospective processing s1, s1, s1) is executed, and as a result, the convergent solution r1.
Is obtained.

The Visionary Memory is searched at an appropriate timing, and the transition corresponding to the convergent solution (sequence of expected processing)
Is registered in the local storage device 140, a new prospective process is acquired.

FIG. 13 is a modification of the autonomous prospective process acquisition model shown in FIG. In FIG. 13, a probable process considering causal relationships with the main process to some extent shown in FIG.
Assuming a case in which the prospective processes that hardly consider the relationship with the main process shown in FIG.
The latter is called fancy processing.

In FIG. 13, reference numeral 910 denotes a main process, which normally performs a routine process (a program for which an algorithm is fixed) based on the input 911, and the result 91
2 is output.

In the case of NOP, the local storage device 140-1
Randomly select one of the multiple expected processes in
While using the input data 911 as necessary, the selected prospect processing 951 is executed (920). The execution result and the selected expected processing information 921 are the Specurative Memory 9
Stored in 60.

When the execution result stored in the speculative memory 960 is not a steady solution or an effective solution, this solution is used as new input data 961 to randomly select and execute a new prospective process from the local storage device 140-1. . Alternatively, the previously selected prospect processing is executed again. The above processing is repeated for a fixed period. When a steady solution or an effective solution is obtained by chance while repeating for a certain period of time, the solution is used in the main process 910. In addition, the sequence 962 of the prospect processing until the steady solution (or the valid solution) is obtained is registered in the local storage device 140-1 as a new prospect processing.

Alternatively, in the case of NOP, one is randomly selected from a plurality of fancy processings in the local storage device 140-2, and while using the input data 911 as needed, the selected fancy processing is performed. The processing 952 is executed (93)
0). The execution result and the selected fancy processing information 931 are
It is stored in Visionary Memory 970.

When the execution result stored in the Visionary Memory 970 is not a stationary solution or an effective solution, this solution is used as new input data 971 to randomly select and execute a new fantastic process from the local storage device 140-2. To do. Alternatively, the previously selected fantastic process is executed again. The above processing is repeated for a fixed period. When a steady solution or an effective solution is obtained by chance while repeating for a certain period of time, the solution is used in the main process 910. In addition, the sequence 972 of the prospect processing until the steady solution (or the effective solution) is obtained is set as a new prospect processing in the local storage devices 140-1 and 140-1.
Register 0-2.

As described above, in the embodiment shown in FIGS. 1 to 13, the example in which the processor in the NOP state is utilized for the execution of the expected processing (fantasy processing) has been shown. Even if an invalid prospective process (fantasy process) is executed, it is originally N
This is because the performance is not deteriorated because the processor in the OP state is used.

Instead of the NOP, it is possible to recognize some external condition (execution condition) and execute the prospective process (fantasy process). It is also possible to allocate a dedicated processor for the prospective processing (fantasy processing).

As described above, in the embodiments shown in FIGS. 1 to 13, the SIMD type computer is taken as an example, but the present invention is not particularly limited to the SIMD type computer. A similar effect can be expected with a MIMD computer.

A local storage device 1 for storing the expected processing
40 does not need to be included in each processor unit. It is also possible to have a processor group (for example, a chip or a board) as a unit.

The present invention can be applied in various ways depending on the application field (main process) and the expected process (fantasy process). Hereinafter, application examples of the present invention will be described with reference to FIGS. 14 to 16.

FIG. 14 shows an example of application to a process that proceeds in an interactive manner between a person and a machine or a machine-to-machine. In FIG. 14, 1400 is a person (or machine),
1500 is a machine. 1401 to 1421 are people 14
00 to machine 1500 response, 1501-1531
Shows a response from machine 1500 to person 1400. Reference numerals 1410, 1420, and 1510 to 1530 indicate that the input is judged and some processing is performed. For example, at 1420, a function f _i is selected in response to the decision made on the input B _i-1 1522, and the function transformation f _i is applied to the input B _i-1 to obtain the result A _i 1421 on the machine 1
Return to 500. At 1530, the function g _i is selected in response to the decision made on the input A _i 1421, and the function transformation g _i is selected.
The result B _i 1531 applied to the input A _i is returned to the person 1400.

Here, in a world in which the functions that can be selected are limited in advance, such as Go and Shogi, the response (response) of the other party is limited to the response that is output next. Therefore, it is possible to make a good prediction by repeating (for one or more times) the expected processing of "preparing the next one's answer to the expected answer of the other party by utilizing the processor in the NOP state". If it hits, the TAT will be shortened. Alternatively, as a result of repeating such a probable process, from the viewpoint of "in order to obtain the best result (for me)", do not interrupt the realization of complicated functions or thinking by deciding the first one's answer. The flow of dialogue can be realized.

FIG. 15 shows an example of application of a neurocomputer to a self test. The neurochip 11 shown in FIG.
0 is composed of a plurality (two in FIG. 15) of elements PE120, a local memory device 140, a test data memory device 150, and an in-chip failure flag register FRC180. In FIG. 15, only the self-test that is online (operating) is assumed as a prospective process, and the micro-instruction for testing is independent of the micro-instruction 210 for normal operation (input from the microcontroller) for each neurochip 110.
This is because the micro-instruction 210 for normal operation and the instruction 141 for test can be selectively executed by being distributedly arranged in the local storage device 140 inside. Each of the local storage device 140 and the test data storage device 150 is composed of a rewritable memory (for example, RAM, EPROM, register, etc.), and can be rewritten by an application or a task (process). In FIG. 15, the element PE120
Is a weight value storage device CW that stores a weight value that is the coupling strength between the arithmetic unit group 130, the input buffer 121, the output buffer 122, the control signal decision logic 160, and the neurons.
It is composed of M170. Control signal decision logic 16
0 is the Inst. This is a logic that combines the decision logic 165 and the NOP determination logic 166. Arithmetic unit group 130
Is an arithmetic and logic unit 131 with a shifter function, a multiplier 132, a register group 133, a flag register 134,
It is composed of a PE failure flag register FR135. In FIG. 15, online (operating) as a prospective process
The memory IWM that stores the weight value information indicating the probability of each prospective process because only the self-test in the middle is assumed.
175 does not have.

The outline of the operation will be described with reference to FIG. For example, when CS 220 is 1 (normal operation), the control signal determination logic 160 outputs the microinstruction 210 input from the microcontroller 220 as the instruction 161 for controlling the computing unit group 130. In accordance with the control signal 161, the arithmetic unit group 130 receives, for example, input data from another element PE (neuron) input from the Din 230-1 via the input buffer 121 and the signal line 171 from the CWM 170.
The internal state of the neuron is calculated from the weight value data input via. Alternatively, the weight value is updated.
Data output to another PE (neuron) is performed using the Dout 230-2 via the output buffer 122. On the other hand, when CS220 is 0 (the chip is not selected) (or CS220 is 1 and the input 1 from the flag register is 1).
When 62 is a specific value (for example, 1), the control signal determination logic 160 outputs the test micro instruction input from the local storage device 140 via the signal line 141 as the instruction 161 for controlling the arithmetic unit group 130. To do. Arithmetic unit group 13
In accordance with the control signal 161, 0 inputs test data from the test data storage device 150 via the signal line 151, and performs a functional test of each arithmetic unit group. The expected value of the operation result is, for example, a part of the REG 133 (address fixed) in advance.
Stored in. If no failure is detected as a result of the test, the FR 135 holds the initial value (for example, 0). If a fault is detected, FR 135 updates the value (set to 1, for example). Also, the value of the weight value in the weight value storage device 170 is set to 0. That is, the faulty PE (neuron) is separated from the system. The value of each PE failure flag register FR135 is ORed and set in the chip failure flag register FRC180. FRC1
The value of 80 is transmitted to the microcontroller 200 as the failure detection signal 181. Micro controller 200
Detects a failure occurrence by the failure detection signal 181,
A failure countermeasure instruction is given to the host computer 400. In accordance with the failure countermeasure instruction, the host computer 400 displays a failure occurrence notification and a failure occurrence location to the user, for example. Alternatively, the faulty unit (board,
The chip or PE) information is provided to the compiler so that no task (process) is assigned to the failed unit.

As shown in FIG. 15, N in the online state is
An application example of the OP section to the self-test is shown. It is effective as an online test when the tested part is in a running state after a sufficiently short time. If there is a long time interval before it becomes operational, it has no meaning as an online test. Therefore, this is a speculative process. However,
It is also possible to perform an offline test while online to consider that the faulty processor is isolated from the system and self-repairing such as avoiding task assignment to the faulty processor.

FIG. 16 shows an example of application to search processing. In FIG. 16, S is the current state, i1 is an input, and an example is shown in which the final process (or search result) is selected as a result of repeating the search (determination) three times. Each branch (0 or 1) is the determination result at each node, and each leaf is the final processing (or search result). In the current state S, for example, if there are sufficient NOP state processors,
If all final processes (or search results) are obtained in advance, TAT can be shortened. When there are not enough processors in the calculation time and NOP state, possible processes (s1 to s4 in FIG. 16) are randomly selected from the current state (or according to IWM shown in FIG. 2). If an appropriate prospect process is selected, the search time can be shortened.

As an application example in which a process that may occur in the future like the search process is processed in advance, risk prediction or risk avoidance in nuclear power generation or the like can be considered. That is, in the present state, if there is a processor in the NOP state, for example, it is possible to predict and avoid a selection that may lead to a danger or a failure by previously determining the final processing (or the previous result).

In the above, the technique for executing the arbitrarily set program by utilizing the processor in the NOP state in the massively parallel machine has been described. As a modification, it is also possible to realize it as a dedicated processor for predictive processing. For example, the element processor 120 shown in FIG. 2 can be used alone.

FIG. 19 shows, as a third embodiment, for example, temperature, dehumidifying function, air volume (strong, medium, weak), wind type (constant direction,
An example in which a dedicated processor 1900 targeting an air conditioner that can be specified by the user (right and left, random) is shown is shown. As the estimation process, as the initial value of the air conditioner, the previous user set value (temperature, dehumidifying function, air volume, wind type) under the same environmental conditions (eg, room temperature, humidity, time)
It is assumed that the operation will be started using.

In FIG. 19, reference numeral 1910 denotes a prospective value memory, which is a set value (temperature, dehumidifying function,
This is a rewritable storage device that stores air volume and type.

As the initial value, standard data is stored in advance. Alternatively, the specification should be such that the user can set it when purchasing an air conditioner. 1920 is a logic for generating a pointer of the expected value memory 1910 based on environmental conditions such as room temperature and humidity and time (day of the week). 1930 is a timer, 1
940 analyzes environmental information input from outside the system,
A logic for outputting environmental conditions such as room temperature and humidity, 1950 is a sensor for inputting environmental information from outside the system.

Next, the operation of the LSI 1900 will be briefly described with reference to FIG. At the same time when the switch of the air conditioner is turned on, the LSI 1900 inputs environmental information such as room temperature and humidity from outside the system through the signal line 1966 and transmits it to the environmental analysis logic 1940 through the signal line 1951.
The environment analysis logic 1940 analyzes the environment information input via the sensor 1950, converts the environment data such as room temperature and humidity into an appropriate format, and transmits it to the prospective value memory pointer determination logic 1920 via the signal line 1941. The predictive value memory pointer determination logic 1920 generates a predictive value memory pointer 1921 from environmental data such as room temperature and humidity and time (day of the week). For generation, a three-dimensional table having variables such as room temperature, humidity and time is used. The reason why the time (day of the week) is considered as one of the variables is that the time (day of the week) may determine the user's state such as after bathing, bathing, eating, and sleeping to some extent. That is, this is to determine the initial setting value of the air conditioner from the external environmental conditions and the user's condition (probable state). Expected value memory 19
10 outputs the data stored in the address designated by the pointer 1921 as initial value signals 1971 to 1974 for controlling temperature, humidity, air volume, and wind type, respectively. The initial value signals 1971 to 1974 are the signals 1981 to 19 for controlling temperature, humidity, air volume, and wind type, respectively.
84. If the expected initial value is not appropriate,
The user gives an instruction to change the setting of temperature, humidity, air volume, or air type, but the change information is L through the signal line 1960.
Input to SI1900. When the user gives an instruction to change the setting of temperature, humidity, air volume, or air type, the value of the signal line 1965 changes (for example, from 0 to 1). When the value of the signal line 1965 changes (for example, from 0 to 1), the signals 1971 to 1 read from the expected value memory 1910.
The value specified by the user instead of 974 1960 (196
1 to 1964) are signals 1981 to 1984 for controlling temperature, humidity, air volume, and wind type, respectively. Further, the set value 1960 (1961-1964) designated by the user is stored in the address designated by the pointer 1921 as data for controlling temperature, humidity, air volume, and wind type, respectively. Home appliances such as air conditioners are gradually becoming more sophisticated (that is, the contents of the expected value memory 1910 are updated), and the number of user-designable elements is increasing. However, it is troublesome to specify all these settings each time the air conditioner is turned on. By using the LSI 1900, it is possible to determine the initial setting value (expected value) of the air conditioner from external environmental conditions and the user's condition (expected state). Further, even if the expected initial value is not completely appropriate, generally, only a part of the designation (for example, wind type) may be changed.

FIG. 20 shows, as a modification, an example implemented as a dedicated processor 2000 targeting a television for which an initial channel is set prospectively. As the estimation process, it is assumed that the operation is started using the previous user-set channel value under the same environmental condition (for example, day of the week, time) as the initial channel value of the television.

In FIG. 20, reference numeral 2010 denotes a prospective value memory, which is a rewritable storage device for storing the channel value designated by the user. As an initial value, an appropriate value (channel information of a program having a high audience rating) is stored in advance. Alternatively, the specifications are such that the user can set when purchasing the television. A logic 2020 is a logic for generating a pointer of the prospect value memory 2010 based on the day of the week and the time. Two
Reference numeral 030 is a timer, and reference numeral 2035 is a logic that corrects the time input from the timer and converts it to a clear time such as 9:00 PM and 9:30 PM. This is because, for example, when the television switch is turned on at 8:56 PM, the program the user wants to watch is supposed to start from 9:00 PM. Reference numeral 2040 is a logic that analyzes the channel information designated by the user and determines which channel (program) is being watched at each time, and 2050 is a logic that monitors the channel information designated by the user.

Next, the operation of the LSI 2000 will be briefly described with reference to FIG. At the same time when the television switch is turned on, the prospective channel value memory 2010 sets the data (channel value) stored at the address designated by the pointer 2021 to the signal line 2 as the initial value of the channel.
Output to 070. The value of the signal line 2070 becomes the channel value signal (or channel control signal) 2080 as it is. The pointer 2021 is generated in the prospective memory pointer determination logic 2020 from the day and time information. Upon generation, a two-dimensional table having variables such as the day of the week and the time of day is used. Timer 20 for day of week information
It is input from 30 through the signal line 2032. The time is input from the correction logic 2035 via the signal line 2036. The correction circuit 2035 corrects the time input from the timer 2030 via the signal line 2031, converts the time into a clear value (the time at which a normal TV program starts), and outputs the value to the expected value memory pointer determination logic 2020. If the expected initial channel value is not appropriate, the user has to reset the channel, but the change information is input to the LSI 2000 via the signal line 2060. Further, the value of the signal line 2065 changes (for example, from 0 to 1) at the same time when the user resets the channel. When the value of the signal line 2065 changes (for example, from 0 to 1), the expected channel value memory 20
A value (channel information) designated by the user is transmitted to the signal line 2080 in place of the signal 2070 read from the signal 10. The channel monitor 2050 observes the channel information specified by the user and outputs it to the channel determination logic 2040 via the signal line 2051. Channel decision logic 2040
Determines the channel of the program watched by the user for each time period based on the information input from the channel monitor 2050. For example, the channel with the longest total time between 9:00 PM and 10:00 PM is determined to be the channel of the program the user is watching. The determined channel information is transmitted to the prospective channel value memory 2010 via the signal line 2041 and stored in the address designated by the pointer 2021. (That is, prospective channel value memory 2010
The content is updated) Currently, when the TV is turned on, the channel when the switch was turned off last time is the initial value. However, there are many people who usually decide what program to watch on what day of the week and at what time. By using the LSI 2000, it is possible to determine the initial value (probable value) of the channel when the switch is turned on from the channel information of the program that the user regularly watches. That is, if the chances are good, it means that the channel is set to the program one wants to watch when the switch is turned on.

As described above, FIG. 19 and FIG. 20 show the example in which the initial value is estimated and the process is started based on the previous value under the same environmental condition. Such ideas can be applied to other home appliances. For example, in a video, a reservation for this week may be automatically (probably) set with reference to the reservation information for last week, and only a part different from the user's intention may be corrected.

[0103]

As described above, according to the present invention, in a massively parallel computer, (1) improvement of utilization rate (2) automation of forecast processing (when and what forecast processing is executed) (3) Self-acquisition of a new prospective process from the minimum required prospective process (4) In addition to the above (1) to (3), it is possible to provide added value such as shortening of TAT.

Therefore, it is one of the solutions to the problem of the lowering of the operating rate when the number of element processors constituting the system is increased. Further, it becomes possible to deal with more complicated information processing (close to the human right brain).

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration diagram of a massively parallel computer system.

FIG. 2 is a diagram showing a configuration diagram of an element processor.

FIG. 3 is a diagram showing a flowchart for learning appropriate prospective processing gradually through experience.

FIG. 4 is a diagram showing an example of a block diagram of an arithmetic unit group.

FIG. 5 is a diagram showing an example of instruction decision logic.

FIG. 6 is a diagram showing selection success / failure determination.

FIG. 7 is a diagram showing a weight value (IWM) update process.

FIG. 8 is a diagram illustrating an example of a realization unit for a fancy process.

FIG. 9 is a diagram illustrating an example of execution of a prospective process and acquisition of an autonomous prospective process.

FIG. 10 is a diagram showing an acquisition flow of autonomous prospective processing.

FIG. 11 is a diagram illustrating an example of autonomous acquisition of a prospective process.

FIG. 12 is a diagram showing an example of transition of a fancy process.

FIG. 13 is a diagram illustrating an example of a combination of a prospective process and a fancy process.

FIG. 14 is a diagram showing an application example to interactive processing.

FIG. 15 is a diagram showing an example of application of a neurocomputer to a self test.

FIG. 16 is a diagram illustrating an example of application to search processing.

FIG. 17 is a diagram showing a conventional example (SIMD type massively parallel computer).

FIG. 18 is a diagram illustrating a conventional example (an example of instruction prefetch).

FIG. 19 is a diagram showing an LSI block diagram for setting an estimated initial value of an air conditioner.

FIG. 20 is a diagram showing an LSI block diagram for television initial channel estimation setting.

[Explanation of symbols]

110 ... Processor array, 200 ... Micro controller, 210 ... Micro instruction, 140 ... Local storage device,
175 ... Instruction weight memory, 165 ...
Instruction determination logic, 166 ... NOP determination logic, 130 ... Operation unit group, 190 ... Success / failure determination logic of selected instruction.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koji Kameshima, inventor Kojitamachi, 502, Tsuchiura, Ibaraki Prefecture, Institute of Mechanical Research, Hiritsu Seisakusho Co., Ltd. Inside Hitachi Research Laboratory

Claims (27)

[Claims] 1. An array composed of a plurality of processors,
In a parallel computer system having a controller for controlling the array, at least one of the plurality of processors has at least one program for a prospective process which may or may not be useful in the future. A parallel computer system characterized by executing a program for the above-mentioned expected process. 2. The parallel computer system according to claim 1, further comprising a process determining means for specifying a program for one prospective process from a plurality of programs for the prospective process. 3. A processor for determining a specific condition for each of the processors or a group of a plurality of processors, and according to the specific condition, the main program is replaced with the specified expected processing. 3. The parallel computer system according to claim 2, wherein a program for performing the processing is set as a processing target. 4. The parallel computer system according to claim 3, wherein the specific condition is a NOP (No OPeration) instruction. 5. The parallel computer system according to claim 2 or 3, further comprising arithmetic means for executing the specified program for the expected processing. 6. An evaluation means for evaluating the calculated result according to a specific standard.
The described parallel computer system. 7. The process determining means for specifying one program for the prospective process from among the plurality of programs for the prospective process is to specify the program for the prospective process by using a random number table. The parallel computer system according to claim 2. 8. The random number table is realized by using a pseudo-random binary sequence counter.
The described parallel computer system. 9. A process determining means for specifying a program for one prospective process from among a plurality of programs for the prospective process has certainty factor information corresponding to each prospective process, and certainty factor information. 3. The parallel computer system according to claim 2, wherein a program for expected processing to be executed is specified based on the above. 10. The parallel computer system according to claim 9, further comprising means for updating the certainty factor information corresponding to each of the prospective processings on-line (operating) according to the evaluation means. 11. The parallel computer system according to claim 5, further comprising means for storing the calculated result, means for searching the expected processing result, and selecting a result according to a specific criterion. . 12. The parallel computer according to claim 11, wherein the information to be stored in the means for storing the expected processing result is labeling information or the like for facilitating the search, which is added to the calculation result and stored. system. 13. The parallel computer system according to claim 5, wherein the arithmetic means for executing the specified program is executed by utilizing an element processor in a NOP (No OPeration) state. 14. As the above-mentioned expected process, a process of preparing the next one's own answer in advance with respect to some expected answers of the other party is assumed, and the process proceeds interactively, and
The parallel computer system according to claim 1, wherein the parallel computer system is applied to a game such as a game of Go / Shogi or an interactive computer in which the selectable answers are limited in advance. 15. The parallel computer system according to claim 1, wherein an online self-test of the NOP unit is assumed as the expected process and is applied to improve the reliability of a neuro computer and a massively parallel computer. 16. A function for automatically separating (self-repairing) a board, a chip, or a processor, which is a failure unit, from a parallel computer system when a failure is detected as a result of the test. 15. The parallel computer system according to item 15. 17. The means for automatically separating (self-repairing) the faulty unit from the parallel computer system is realized by rewriting the value of the memory storing the coupling strength between the processors. 16. A parallel computer system according to item 16. 18. The parallel computer system according to claim 1, wherein a final process (or a search result) in the search process is assumed as the expected process and is applied to shorten the TAT of the search process. 19. The parallel computer system according to claim 1, wherein the expected process is a process that may occur in the future in a process involving a risk and is applied to risk prediction or risk avoidance. 20. The parallel computer system according to claim 1, wherein an amino acid or data expressing an amino acid is assumed as the above-mentioned probable processing and is applied to protein synthesis suitable for a purpose. 21. The parallel computer system according to claim 1, wherein the prospective processing is applied to narrowing down a gene suitable for a purpose by assuming a gene or data expressing a gene. 22. The parallel computer system according to claim 1, further comprising means for autonomously acquiring a new program based on the program for the prospective processing. 23. The means for autonomously acquiring a new program based on the program for the prospective processing, the result of repeating the program for the prospective processing a plurality of times until a result satisfying a specific criterion is obtained. 23. The parallel computer system according to claim 22, which is realized by storing a combination of programs for the above-mentioned prospect processing as a new program in a storage device. 24. A processor for the purpose of predetermined control or determination of an initial value, wherein at least one data whose validity is not always guaranteed is processed. 25. The processor according to claim 24, further comprising means for storing at least one data whose validity is not guaranteed. 26. The processor according to claim 24, wherein the at least one data whose validity is not always guaranteed is a previous user specified value under the same environmental condition. 27. The processor according to claim 26, wherein the environmental condition includes at least one of room temperature, humidity, time of day, and day of the week.