JP4395412B2 - Constant voltage circuit - Google Patents
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Description
本発明は、基準電圧発生回路を使用した定電圧回路に係り、特に基準電圧に含まれるノイズの吸収と電源投入時の立ち上がりの高速化の双方を同時に図った定電圧回路に関するものである。 The present invention relates to a constant voltage circuit that uses a reference voltage generation circuit, and more particularly to a constant voltage circuit that simultaneously absorbs noise contained in a reference voltage and speeds up rising when power is turned on.
バンドギャップ電圧を利用して温度補償を行う基準電圧発生回路を使用した従来の定電圧回路は、図３に示すように、ベースが共通接続されたＮＰＮトランジスタＱ１，Ｑ２、トランジスタＱ１と接地間に接続され且つトランジスタＱ２のエミッタが共通接続点に接続された抵抗Ｒ１，Ｒ２、トランジスタＱ１，Ｑ２のコレクタ電流を供給するカレントミラー接続のＰＮＰトランジスタＱ４，Ｑ５、バッファアンプとして働くＰＮＰトランジスタＱ３からなる基準電圧発生回路１（例えば、特許文献１参照）と、抵抗Ｒ３とキャパシタＣ１からなるＣＲフィルタ回路２とで構成されている。３は出力端子、４は基準電圧ノードである。トランジスタＱ１，Ｑ２の面積比はＮ１：１に設定されている。
As shown in FIG. 3, a conventional constant voltage circuit using a reference voltage generation circuit that performs temperature compensation using a bandgap voltage has NPN transistors Q1 and Q2, whose bases are commonly connected, and between the transistor Q1 and the ground. A reference composed of resistors R1 and R2 connected to each other and having the emitter of the transistor Q2 connected to a common connection point, PNP transistors Q4 and Q5 in current mirror connection for supplying collector currents of the transistors Q1 and Q2, and a PNP transistor Q3 serving as a buffer amplifier The voltage generating circuit 1 (see, for example, Patent Document 1) and a
この定電圧回路では、トランジスタＱ１，Ｑ２のコレクタにトランジスタＱ４，Ｑ５により同じ電流を供給すると、基準電圧ノード４に得られる基準電圧Ｖrefは、
Ｖref＝ＶBE2＋ＶR2
＝ＶBE2＋２・R2/R1・ＶT・ln（N1） (1)
で与えられる。ＶBE2はトランジスタＱ２のベース・エミッタ間電圧、ＶR2は抵抗Ｒ２に発生する電圧、R2/R1は抵抗Ｒ１，Ｒ２の抵抗比、ＶTは負の温度係数を持つサーマル電圧（＝kT/q）、lnは自然対数である。なお、ｋはボルツマン定数、Ｔは絶対温度、ｑは電子の電荷である。
In this constant voltage circuit, when the same current is supplied to the collectors of the transistors Q1 and Q2 by the transistors Q4 and Q5, the reference voltage Vref obtained at the
Vref = V BE2 + V R2
＝ V BE2 ＋2 ・ R 2 / R 1・ V T・ ln （N1） (1)
Given in. V BE2 is a base-emitter voltage of the transistor Q2, V R2 is a voltage generated in the resistor R2, R 2 / R 1 is a resistance ratio of the resistors R1 and R2, and V T is a thermal voltage having a negative temperature coefficient (= kT / q), ln is the natural logarithm. Here, k is a Boltzmann constant, T is an absolute temperature, and q is an electron charge.
そして、基準電圧Ｖrefが温度変化ｄＴに対して安定化するようにトランジスタＱ１，Ｑ２の面積比Ｎ１や抵抗Ｒ１，Ｒ２の値Ｒ2，Ｒ1が設定される。すなわち、
ＶBE2／ｄＴ＋２・R2/R1・ＶT・ln（N1）＝０ (2)
となるように条件を設定し、(2)式の左式の第１項（負の温度特性）の温度による変化を第２項（正の温度特性）が打ち消すようにしている。
The reference voltage Vref has a value R 2, R 1 of the area ratio of to stabilize the transistor Q1, Q2 N1 and resistors R1, R2 are set to temperature changes dT. That is,
V BE2 / dT + 2 ・ R 2 / R 1・ V T・ ln (N1) = 0 (2)
The conditions are set so that the second term (positive temperature characteristic) cancels the change of the first term (negative temperature characteristic) in the left expression of equation (2) due to temperature.
また、この定電圧回路では、基準電圧Ｖrefに含まれるノイズが抵抗Ｒ３とキャパシタＣ１からなるＣＲフィルタ回路２によって除去され、そのカットオフ周波数ｆｃは、
ｆｃ＝１／（２π・Ｃ1・Ｒ3） (3)
となる。Ｃ1はキャパシタＣ１の容量、Ｒ3は抵抗Ｒ３の抵抗値である。さらに、電源電圧Ｖccの立ち上がり時の出力電圧Ｖｏ(t)の特性は、ＣＲフィルタ回路２の時定数τ（＝Ｃ1・Ｒ3）によって、
Ｖｏ(t)＝Ｖｏ［１−exp（−ｔ/τ）］ (4)
となり、図４に示す特性となる。
fc = 1 / (2π · C 1 · R 3 ) (3)
It becomes. C 1 is the capacitance of the capacitor C 1 , and R 3 is the resistance value of the resistor R 3 . Further, the characteristics of the output voltage Vo (t) at the rise of the power supply voltage Vcc are determined by the time constant τ (= C 1 · R 3 ) of the
Vo (t) = Vo [1-exp (−t / τ)] (4)
Thus, the characteristics shown in FIG. 4 are obtained.
ところが、上記した定電圧回路では、ノイズを低減するためにカットオフ周波数ｆｃを下げるには、抵抗Ｒ３又はキャパシタＣ１の値を大きくする必要があるが、このようにすると時定数τが大きくなってしまい、電源電圧Ｖccの立ち上がり時の出力電圧Ｖｏの立ち上がりが遅くなるという問題があった。 However, in the above-described constant voltage circuit, in order to reduce the cut-off frequency fc in order to reduce noise, it is necessary to increase the value of the resistor R3 or the capacitor C1, but this increases the time constant τ. As a result, the rise of the output voltage Vo at the rise of the power supply voltage Vcc is delayed.
本発明の目的は、基準電圧発生回路で発生するノイズを低減でき、しかも電源電圧立ち上がり時の出力電圧の立ち上がりも高速化できるようにした定電圧回路を提供することである。 An object of the present invention is to provide a constant voltage circuit that can reduce noise generated in a reference voltage generation circuit and that can also speed up the rise of the output voltage when the power supply voltage rises.
請求項１にかかる発明は、基準電圧発生回路と、該基準電圧発生回路で発生した基準電圧に含まれるノイズを吸収するためのＣＲフィルタ回路と、電源投入時の前記基準電圧発生回路の立ち上がりを検出して前記ＣＲフィルタ回路のキャパシタを急速充電するコンパレータ回路と、を具備する定電圧回路において、前記基準電圧発生回路は、前記基準電圧が生成される基準電圧ノードにベースが共通接続された第１導電型の第１，第２のトランジスタと、該第１のトランジスタのエミッタと接地間に直列接続され且つ共通接続点に前記第２のトランジスタのエミッタが接続された第１，第２の抵抗と、エミッタが電源端子に接続されベースが前記第１のトランジスタのコレクタに接続され、コレクタが前記基準電圧ノードに接続された第２導電型の第３のトランジスタと、エミッタが前記電源端子に接続されコレクタが前記第１のトランジスタのコレクタに接続された第２の導電型の第４のトランジスタと、エミッタが前記電源端子に接続されコレクタが前記第２のトランジスタのコレクタに接続され、ベースが前記第４のトランジスタのベースに接続され且つベースとコレクタが共通接続された第２の導電型の第５のトランジスタと、を具備し、且つ出力電圧の立ち上がり後の前記第３のトランジスタのベース・エミッタ間電圧が前記第５のトランジスタのベース・エミッタ間電圧より小さくなるよう設定され、前記コンパレータ回路は、前記第３のトランジスタのベース電圧と前記第５のトランジスタのベース電圧を比較し、前者が後者より低いときのみ、前記ＣＲフィルタ回路への急速充電電流を供給する、ことを特徴とする。 The invention according to claim 1 includes a reference voltage generation circuit, a CR filter circuit for absorbing noise included in the reference voltage generated by the reference voltage generation circuit, and a rise of the reference voltage generation circuit when the power is turned on. A constant voltage circuit that detects and rapidly charges a capacitor of the CR filter circuit , wherein the reference voltage generating circuit has a base commonly connected to a reference voltage node where the reference voltage is generated. First and second transistors of one conductivity type, and first and second resistors connected in series between the emitter of the first transistor and the ground and having the emitter of the second transistor connected to a common connection point A second conductor having an emitter connected to the power supply terminal, a base connected to the collector of the first transistor, and a collector connected to the reference voltage node. A third transistor of the type, a fourth transistor of the second conductivity type having an emitter connected to the power supply terminal and a collector connected to the collector of the first transistor, and an emitter connected to the power supply terminal Is connected to the collector of the second transistor, the base is connected to the base of the fourth transistor, and the base and the collector are connected in common. The base-emitter voltage of the third transistor after the rising of the output voltage is set to be smaller than the base-emitter voltage of the fifth transistor, and the comparator circuit has the base voltage of the third transistor The base voltage of the fifth transistor is compared, and only when the former is lower than the latter, the CR filter circuit Supplying a rapid charging current to, characterized in that.
本発明によれば、基準電圧発生回路の立ち上がりタイミングをコンパレータ回路で検出してＣＲフィルタ回路のキャパシタへの急速充電を行うので、時定数τの大きなＣＲフィルタ回路を使用してカットオフ周波数を低下させて基準電圧に含まれるノイズ低減を図っても、電源電圧立ち上がり時の出力電圧立ち上がりを高速化することができる。つまり、ノイズ低減と出力電圧立ち上がり高速化の両者を満足させることができる。よって、特にノイズを低減するためにカットオフ周波数の低いＣＲフィルタ回路を使用する場合に効果的である。 According to the present invention, the rise timing of the reference voltage generation circuit is detected by the comparator circuit and the capacitor of the CR filter circuit is rapidly charged, so the cut-off frequency is lowered by using the CR filter circuit having a large time constant τ. Even if the noise included in the reference voltage is reduced, the rise of the output voltage at the rise of the power supply voltage can be accelerated. That is, both noise reduction and output voltage rise speed can be satisfied. Therefore, this is particularly effective when a CR filter circuit having a low cut-off frequency is used in order to reduce noise.
図１は本発明の１つの実施例の定電圧回路の構成を示す回路図である。本実施例の定電圧回路では、ベースが共通接続されたＮＰＮトランジスタＱ１，Ｑ２と、トランジスタＱ１と接地間に接続され且つ共通接続点にトランジスタＱ２のエミッタが接続された抵抗Ｒ１，Ｒ２と、トランジスタＱ１，Ｑ２に同じコレクタ電流を供給するカレントミラー接続のＰＮＰトランジスタＱ４，Ｑ５（トランジスタＱ５が基準側、トランジスタＱ４が出力側）と、バッファアンプとして働くＰＮＰトランジスタＱ３とからなる基準電圧発生回路１が構成されている。また、基準電圧ノード４と出力端子３の間には、抵抗Ｒ３とキャパシタＣ１からなるＣＲフィルタ回路２が接続されている。さらに、ＮＰＮトランジスタＱ６，Ｑ７と、カレントミラー接続のＰＮＰトランジスタＱ８，Ｑ９と、定電流源Ｉ２と、、ＰＮＰトランジスタＱ１０とにより、トランジスタＱ１，Ｑ２のコレクタ電圧を比較してキャパシタＣ１への充電電流を供給するコンパレータ回路５が構成されている。トランジスタＱ１，Ｑ２の面積比はＮ１：１に設定され、トランジスタＱ３，Ｑ５の面積比はＮ２：１に設定されている。
FIG. 1 is a circuit diagram showing a configuration of a constant voltage circuit according to one embodiment of the present invention. In the constant voltage circuit of this embodiment, NPN transistors Q1 and Q2 whose bases are connected in common, resistors R1 and R2 connected between the transistor Q1 and the ground, and the emitter of the transistor Q2 connected to the common connection point, A reference voltage generating circuit 1 comprising PNP transistors Q4 and Q5 in a current mirror connection for supplying the same collector current to Q1 and Q2 (transistor Q5 is a reference side, transistor Q4 is an output side) and a PNP transistor Q3 serving as a buffer amplifier is provided. It is configured. A
さて、電源電圧Ｖccの立ち上がり時は、トランジスタＱ３のコレクタ電流は、トランジスタＱ１，Ｑ２のベースに、および抵抗Ｒ３を介してキャパシタＣ１に流れ込む。そのとき、トランジスタＱ３，Ｑ５のコレクタ電流をＩC3，ＩC5、ベース・エミッタ間電圧をＶBE3、ＶBE5とすると、通常ＩC3＞ＩC5となるため、ＶBE3＞ＶBE5となる。よって、コンパレータ回路５のトランジスタＱ６はオフし、トランジスタＱ７はオンして、トランジスタＱ１０がオンとなり、そのトランジスタＱ１０のコレクタ電流がキャパシタＣ１に流れ込む。このとき、トランジスタＱ１０のコレクタ電流をＩC10、電流源Ｉ２の電流をＩ2とすると、
ＩC10＝βｐ・Ｉ2 (5)
となる。βｐはＰＮＰトランジスタの電流増幅率である。
When the power supply voltage Vcc rises, the collector current of the transistor Q3 flows into the bases of the transistors Q1 and Q2 and into the capacitor C1 via the resistor R3. At this time, assuming that the collector currents of the transistors Q3 and Q5 are I C3 and I C5 and the base-emitter voltages are V BE3 and V BE5 , since usually I C3 > I C5 , V BE3 > V BE5 . Therefore, the transistor Q6 of the comparator circuit 5 is turned off, the transistor Q7 is turned on, the transistor Q10 is turned on, and the collector current of the transistor Q10 flows into the capacitor C1. At this time, if the collector current of the transistor Q10 is I C10 and the current of the current source I2 is I 2 ,
I C10 = βp · I 2 (5)
It becomes. βp is the current amplification factor of the PNP transistor.
よって、電源電圧Ｖccの立ち上がりの時のキャパシタＣ１への充電電流をＩ1(t)、抵抗Ｒ３に流れる電流をＩR3(t)、抵抗Ｒ３の両端の電圧をＶR3(t)とすると、
Ｉ1(t)＝ＩC10＋ＩR3(t) (6)
ＩR3(t)＝ＶR3(t)／Ｒ３ (7)
となる。この電流Ｉ1(t)は、コンパレータ回路５がない図３の従来回路の場合の充電電流がＩR3(t)のみとなるのに対し、ＩC10だけ大きな電流値であり、このような急速充電により、電源電圧立ち上がり時の出力電圧Ｖｏ(t)の遅延時間を従来回路よりも小さくできる。さらに、この電流ＩC10は(5)式のように定電流源Ｉ２の電流Ｉ2によって決まる値であり、ＣＲフィルタ回路２を構成するキャパシタＣ１と抵抗Ｒ３の値に関係なく設定することができるので、ＣＲフィルタ回路２のカットオフ周波数ｆｃに影響を与えない。
Therefore, if the charging current to the capacitor C1 at the rise of the power supply voltage Vcc is I 1 (t), the current flowing through the resistor R3 is I R3 (t), and the voltage across the resistor R3 is V R3 (t),
I 1 (t) = I C10 + I R3 (t) (6)
I R3 (t) = V R3 (t) / R3 (7)
It becomes. The current I 1 (t) has a large current value by I C10 while the charging current in the conventional circuit of FIG. 3 without the comparator circuit 5 is only I R3 (t). By charging, the delay time of the output voltage Vo (t) when the power supply voltage rises can be made smaller than that of the conventional circuit. Further, the current I C10 is a value determined by the current I 2 of the constant current source I2 as shown in the equation (5), and can be set regardless of the values of the capacitor C1 and the resistor R3 constituting the
本実施例の定電圧回路の出力電圧Ｖｏ(t)の立ち上がり特性を図２に示す。電流ＩC10は電流ＩR3(t)が出力電圧の立ち上がりとともに減少するため、電流ＩC3も減少するので、ＶBE3＝ＶBE5となる時刻ｔ１まで流れる。ＶBE3＜ＶBE5となった時刻ｔ１以降では、コンパレータ回路５のトランジスタＱ６はオン、トランジスタＱ７はオフとなり、トランジスタＱ１０がオフとなるため、充電電流Ｉ1(t)は抵抗Ｒ３を流れるＩR3(t)のみとなり、出力電圧Ｖｏ(t)は時定数τに従って立ち上がることになる。 FIG. 2 shows the rising characteristics of the output voltage Vo (t) of the constant voltage circuit of this embodiment. Since the current I C10 decreases with the rise of the current I R3 (t) is the output voltage, the current I C3 is also reduced, it flows until time t1 when the V BE3 = V BE5. After time t1 when V BE3 <V BE5 , the transistor Q6 of the comparator circuit 5 is turned on, the transistor Q7 is turned off, and the transistor Q10 is turned off, so that the charging current I 1 (t) flows through the resistor R3 I R3 (t) only, and the output voltage Vo (t) rises according to the time constant τ.
また、出力電圧Ｖｏ(t)が完全に立ち上がった後では、基準電圧Ｖrefの変動や素子の不均一性などによりコンパレータ回路５のトランジスタＱ１０から出力端子３に電流が流れ込むことがないように、トランジスタＱ３のベース・エミッタ間電圧ＶBE3とトランジスタＱ５のベース・エミッタ間電圧ＶBE5との間にオフセット電圧ΔＶを持たせる必要がある。すなわち、ＶBE3＜ＶBE5が保持できるように、トランジスタＱ３，Ｑ５のエミッタ面積比をそれぞれの電流比に応じて適切な値Ｎ２：１に設定し、通常動作においてコンパレータ回路５が定電圧回路の特性に影響を及ぼさないようにする。 Further, after the output voltage Vo (t) has risen completely, the transistor is prevented from flowing into the output terminal 3 from the transistor Q10 of the comparator circuit 5 due to fluctuations in the reference voltage Vref, element non-uniformity, or the like. It is necessary to provide an offset voltage ΔV between the base-emitter voltage V BE3 of Q3 and the base-emitter voltage V BE5 of the transistor Q5. That is, the emitter area ratio of the transistors Q3 and Q5 is set to an appropriate value N2: 1 according to the respective current ratios so that V BE3 <V BE5 can be maintained, and the comparator circuit 5 is connected to the constant voltage circuit in normal operation. Do not affect the characteristics.
なお、基準電圧発生回路１で発生するノード４の基準電圧Ｖrefは、前述したように温度特性を持たない電圧であり、この基準電圧Ｖrefに含まれるノイズがＣＲフィルタ回路２で吸収されて、ノイズ低減された安定化電圧が出力端子３に得られる。
Note that the reference voltage Vref of the
１：基準電圧発生回路
２：ＣＲフィルタ回路
３：出力端子
４：基準電圧ノード
５：コンパレータ回路
1: Reference voltage generation circuit 2: CR filter circuit 3: Output terminal 4: Reference voltage node 5: Comparator circuit
Claims (1)
前記基準電圧発生回路は、前記基準電圧が生成される基準電圧ノードにベースが共通接続された第１導電型の第１，第２のトランジスタと、該第１のトランジスタのエミッタと接地間に直列接続され且つ共通接続点に前記第２のトランジスタのエミッタが接続された第１，第２の抵抗と、エミッタが電源端子に接続されベースが前記第１のトランジスタのコレクタに接続され、コレクタが前記基準電圧ノードに接続された第２導電型の第３のトランジスタと、エミッタが前記電源端子に接続されコレクタが前記第１のトランジスタのコレクタに接続された第２の導電型の第４のトランジスタと、エミッタが前記電源端子に接続されコレクタが前記第２のトランジスタのコレクタに接続され、ベースが前記第４のトランジスタのベースに接続され且つベースとコレクタが共通接続された第２の導電型の第５のトランジスタと、を具備し、且つ出力電圧の立ち上がり後の前記第３のトランジスタのベース・エミッタ間電圧が前記第５のトランジスタのベース・エミッタ間電圧より小さくなるよう設定され、
前記コンパレータ回路は、前記第３のトランジスタのベース電圧と前記第５のトランジスタのベース電圧を比較し、前者が後者より低いときのみ、前記ＣＲフィルタ回路への急速充電電流を供給する、
ことを特徴とする定電圧回路。 A reference voltage generation circuit, a CR filter circuit for absorbing noise included in the reference voltage generated by the reference voltage generation circuit, and a rise of the reference voltage generation circuit when the power is turned on to detect the CR filter circuit A constant voltage circuit comprising a comparator circuit for rapidly charging a capacitor ;
The reference voltage generation circuit includes a first conductivity type first and second transistor having a base commonly connected to a reference voltage node where the reference voltage is generated, and a series connection between the emitter of the first transistor and the ground. A first resistor connected to a common connection point and an emitter connected to a power supply terminal; a base connected to a collector of the first transistor; a collector connected to a common connection point; A third transistor of the second conductivity type connected to a reference voltage node; a fourth transistor of the second conductivity type having an emitter connected to the power supply terminal and a collector connected to the collector of the first transistor; The emitter is connected to the power supply terminal, the collector is connected to the collector of the second transistor, and the base is connected to the base of the fourth transistor. And a fifth transistor of the second conductivity type whose base and collector are commonly connected, and the base-emitter voltage of the third transistor after rising of the output voltage is that of the fifth transistor. It is set to be smaller than the base-emitter voltage,
The comparator circuit compares the base voltage of the third transistor and the base voltage of the fifth transistor, and supplies a quick charging current to the CR filter circuit only when the former is lower than the latter.
A constant voltage circuit characterized by that.
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| JP2004160559A JP4395412B2 (en) | 2004-05-31 | 2004-05-31 | Constant voltage circuit |
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| JP2004160559A JP4395412B2 (en) | 2004-05-31 | 2004-05-31 | Constant voltage circuit |
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| JP4395412B2 true JP4395412B2 (en) | 2010-01-06 |
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| KR100836529B1 (en) | 2007-01-15 | 2008-06-10 | (주)태진기술 | Regulator circuit for generating stability voltage |
| CN101578561B (en) * | 2007-06-08 | 2012-06-27 | 松下电器产业株式会社 | High-speed reset circuit |
| JP2009020550A (en) * | 2007-07-10 | 2009-01-29 | Sanyo Electric Co Ltd | Quick charging circuit |
| JP5353548B2 (en) | 2009-08-14 | 2013-11-27 | 富士通セミコンダクター株式会社 | Band gap reference circuit |
| JP7271227B2 (en) * | 2019-02-27 | 2023-05-11 | ローム株式会社 | power circuit |
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