JP4385529B2 - IC chip mounting method - Google Patents

IC chip mounting method Download PDF

Info

Publication number
JP4385529B2
JP4385529B2 JP2001028748A JP2001028748A JP4385529B2 JP 4385529 B2 JP4385529 B2 JP 4385529B2 JP 2001028748 A JP2001028748 A JP 2001028748A JP 2001028748 A JP2001028748 A JP 2001028748A JP 4385529 B2 JP4385529 B2 JP 4385529B2
Authority
JP
Japan
Prior art keywords
film
chip
wiring board
bumps
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001028748A
Other languages
Japanese (ja)
Other versions
JP2002231764A (en
Inventor
敏広 三宅
宏司 近藤
成男 沼澤
克己 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2001028748A priority Critical patent/JP4385529B2/en
Publication of JP2002231764A publication Critical patent/JP2002231764A/en
Application granted granted Critical
Publication of JP4385529B2 publication Critical patent/JP4385529B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

Description

【0001】
【発明の属する技術分野】
この発明はICチップの実装方法に関するものである。
【0002】
【従来の技術】
従来、プリント配線板(PWB)にICチップをフリップチップ法で搭載していたが、接合部の疲労寿命を向上して信頼性を確保するために、チップの下にアンダーフィルと呼ばれる樹脂を注入してきた。これに代わる手法として、基板とチップとの間に樹脂フィルムを挟んで接合を行うことにより基板・チップ間を樹脂で封止する技術がある(特開平9−64237号公報、特許第2812238号公報等)。しかし、電極間の接合強度を高めるとともに、チップとプリント配線板との間の封止性(樹脂の接着性)を向上したいという要求がある。
【0003】
【発明が解決しようとする課題】
そこで、この発明の目的は、より信頼性の高いICチップの実装方法を提供することにある。
【0004】
【課題を解決するための手段】
請求項1に記載のように、バンプを有するプリント配線板とバンプを有するICチップとの間に、バンプに対応する位置に貫通孔を設けた熱可塑性樹脂フィルムを配置した後に、加熱・加圧して、プリント配線板のバンプとICチップのバンプを接合するとともにフィルムを溶融させてICチップとプリント配線板との間を樹脂封止する際に、熱可塑性樹脂フィルムの両面にアルカン類よりなる膜を配置し、この膜をチップ・配線板間に介在させた状態で加熱・加圧してバンプの接合および樹脂封止を行う。すると、フィルムの表面はアルカン類を介在させているので、熱可塑性樹脂フィルムとの界面で、アルカン類が熱可塑性樹脂に浸透して弾性率が下がることにより、接着力が向上し、高い信頼性が得られる。
【0010】
【発明の実施の形態】
比較例
以下、この発明を具体化した実施の形態に先立ち、同実施の形態との比較例について図面に従って説明する。
【0011】
図1〜図3には、本比較例におけるICチップの実装工程を示す。
図1に示すように、プリント配線板(PWB)10において、絶縁基板11には導体パターン12が形成されている。導体パターン12でのICチップとの接合部(PWB端子部)においてはその上面に銅めっきによる突起(厚さ10〜50μm)13が形成され、その上部にはニッケルめっき(厚さ1〜5μm)14と金めっき(厚さ1〜5μm)15が形成されている。このようにプリント配線板10のバンプとして金バンプを用いている。さらに本例では、金バンプ部を含めた配線板上面には、C−H結合解離エネルギーが950kJ/mol以下の炭化水素化合物よりなる膜16が形成されている。具体的には、ジシクロペンタジエン、テトラメチルペンタデカン等よりなる膜を用いる。
【0012】
また、ICチップ20において、シリコンチップ21には金属突起22が形成され、金属突起22は、銅(あるいはアルミまたは金)よりなる膜23にて被覆されている。このようにしてバンプが形成されている。
【0013】
一方、熱可塑性樹脂フィルム30としてPEEK−PEIフィルム(ポリエーテルエーテルケトンとポリエーテルイミドの混合物)を用いており、プリント配線板10のバンプ13〜15およびICチップ20のバンプ22,23に対応する位置に貫通孔31が形成されている。
【0014】
そして、図2に示すように、プリント配線板(PWB)10の上にPEEK−PEIフィルム30を介してICチップ20を位置合わせして重ねる。つまり、プリント配線板10のバンプとPEEK−PEIフィルム30の穴位置とICチップ20のバンプとを一致させて重ねる。
【0015】
この状態で、チップ表面に加熱ツール(ヒータヘッドH)を押し当て、プリント配線板10とPEEK−PEIフィルム30の界面の温度が300〜330℃になるように加熱・加圧する(圧力0.05〜0.5MPa、1〜15秒)。このように熱圧着すると、図3に示すように、ICチップ20の電極とプリント配線板10の金バンプとが接合するとともに、PEEK−PEIフィルム30が溶けて接着する。つまり、図2でプリント配線板10とICチップ20との間に熱可塑性樹脂フィルム30を配置した後に、加熱・加圧して、プリント配線板10のバンプ13〜15とICチップ20のバンプ22,23を接合するとともにフィルム30を溶融してICチップ20とプリント配線板10との間を樹脂40(図3参照)で封止する。
【0016】
ここで、プリント配線板10の金バンプ部に配したC−H結合解離エネルギーの小さい炭化水素化合物(膜16)が介在されていることにより、電極表面の酸化膜を還元して活性な金属表面を界面に形成させながら接合することができる。詳しくは、図7に示すように、炭化水素化合物(膜16)を加熱することにより、炭化水素化合物が熱分解されて、炭化水素化合物から水素が分離されたラジカルな状態となり、このラジカルな状態とされた炭化水素化合物によって金属の表面に形成された酸化膜を還元しつつ、金属(Cu等)の溶融によって両基板の接続部を構成する金属が接合される。つまり、酸化膜の還元によって酸化膜が破れて清浄な金属表面が露出し、濡れ性が良い状態で、図2の配線板10側のAu膜15の表面とICチップ20側のCu膜23の表面が接触し、さらに、Cu膜23の溶解に伴い、図3に示すように、ICチップ20側のCu膜23と配線板10側のAu膜15とが接合される。
【0017】
このように本比較例では、炭化水素化合物の膜16を加熱することにより、Cu膜23もしくはAu膜15表面の酸化膜を炭化水素化合物で還元しつつ、Cu膜23を溶融することによって両バンプを接合する。
【0018】
接合原理について本発明者らは種々の実験を行ったので、それを以下に説明する。
(i ).各種の炭化水素化合物溶液中に酸化銅を浸して加熱したときの水素及び水の発生量を検出した。この結果、水素の発生は確認されたが、水は検出されなかった。このため、酸化銅の還元は、水素によってなされたものではないことが確認された。
【0019】
(ii).各種の炭化水素化合物溶液中に酸化銅を浸して加熱したときの反応生成物を分析した。その結果、酸化された炭化水素化合物の存在が確認された(例えば、シクロオクタンの場合、シクロオクタノン及びシクロオクタノールの存在が確認された)。これにより、炭化水素化合物自身が酸化銅を還元している可能性があると考えた。
【0020】
(iii ).この(ii)の推論の真偽を確認するため、各種炭化水素化合物のC−H結合解離エネルギーと還元速度定数との関係を求めた。その結果を図8に示す。図8において横軸にC−H結合解離エネルギーΔHをとり、縦軸に還元速度定数をとり、サンプルとして、ジシクロペンタジエンとトリフェニルメタンとシクロオクタンとテトラメチルペンタデカンとエイコサンを用いた。ここで、還元速度定数とは、図9に示すように試料中に基板(銅端子を酸化済のもの)を入れ300℃で所定時間保持した際における銅表面の酸素を波長分散型X線分光分析法により定量(還元状態の定量)を行い、次式により求めたものである。
【0021】
還元速度定数k=(1−X/X1)/(t・X)
ただし、X1;初期酸化状態でのX線カウント数
X;時間が経過した段階でのX線カウント数
t;加熱時間(秒)
この結果、図8に示すように、C−H結合解離エネルギーが小さくなるほど、還元速度が上昇する関係があることが確認された。このため、ラジカルな状態となった炭化水素化合物によって酸化銅等が還元されていることが確認された。
【0022】
(iv).C−H結合解離エネルギーが比較的小さい各種物質を用いて、銅端子とハンダ被覆端子との接合を行ったところ、図10に示すように、C−H結合解離エネルギーが950kJ/mol以下の炭化水素化合物については、従来のフラックスと同等の接続面積率が得られ、十分な接続強度を確保できた(C−H結合解離エネルギーが小さいほど接続特性が良好である)。詳しくは、図10において横軸にC−H結合解離エネルギーΔHをとり、縦軸に接続面積率をとり、サンプルとして、ジヒドロアントラセンとジシクロペンタジエンとシクロオクタンとテトラメチルペンタデカンとエイコサンを用いた。ここで、接続面積率とは、長方形の接合部位における当該部位の短辺により正方形の観察窓を作り(想定し)、長方形の接合部位での最も接合が不良となっている領域に前述の観察窓を持っていき、この窓の内部における全面積に対する実際に接合が行われた面積の比率を求めたものである。その結果、フラックを用いた場合の接続面積率である「0.7」以上とするためにはC−H結合解離エネルギーが約950kJ/mol以下の物質を用いればよいことが分かった。
【0023】
以上のように、プリント配線板10のバンプ13〜15の表面に、C−H結合解離エネルギーが950J/mol以下の炭化水素化合物よりなる膜16を配置し、この膜16を両バンプ間に介在させた状態で加熱・加圧してバンプの接合および樹脂封止を行うようにした。よって、プリント配線板10の電極部に配したC−H結合解離エネルギーの小さい炭化水素化合物により、電極表面の酸化膜を還元して活性な金属表面を界面に形成させながら接合することができ、高い信頼性が得られる。
【0024】
さらに、上述の炭化水素化合物(16)は、加圧・加熱により熱可塑性樹脂フィルム30の表層部に浸透し、その表層部の弾性率を低下させる性質を有するため、熱可塑性樹脂フィルム30のプリント配線板10側の面全体を炭化水素化合物の膜16に当接させることにより、熱可塑性樹脂フィルム30とプリント配線板10との接着性を向上させることができる。
(実施の形態)
次に、実施の形態を図面に従って説明する。図4〜図6には、本実施形態におけるICチップの実装工程を示す。
【0025】
図4に示すように、プリント配線板(PWB)50において、絶縁基板51には導体パターン52が形成されている。導体パターン52でのICチップとの接合部(PWB端子部)においてはその上面に銅めっきによる突起(厚さ10〜50μm)53が形成され、その上部にはハンダめっき(厚さ2〜10μm)54が形成されている。このようにプリント配線板10のバンプとしてハンダバンプを用いている。
【0026】
また、ICチップ60において、シリコンチップ61には金属突起62が形成され、金属突起62は、金よりなる膜63にて被覆されている。このようにしてバンプが形成されている。
【0027】
一方、熱可塑性樹脂フィルム70としてPEEK−PEIフィルム(ポリエーテルエーテルケトンとポリエーテルイミドの混合物)を用いており、両面にはアルカン類よりなる膜71がコーティングされている。膜71の材料としてのアルカン類は、エイコサン、テトラデカンを用いる。この熱可塑性樹脂フィルム70および膜71においてプリント配線板50のバンプ53,54およびICチップ60のバンプ62,63に対応する位置に貫通孔72が形成されている。
【0028】
そして、図5に示すように、プリント配線板(PWB)50の上に熱可塑性樹脂フィルム70を介してICチップ60を位置させる。このとき、プリント配線板50のバンプと熱可塑性樹脂フィルム70の穴位置とICチップ60のバンプとを一致させて重ねる。
【0029】
この状態で、チップ表面に加熱ツール(ヒータヘッドH)を押し当て、プリント配線板50と熱可塑性樹脂フィルム70の界面の温度が300〜330℃になるように加熱・加圧する(圧力0.05〜0.5MPa、1〜15秒)。このように熱圧着すると、図6に示すように、ICチップ60の電極とプリント配線板50のハンダバンプとが接合するとともに、熱可塑性樹脂フィルム70が溶けて接着する。つまり、図5でプリント配線板50とICチップ60との間に熱可塑性樹脂フィルム70を配置した後に、加熱・加圧して、プリント配線板50のバンプ53,54とICチップ60のバンプ62,63を接合するとともにフィルム70を溶融してICチップ60とプリント配線板50との間を樹脂80(図6参照)で封止する。
【0030】
ここで、PEEK−PEIフィルム70の両面には、アルカン類(エイコサン、テトラデカン等)よりなる膜71を介在させているので、PEEK−PEIとの界面で、アルカン類がPEEK−PEIに浸透して弾性率が下がることにより、接着力が向上する。
【0031】
以下、実験を行ったので、その結果について説明する。
図11には、接着界面温度を変えていったときの接着強度の測定結果を示す。サンプルには、アルカン膜(C1430)を用いたものと、用いなかったものを使用している。
【0032】
この図11から、270℃で接着する場合には、アルカン膜を用いることにより、1.5N/mmの接着強度を得ることができることが分かる。換言すると、同じ接着強度を得る場合には、より低い温度での加熱でよいことになる。具体的には、図11において縦軸の接着強度を1.5N/mmとしたい場合において、アルカン膜を用いない場合には約300℃に加熱する必要があるが、アルカン膜を用いると約270℃に加熱するだけでよいことになる。
【0033】
以上のように、熱可塑性樹脂フィルム70の両面にアルカン類よりなる膜71を配置し、この膜71をチップ・配線板間に介在させた状態で加熱・加圧してバンプの接合および樹脂封止を行うようにした。よって、フィルム70の表面はアルカン類を介在させているので、PEEK−PEIとの界面で、アルカン類がPEEK−PEIに浸透して弾性率が下がることにより、接着力が向上し、高い信頼性が得られる。
【図面の簡単な説明】
【図1】 比較例におけるICチップの実装方法の説明図。
【図2】 ICチップの実装方法の説明図。
【図3】 ICチップの実装方法の説明図。
【図4】 施の形態におけるICチップの実装方法の説明図。
【図5】 ICチップの実装方法の説明図。
【図6】 ICチップの実装方法の説明図。
【図7】 アルカンによるCuO還元反応を説明するための図。
【図8】 C−H結合解離エネルギーと還元速度定数の関係を示す図。
【図9】 CuO還元反応速度の測定方法を説明するための図。
【図10】 C−H結合解離エネルギーと接続面積率の関係を示す図。
【図11】 接着強度の測定結果を示す図。
【符号の説明】
10…プリント配線板、11…絶縁基板、12…導体パターン、13…突起、14…ニッケルめっき、15…金めっき、16…炭化水素化合物よりなる膜、20…ICチップ、21…シリコンチップ、22…金属突起、23…銅よりなる膜、30…樹脂フィルム、31…貫通孔、50…プリント配線板、51…絶縁基板、52…導体パターン、53…突起、54…ハンダめっき、60…ICチップ、61…シリコンチップ、62…金属突起、63…金よりなる膜、70…熱可塑性樹脂フィルム、71…アルカン類よりなる膜、72…貫通孔。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC chip mounting method.
[0002]
[Prior art]
Conventionally, an IC chip was mounted on a printed wiring board (PWB) by the flip chip method, but a resin called underfill was injected under the chip to improve the fatigue life of the joint and ensure reliability. I have done it. As an alternative method, there is a technique in which a resin film is sandwiched between a substrate and a chip to bond the substrate and the chip with a resin (Japanese Patent Laid-Open No. 9-64237 and Japanese Patent No. 2812238). etc). However, there is a demand for enhancing the bonding strength between the electrodes and improving the sealing property (resin adhesion) between the chip and the printed wiring board.
[0003]
[Problems to be solved by the invention]
An object of the present invention is to provide a more reliable IC chip mounting method.
[0004]
[Means for Solving the Problems]
As described in claim 1, after placing a thermoplastic resin film having through holes at positions corresponding to the bumps between the printed wiring board having bumps and the IC chip having bumps, heating and pressurizing are performed. Te, the time of resin sealing between by the film is melted together with bonding the bump and the IC chip bumps printed circuit board IC chip and the printed wiring board, consisting of alkanes to both sides of the thermoplastic resin film the membrane is arranged, it performs a bonding and resin sealing bump the film heated and pressed while being interposed between the chip and wiring board. Then, since alkanes are interposed on the surface of the film, alkanes penetrate into the thermoplastic resin at the interface with the thermoplastic resin film and the elastic modulus decreases, thereby improving the adhesive force and high reliability. Is obtained.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
( Comparative example )
Hereinafter, prior to the form of implementation embodying the present invention will be described with reference to the accompanying drawings comparative example of the same embodiment.
[0011]
1 to 3 show an IC chip mounting process in this comparative example .
As shown in FIG. 1, in a printed wiring board (PWB) 10, a conductive pattern 12 is formed on an insulating substrate 11. In the joint portion (PWB terminal portion) of the conductor pattern 12 with the IC chip, a protrusion (thickness 10 to 50 μm) 13 by copper plating is formed on the upper surface, and nickel plating (thickness 1 to 5 μm) is formed on the upper portion. 14 and gold plating (thickness 1 to 5 μm) 15 are formed. Thus, gold bumps are used as the bumps of the printed wiring board 10. Furthermore, in this example, a film 16 made of a hydrocarbon compound having a C—H bond dissociation energy of 950 kJ / mol or less is formed on the upper surface of the wiring board including the gold bump portion. Specifically, a film made of dicyclopentadiene, tetramethylpentadecane, or the like is used.
[0012]
In the IC chip 20, a metal protrusion 22 is formed on the silicon chip 21, and the metal protrusion 22 is covered with a film 23 made of copper (or aluminum or gold). In this way, bumps are formed.
[0013]
On the other hand, a PEEK-PEI film (a mixture of polyetheretherketone and polyetherimide) is used as the thermoplastic resin film 30 and corresponds to the bumps 13 to 15 of the printed wiring board 10 and the bumps 22 and 23 of the IC chip 20. A through hole 31 is formed at the position.
[0014]
Then, as shown in FIG. 2, the IC chip 20 is aligned and stacked on the printed wiring board (PWB) 10 via the PEEK-PEI film 30. That is, the bumps of the printed wiring board 10 and the hole positions of the PEEK-PEI film 30 and the bumps of the IC chip 20 are overlapped.
[0015]
In this state, a heating tool (heater head H) is pressed against the chip surface and heated and pressurized so that the temperature at the interface between the printed wiring board 10 and the PEEK-PEI film 30 is 300 to 330 ° C. (pressure 0.05) -0.5 MPa, 1-15 seconds). When thermocompression bonding is performed in this manner, as shown in FIG. 3, the electrodes of the IC chip 20 and the gold bumps of the printed wiring board 10 are bonded, and the PEEK-PEI film 30 is melted and bonded. That is, after the thermoplastic resin film 30 is disposed between the printed wiring board 10 and the IC chip 20 in FIG. 2, heating and pressurization are performed, so that the bumps 13 to 15 of the printed wiring board 10 and the bumps 22 of the IC chip 20. 23 and the film 30 are melted to seal the gap between the IC chip 20 and the printed wiring board 10 with a resin 40 (see FIG. 3).
[0016]
Here, a hydrocarbon compound (film 16) having a small C—H bond dissociation energy disposed on the gold bump portion of the printed wiring board 10 is interposed, so that the oxide film on the electrode surface is reduced and the active metal surface is reduced. Can be bonded while forming at the interface. Specifically, as shown in FIG. 7, by heating the hydrocarbon compound (film 16), the hydrocarbon compound is thermally decomposed into a radical state in which hydrogen is separated from the hydrocarbon compound, and this radical state. While the oxide film formed on the surface of the metal is reduced by the hydrocarbon compound, the metal constituting the connection portion of both substrates is joined by melting of the metal (Cu or the like). That is, the oxide film is broken by the reduction of the oxide film, and a clean metal surface is exposed, and the wettability is good, and the surface of the Au film 15 on the wiring board 10 side and the Cu film 23 on the IC chip 20 side in FIG. As shown in FIG. 3, the Cu film 23 on the IC chip 20 side and the Au film 15 on the wiring board 10 side are bonded together as the surface comes into contact with the Cu film 23 and melts.
[0017]
As described above, in this comparative example , both bumps are obtained by heating the hydrocarbon compound film 16 to melt the Cu film 23 while reducing the oxide film on the surface of the Cu film 23 or the Au film 15 with the hydrocarbon compound. Join.
[0018]
The inventors have conducted various experiments on the bonding principle, which will be described below.
(I). The generation amounts of hydrogen and water were detected when copper oxide was immersed in various hydrocarbon compound solutions and heated. As a result, generation of hydrogen was confirmed, but water was not detected. For this reason, it was confirmed that reduction of copper oxide was not performed by hydrogen.
[0019]
(Ii). Reaction products when copper oxide was immersed in various hydrocarbon compound solutions and heated were analyzed. As a result, the presence of an oxidized hydrocarbon compound was confirmed (for example, in the case of cyclooctane, the presence of cyclooctanone and cyclooctanol was confirmed). Thereby, it was considered that the hydrocarbon compound itself may be reducing copper oxide.
[0020]
(Iii). In order to confirm the truth of the inference of (ii), the relationship between the C—H bond dissociation energy and the reduction rate constant of various hydrocarbon compounds was determined. The result is shown in FIG. In FIG. 8, the horizontal axis represents the C—H bond dissociation energy ΔH, the vertical axis represents the reduction rate constant, and dicyclopentadiene, triphenylmethane, cyclooctane, tetramethylpentadecane, and eicosane were used as samples. Here, as shown in FIG. 9, the reduction rate constant is the wavelength dispersive X-ray spectroscopy of oxygen on the copper surface when a substrate (with the copper terminal oxidized) is placed in a sample and held at 300 ° C. for a predetermined time. Quantification (reduction state quantification) is performed by an analytical method, and is obtained by the following formula.
[0021]
Reduction rate constant k = (1−X / X1) / (t · X)
However, X1; X-ray count number X in the initial oxidation state; X-ray count number t after time; heating time (seconds)
As a result, as shown in FIG. 8, it was confirmed that there is a relationship in which the reduction rate increases as the C—H bond dissociation energy decreases. For this reason, it was confirmed that the copper oxide etc. were reduced with the hydrocarbon compound which became the radical state.
[0022]
(Iv). When a copper terminal and a solder-coated terminal were joined using various substances having a relatively low C—H bond dissociation energy, as shown in FIG. 10, carbonization with a C—H bond dissociation energy of 950 kJ / mol or less was performed. About a hydrogen compound, the connection area ratio equivalent to the conventional flux was obtained, and sufficient connection strength was ensured (The connection characteristic is so favorable that CH bond dissociation energy is small). Specifically, in FIG. 10, the horizontal axis represents C—H bond dissociation energy ΔH, the vertical axis represents the connection area ratio, and dihydroanthracene, dicyclopentadiene, cyclooctane, tetramethylpentadecane, and eicosane were used as samples. Here, the connection area ratio refers to the above-mentioned observation in the region where the rectangular junction part has the poorest junction at the rectangular junction part (assuming that a square observation window is created). Taking the window, the ratio of the area where bonding was actually performed to the total area inside the window was obtained. As a result, it was found that may be used in the following materials C-H bond dissociation energy of about 950kJ / mol in order to "0.7" or more, which is a connection area ratio in the case of using the fluxes.
[0023]
As described above, the surface of the bump 13 to 15 of the printed wiring board 10, place the film 16 C-H bond dissociation energy is from 950 k J / mol or less of hydrocarbon compounds, among the film 16 both bumps The bumps were joined and the resin was sealed by heating and pressurizing in the state of being interposed. Therefore, by using a hydrocarbon compound having a small C—H bond dissociation energy disposed on the electrode portion of the printed wiring board 10, it is possible to bond while reducing the oxide film on the electrode surface and forming an active metal surface at the interface, High reliability is obtained.
[0024]
Furthermore, since the above-mentioned hydrocarbon compound (16) has the property of penetrating into the surface layer portion of the thermoplastic resin film 30 by pressurization and heating and reducing the elastic modulus of the surface layer portion, the printing of the thermoplastic resin film 30 is performed. Adhesion between the thermoplastic resin film 30 and the printed wiring board 10 can be improved by bringing the entire surface on the wiring board 10 side into contact with the hydrocarbon compound film 16.
(In the form of implementation)
It will now be described with reference to the drawings in the form of implementation. 4 to 6 show an IC chip mounting process according to the present embodiment.
[0025]
As shown in FIG. 4, in a printed wiring board (PWB) 50, a conductive pattern 52 is formed on an insulating substrate 51. At the joint portion (PWB terminal portion) of the conductor pattern 52 with the IC chip, a protrusion (thickness 10 to 50 μm) 53 is formed on the upper surface thereof, and solder plating (thickness 2 to 10 μm) is formed thereon. 54 is formed. Thus, solder bumps are used as the bumps of the printed wiring board 10.
[0026]
In the IC chip 60, a metal protrusion 62 is formed on the silicon chip 61, and the metal protrusion 62 is covered with a film 63 made of gold. In this way, bumps are formed.
[0027]
On the other hand, a PEEK-PEI film (a mixture of polyetheretherketone and polyetherimide) is used as the thermoplastic resin film 70, and a film 71 made of alkanes is coated on both surfaces. As the alkanes as the material of the film 71, eicosane and tetradecane are used. Through holes 72 are formed at positions corresponding to the bumps 53 and 54 of the printed wiring board 50 and the bumps 62 and 63 of the IC chip 60 in the thermoplastic resin film 70 and the film 71.
[0028]
Then, as shown in FIG. 5, the IC chip 60 is positioned on the printed wiring board (PWB) 50 via the thermoplastic resin film 70. At this time, the bumps of the printed wiring board 50, the hole positions of the thermoplastic resin film 70, and the bumps of the IC chip 60 are made to coincide with each other.
[0029]
In this state, a heating tool (heater head H) is pressed against the chip surface and heated and pressurized so that the temperature at the interface between the printed wiring board 50 and the thermoplastic resin film 70 is 300 to 330 ° C. (pressure 0.05) -0.5 MPa, 1-15 seconds). When thermocompression bonding is performed in this manner, the electrodes of the IC chip 60 and the solder bumps of the printed wiring board 50 are joined and the thermoplastic resin film 70 is melted and bonded as shown in FIG. That is, in FIG. 5, after the thermoplastic resin film 70 is disposed between the printed wiring board 50 and the IC chip 60, the bumps 53 and 54 of the printed wiring board 50 and the bumps 62 of the IC chip 60 are heated and pressed. 63 is joined and the film 70 is melted to seal between the IC chip 60 and the printed wiring board 50 with a resin 80 (see FIG. 6).
[0030]
Here, since the film 71 made of alkanes (eicosane, tetradecane, etc.) is interposed on both sides of the PEEK-PEI film 70, the alkanes penetrate into the PEEK-PEI at the interface with the PEEK-PEI. Adhesive force improves because the elastic modulus decreases.
[0031]
Hereinafter, since the experiment was performed, the result will be described.
FIG. 11 shows the measurement results of the adhesive strength when the adhesive interface temperature is changed. Samples with and without an alkane membrane (C 14 H 30 ) are used.
[0032]
From FIG. 11, it can be seen that, when bonding is performed at 270 ° C., an adhesive strength of 1.5 N / mm can be obtained by using an alkane film. In other words, in order to obtain the same adhesive strength, heating at a lower temperature is sufficient. Specifically, in the case where it is desired to set the adhesive strength on the vertical axis in FIG. 11 to 1.5 N / mm, it is necessary to heat to about 300 ° C. when the alkane film is not used, but when the alkane film is used, about 270 is used. All you need to do is heat to ° C.
[0033]
As described above, the film 71 made of alkanes is disposed on both surfaces of the thermoplastic resin film 70, and this film 71 is heated and pressed in a state of being interposed between the chip and the wiring board to bond the bumps and seal the resin. To do. Therefore, since the surface of the film 70 contains alkanes, the alkanes penetrate into the PEEK-PEI at the interface with the PEEK-PEI and the elastic modulus is lowered, thereby improving the adhesive force and high reliability. Is obtained.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an IC chip mounting method in a comparative example .
FIG. 2 is an explanatory diagram of an IC chip mounting method.
FIG. 3 is an explanatory diagram of an IC chip mounting method.
Figure 4 is an explanatory view of an IC chip mounting method in the form of implementation.
FIG. 5 is an explanatory diagram of an IC chip mounting method.
FIG. 6 is an explanatory diagram of an IC chip mounting method.
FIG. 7 is a diagram for explaining a CuO reduction reaction by alkane.
FIG. 8 is a graph showing the relationship between C—H bond dissociation energy and reduction rate constant.
FIG. 9 is a diagram for explaining a method of measuring a CuO reduction reaction rate.
FIG. 10 is a diagram showing a relationship between C—H bond dissociation energy and a connection area ratio.
FIG. 11 is a diagram showing a measurement result of adhesive strength.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Printed wiring board, 11 ... Insulating substrate, 12 ... Conductor pattern, 13 ... Protrusion, 14 ... Nickel plating, 15 ... Gold plating, 16 ... Film | membrane consisting of a hydrocarbon compound, 20 ... IC chip, 21 ... Silicon chip, 22 ... Metal projection, 23 ... Copper film, 30 ... Resin film, 31 ... Through hole, 50 ... Printed wiring board, 51 ... Insulating substrate, 52 ... Conductor pattern, 53 ... Projection, 54 ... Solder plating, 60 ... IC chip , 61 ... Silicon chip, 62 ... Metal projection, 63 ... Film made of gold, 70 ... Thermoplastic resin film, 71 ... Film made of alkanes, 72 ... Through-hole.

Claims (2)

バンプ(,54)を有するプリント配線板(0)とバンプ(2,3)を有するICチップ(0)との間に、前記バンプ(53,542,3)に対応する位置に貫通孔(72)を設けた熱可塑性樹脂フィルム(0)を配置した後に、加熱・加圧して、プリント配線板(0)のバンプ(,54)とICチップ(0)のバンプ(2,3)を接合するとともに前記フィルム(0)を溶融させてICチップ(0)とプリント配線板(0)との間を樹脂封止するICチップの実装方法であって、
前記熱可塑性樹脂フィルム(70)の両面にアルカン類よりなる膜(71)を配置し、この膜(71)をチップ・配線板間に介在させた状態で加熱・加圧して前記バンプの接合および樹脂封止を行うようにしたことを特徴とするICチップの実装方法。
Between the bumps (5 3, 54) IC chip (6 0) with the printed circuit board (5 0) bumps (6 2, 6 3) with the bump (53, 54, 6 2, 6 3 after placing a thermoplastic resin film (7 0) having a through hole (72) in a position corresponding to), heating and pressurizing, the printed circuit board (5 0) of the bump (5 3, 54) IC sealed with resin between the chip (6 0) of the bump (6 2, 6 3) IC chip (6 0) by melting the film (7 0) with bonding the printed circuit board (5 0) An IC chip mounting method,
Place the membrane (71) consisting of alkanes on both sides of the thermoplastic resin film (70), bonding and the bump this membrane (71) a heating and pressurizing in a state of being interposed between the chip and wiring board An IC chip mounting method characterized by resin sealing.
前記アルカン類は、エイコサンまたはテトラデカンであることを特徴とする請求項1に記載のICチップの実装方法。 2. The IC chip mounting method according to claim 1, wherein the alkane is eicosane or tetradecane .
JP2001028748A 2001-02-05 2001-02-05 IC chip mounting method Expired - Fee Related JP4385529B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001028748A JP4385529B2 (en) 2001-02-05 2001-02-05 IC chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001028748A JP4385529B2 (en) 2001-02-05 2001-02-05 IC chip mounting method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009184508A Division JP4935870B2 (en) 2009-08-07 2009-08-07 IC chip mounting method

Publications (2)

Publication Number Publication Date
JP2002231764A JP2002231764A (en) 2002-08-16
JP4385529B2 true JP4385529B2 (en) 2009-12-16

Family

ID=18893196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001028748A Expired - Fee Related JP4385529B2 (en) 2001-02-05 2001-02-05 IC chip mounting method

Country Status (1)

Country Link
JP (1) JP4385529B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4595471B2 (en) * 2004-09-30 2010-12-08 住友電気工業株式会社 Conductive paste and method for producing multilayer printed wiring board using the same

Also Published As

Publication number Publication date
JP2002231764A (en) 2002-08-16

Similar Documents

Publication Publication Date Title
US6646355B2 (en) Structure comprising beam leads bonded with electrically conductive adhesive
JP4605155B2 (en) Semiconductor device and manufacturing method thereof
US20060061974A1 (en) Solder foil semiconductor device and electronic device
JP5066935B2 (en) Method for manufacturing electronic component and electronic device
KR19990076497A (en) Semiconductor devices, lead patterned substrates, and electronic devices and manufacturing methods thereof
JP2005520333A (en) Multilayer substrate stacking technology
CN102208388A (en) Semiconductor device and semiconductor device manufacturing method
JP2007184381A (en) Flip chip mounting circuit board, its manufacturing method, semiconductor device, and its manufacturing method
JP4136844B2 (en) Electronic component mounting method
JP3356649B2 (en) Semiconductor device and manufacturing method thereof
JP4385529B2 (en) IC chip mounting method
JP4051570B2 (en) Manufacturing method of semiconductor device
US7750484B2 (en) Semiconductor device with flip-chip connection that uses gallium or indium as bonding material
JP4935870B2 (en) IC chip mounting method
KR101115705B1 (en) Method of forming metallic bump and seal for semiconductor device
JP2002232123A (en) Manufacturing method of composite circuit substrate
JP2000022300A (en) Wiring board and electronic unit
US6769598B2 (en) Method of connecting circuit boards
Baldwin et al. Gallium alloy interconnects for flip-chip assembly applications
JPH11135567A (en) Anisotropic conductive film and manufacture of semiconductor device
JP2001185843A (en) Metal bonding method
JPS63168028A (en) Fine connection structure
JPH10308415A (en) Method for mounting electrode, electronic component, electronic device, and electronic component
CN104882429A (en) Thin NiB Or CoB Capping Layer For Non-noble Metal Bond Pads
JP2003152023A (en) Connecting structure for semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070329

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090317

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090515

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090609

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090807

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090908

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090921

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121009

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121009

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121009

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131009

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131009

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees