JP4383478B2 - memory - Google Patents

Description

  The present invention relates to a memory, and more particularly to a memory including a memory cell including a diode.

  Conventionally, as an example of a memory, a cross-point type mask ROM (hereinafter referred to as a diode ROM) in which a plurality of memory cells each including a diode are arranged in a matrix is known (see, for example, Patent Document 1).

  In the conventional diode ROM disclosed in Patent Document 1, a plurality of word lines and a plurality of bit lines arranged so as to cross the plurality of word lines and adjacent to each other with a predetermined interval are provided. A plurality of memory cells made of diodes arranged at positions where the word lines and the bit lines intersect with each other, and a sense amplifier connected to the bit lines and for determining data read from the selected memory cells. Yes. In this diode ROM, the sense amplifier detects the current flowing from the sense amplifier to the word line via the bit line and the diode, thereby determining the data of the memory cell. The cathode of each diode constituting each memory cell connected to each word line is constituted by a common conductive layer (impurity region).

JP 2007-5580 A

  However, in the conventional diode ROM disclosed in Patent Document 1, the distance of the conductive layer through which the current flowing from each bit line to the end of the word line passes is different for each bit line. For this reason, when the distance of the conductive layer between the bit line and the end of the word line is short, the cell current increases, and the distance of the conductive layer between the bit line and the end of the word line is long. In this case, the cell current becomes small. Therefore, when the distance of the conductive layer between the bit line and the end of the word line is short, a large current flows through the bit line. For example, in a memory cell composed of multiple bits, there is an inconvenience that a large current flows as a whole when a bit line through which a large current flows in each bit is selected. As a result, there is a problem that current consumption (power consumption) increases as a whole.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory capable of suppressing an increase in current consumption (power consumption). It is.

  In order to achieve the above object, a memory according to the present invention is provided to extend in parallel to a plurality of word lines, a plurality of bit lines arranged to cross the plurality of word lines, and the word lines. A conductive layer, a memory cell disposed at a position where the conductive layer and the bit line intersect, and a plurality of backing wirings provided for each predetermined number of memory cells and connecting the word line and the conductive layer. In the first block and the second block in which a predetermined number of bit lines sandwiched between adjacent backing wirings are respectively arranged, end portions of the first block bit lines of the first block that are simultaneously selected at the time of data reading are The reference position and the position relative to the end of the second block of the bit line of the second block are different.

  In the present invention, as described above, in the first block and the second block, the position of the bit line of the first block that is simultaneously selected at the time of data reading and the bit of the second block The position is determined so that the position relative to the end of the second block of the line is different. Thereby, for example, in the case where the memory cell includes a diode and the cathode of the diode included in each of the memory cells connected to each conductive layer is configured by a common conductive layer, the first block is the first block. The data of the bit line located at the end of the second block can be read out, and the data of the bit line located near the center of the second block can be read out in the second block. In this case, the bit line located at the end portion has a small distance of the conductive layer between the memory cell connected to the bit line and the backing wiring, so that a large current flows and the bit line located near the center portion is Since the distance of the conductive layer between the memory cell and the backing wiring is large, a small current flows. If the first block reads out the data of the bit line located at the end portion and the second block reads out the data of the bit line located near the center portion, both the first block and the second block are configured. Unlike the case where data is read from the bit line located at the end in FIG. 5, a large current and a small current flow through the bit lines read simultaneously. Thereby, the magnitude | size of the electric current which flows can be made smaller than the case where big electric current flows. As a result, an increase in current consumption (power consumption) can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a cross-point type mask ROM (hereinafter referred to as a diode ROM) according to the first embodiment of the present invention.

  As shown in FIG. 1, the diode ROM according to the first embodiment includes an address input circuit 1, a row decoder 2, a column decoder 3, a sense amplifier 4, an output circuit 5, and a memory cell array region 6. Yes. The address input circuit 1 is configured to output address data to the row decoder 2 and the column decoder 3 when a predetermined address is input from the outside. The row decoder 2 is connected to a word line (WL) 7. A conductive layer 8 is provided so as to extend in parallel with the word line 7. The word line 7 and the conductive layer 8 are connected by a backing wiring 9 provided for each of eight memory cells 11 described later. The row decoder 2 receives the address data from the address input circuit 1, selects the word line 7 corresponding to the input address data, and sets the potential of the word line 7 to the L level (GND = 0V). And the potentials of the word lines 7 other than the selected word line 7 are set to the H level (Vcc).

  The column decoder 3 is connected to a plurality of bit lines (BL) 10 arranged so as to be orthogonal to the word lines 7. Further, eight bit lines 10 (10a to 10h, 10i to 10p) are sandwiched between adjacent backing wirings 9. A region where the plurality of bit lines 10a to 10h sandwiched between the backing wirings 9 is arranged is a first block, and a region where the plurality of bit lines 10i to 10p is arranged is a second block.

  In the memory cell array region 6, a plurality of memory cells 11 are arranged in a matrix. The plurality of memory cells 11 are respectively arranged at the intersections of the plurality of conductive layers 8 and the bit lines 10 arranged so as to be orthogonal to each other. In the memory cell array region 6, a memory cell 11 including a diode 12 whose anode is connected to the bit line 10 and a memory cell 11 including a diode 12 whose anode is not connected to the bit line 10 are provided. .

  The column decoder 3 is configured to connect the selected bit line 10 and the sense amplifier 4 via a p-type transistor 13. A wiring 14 is connected to the gate of each transistor 13. The wiring 14 is an example of the “first wiring” in the present invention. The column decoder 3 receives the address data from the address input circuit 1 and selects the bit line 10 corresponding to the input address data. Here, in the first embodiment, the gate of the transistor 13 connected to the bit line 10a included in the first block and the gate of the transistor 13 connected to the bit line 10m included in the second block are the same. It is connected to the wiring 14. The bit line 10a is disposed at the end in the first block, and the bit line 10m is disposed near the center in the second block.

  The sense amplifier 4 detects a current flowing through the bit line 10 selected by the column decoder 3 and outputs an H level signal when a current of a predetermined current or more flows through the selected bit line 10. When a current less than a predetermined current flows through the selected bit line 10, an L level signal is output. The output circuit 5 is configured to output a signal to the outside when the output of the sense amplifier 4 is input.

  Next, the operation of the diode ROM according to the first embodiment will be described with reference to FIG.

  First, a predetermined address is input to the address input circuit 1. As a result, address data corresponding to the input address is output from the address input circuit 1 to the row decoder 2 and the column decoder 3, respectively. Then, by decoding the address data by the row decoder 2, a predetermined word line 7 corresponding to the address data is selected. The potential of the selected word line 7 is lowered to L level (GND), and the potential of the unselected word line 7 is set to H level (Vcc).

  On the other hand, in the column decoder 3 to which the address data is input from the address input circuit 1, a predetermined bit line 10 corresponding to the input address data is selected, and the selected bit line 10 is connected to the sense amplifier 4. Is done. Then, a potential close to Vcc is supplied from the sense amplifier 4 to the selected bit line 10. The anode of the diode 12 of the selected memory cell 11 located at the intersection of the conductive layer 8 provided so as to extend with respect to the selected word line 7 and the selected bit line 10 is connected to the bit line 10. When connected, a current flows from the sense amplifier 4 to the word line 7 via the bit line 10 and the diode 12. At this time, the sense amplifier 4 detects that a predetermined current or more flows through the bit line 10 and outputs an H level signal. The output circuit 5 receives the output signal of the sense amplifier 4 and outputs an H level signal to the outside.

  If the anode of the diode 12 of the selected memory cell 11 located at the intersection of the selected word line 7 and the selected bit line 10 is not connected to the bit line 10, the bit line 10 to the word line No current flows to 7 In this case, the sense amplifier 4 detects that no current flows and outputs an L level signal. The output circuit 5 receives the output signal of the sense amplifier 4 and outputs an L level signal to the outside.

  Here, when a signal is input to the wiring 14 and the transistor 13 is turned on, the bit lines 10 included in the first block and the second block are selected one by one. The bit lines 10 included in the first block are sequentially selected from the bit line 10a located at one end of the first block to the bit line 10h located at the other end. In the first embodiment, in the second block, when the bit line 10a at one end of the first block is selected, the bit line 10m located near the center of the second block is selected. Thereafter, the bit lines 10n to 10p are sequentially selected. When the bit line 10e near the center of the first block is selected, the bit line 10i located at one end of the second block is selected. Thereafter, the bit lines 10j to 10l are sequentially selected toward the central portion of the second block. As described above, in the first embodiment, when the bit line 10 located on the end side of the first block is selected, the bit line 10 located on the center side is selected in the second block. When the bit line 10 located on the center side of the first block is selected, the bit line 10 located on the end side is selected in the second block.

  In the first embodiment, as described above, the data of the bit line 10 located on the end side of the first block and the data of the bit line 10 located on the center side of the second block are read simultaneously. By doing so, the bit line 10 on the end side with a large amount of flowing current and the bit line 10 on the central side with a small amount of flowing current can be called simultaneously. For this reason, unlike the case where data is read from the bit line 10 located at the end in both the first block and the second block, a large current and a small current flow through the bit line 10 that is read simultaneously. The amount of flowing current can be made smaller than when flowing. As a result, an increase in current consumption (power consumption) can be suppressed.

  In the first embodiment, as described above, the data of the bit line 10a located at the end of the first block and the data of the bit line 10m located near the center of the second block are read simultaneously. Constitute. Thus, unlike the case where data is read from the bit line 10 located at the end in both the first block and the second block, the amount of current that flows more easily than when a large current flows through the bit lines 10 that are read simultaneously. Can be reduced in size.

  In the first embodiment, as described above, the wiring 14 is connected to the first block sandwiched by the backing wiring 9 when the bit lines 10 of the first block and the second block are simultaneously selected at the time of data reading. Among the transistors 13 connected to each of the plurality of bit lines 10, the transistor 13 disposed on the end side is turned on, and each of the plurality of bit lines 10 in the second block sandwiched between the backing wirings 9 is connected. Among the transistors 13 to be connected, the transistor 13 disposed in the vicinity of the central portion is configured to be turned on. As a result, since the bit line 10a having a large amount of flowing current and the bit line 10m having a small amount of flowing current can be simultaneously called, data is transferred from the bit line 10 located at the end in both the first block and the second block. Unlike the case of reading, the amount of current flowing can be easily made smaller than when large currents flow through the bit lines 10 read simultaneously.

(Second Embodiment)
FIG. 2 is a plan layout view showing a configuration of a cross-point type mask ROM (hereinafter referred to as a diode ROM) according to the second embodiment of the present invention. FIG. 3 is an enlarged view of the configuration of the diode ROM according to the second embodiment of the present invention. In the diode ROM of the second embodiment, unlike the first embodiment, 32 bit lines 31 are sandwiched between the backing wirings 30.

  As shown in FIG. 2, the diode ROM according to the second embodiment includes an address input circuit 21, a row decoder 22, a column decoder 23, sense amplifiers (SA) 24a to 24h, NAND circuits 25a and 25b, and an output. Circuits 26 a and 26 b and a memory cell array region 27 are provided. The sense amplifiers 24a, 24c, 24e and 24g are examples of the “first sense amplifier” of the present invention, and the sense amplifiers 24b, 24d, 24f and 24h are examples of the “second sense amplifier” of the present invention. It is. The address input circuit 21 is configured to output address data to the row decoder 22 and the column decoder 23 when a predetermined address is input from the outside. A word line 28 is connected to the row decoder 22. A conductive layer 29 is provided so as to extend in parallel with the word line 28. The word line 28 and the conductive layer 29 are connected by a backing wiring 30 provided for each of 16 memory cells 32 described later. The row decoder 22 receives the address data from the address input circuit 21, selects the word line 28 corresponding to the input address data, and sets the potential of the word line 28 to the L level (GND = 0V). And the potentials of the word lines 28 other than the selected word line 28 are set to the H level (Vcc).

  The column decoder 23 is connected to a plurality of bit lines 31 arranged so as to be orthogonal to the word lines 28. Further, the bit line 31 includes 32 bit lines 31 sandwiched between adjacent backing wirings 30.

  In the memory cell array region 27, a plurality of memory cells 32 are arranged in a matrix. The plurality of memory cells 32 are respectively arranged at the intersections of the conductive layers 29 and the bit lines 31 arranged to extend in parallel to the plurality of word lines 28 arranged to be orthogonal to each other. Yes. In the memory cell array region 27, a memory cell 32 including a diode 33 whose anode is connected to the bit line 31 and a memory cell 32 including a diode 33 whose anode is not connected to the bit line 31 are provided. .

  As shown in FIG. 3, the column decoder 23 receives the address data from the address input circuit 21 (see FIG. 2), and selects the bit line 31 corresponding to the input address data. The bit line 31 and one of the sense amplifiers 24 a to 24 h are connected via a p-type transistor 34. A wiring 35 is connected to the gate of each transistor 34. In addition, the plurality of bit lines 31 are configured to be sequentially selected from the bit line 31 located at one end to the bit line 31 located at the other end among the 16 adjacent bit lines 31.

  Further, as shown in FIG. 2, the 32 bit lines 31 sandwiched between the backing wirings 30 are connected to the sense amplifiers 24a to 24h, 16 pieces each. The sense amplifiers 24a to 24d are connected to the NAND circuit 25a, and the NAND circuit 25a is connected to the output circuit 26a. The sense amplifiers 24e to 24h are connected to the NAND circuit 25b, and the NAND circuit 25b is connected to the output circuit 26b. In this way, one output is obtained from the 64 bit lines 31 connected to the sense amplifiers 24a to 24d (sense amplifiers 24e to 24h). The area where the bit lines 31 connected to the sense amplifiers 24a (24c) and 24b (24d) are arranged is the first block, and the bit lines 31 connected to the sense amplifiers 24e (24g) and 24f (24h). The area where is placed is the second block.

  The sense amplifier 24a (24c) is connected to a plurality of bit lines 31 from the end of the first block toward the vicinity of the center among the bit lines 31 of the first block, and the sense amplifier 24b (24d). ) Is connected to a plurality of bit lines 31 from which data is read from the vicinity of the center of the first block toward the end. The sense amplifier 24e (24g) is connected to a plurality of bit lines 31 from the end of the second block toward the vicinity of the center among the bit lines 31 of the second block, and the sense amplifier 24f (24h). ) Is connected to a plurality of bit lines 31 from which data is read from the vicinity of the center of the second block toward the end.

  In addition, one ends of the sense amplifiers 24 a to 24 h are connected to the bit line 31 and to the wiring 36. The wiring 36 is an example of the “second wiring” in the present invention. Further, since the sense amplifier 24a (24b) and the sense amplifier 24f (24e) are connected by the same wiring 36, the sense amplifier 24a (24b) and the sense amplifier 24f (24e) are simultaneously selected. It is configured as follows. Further, the sense amplifier 24c (24d) and the sense amplifier 24h (24g) are connected by the same wiring 36, so that the sense amplifier 24c (24d) and the sense amplifier 24h (24g) are simultaneously selected. It is configured as follows.

  As described above, in the second embodiment, among the sense amplifiers 24a to 24d connected to the output circuit 26a, the bit line 31 reads data from the end portion of the first block toward the center portion. 24c), among the sense amplifiers 24e to 24h connected to the output circuit 26b, the connected bit line 31 reads data from the vicinity of the center portion of the second block toward the end portion thereof. The sense amplifier 24f (24h) Are selected at the same time. In the second embodiment, among the sense amplifiers 24a to 24d connected to the output circuit 26a, the bit line 31 is read from the vicinity of the central portion of the first block toward the end thereof. The sense amplifier 24b (24d) Among the sense amplifiers 24e to 24h connected to the output circuit 26b, the sense amplifier 24e (24g) from which the bit line 31 to be connected is read out from the end of the second block toward the center is simultaneously selected. It is configured to be.

  Next, the operation of the diode ROM according to the second embodiment will be described with reference to FIGS.

  First, a predetermined address is input to the address input circuit 21. As a result, address data corresponding to the input address is output from the address input circuit 21 to the row decoder 22 and the column decoder 23, respectively. Then, the address data is decoded by the row decoder 22, whereby a predetermined word line 28 corresponding to the address data is selected. Then, the potential of the selected word line 28 is lowered to the L level (GND), and the potential of the unselected word line 28 is set to the H level (Vcc).

  On the other hand, in the column decoder 23 to which the address data is input from the address input circuit 21, the transistor 34 whose gate is connected to the wiring 35 is turned on, whereby a predetermined bit line 31 corresponding to the input address data is set. Is selected and connected to one of the sense amplifiers 24a to 24h to which the selected bit line 31 is connected. Here, it is assumed that the bit line 31a of the first block connected to the sense amplifier 24a is selected. Next, a potential close to Vcc is supplied from the sense amplifier 24a to the selected bit line 31a. Then, when a signal is input from the wiring 36 connected to the sense amplifier 24a, the anode of the diode 33 of the selected memory cell 32 located at the intersection of the selected word line 28 and the selected bit line 31a. However, when it is connected to the bit line 31 a, a current flows from the sense amplifier 24 to the word line 28 via the bit line 31 a and the diode 33. At this time, the sense amplifier 24a detects that a predetermined current or more flows through the bit line 31a and outputs an H level signal. The output circuit 26a receives the output signal of the sense amplifier 24a via the NAND circuit 25a and outputs an H level signal to the outside.

  The bit line 31b connected to the same wiring 35 as the wiring 35 to which the bit line 31a is connected is selected simultaneously with the bit line 31a, and the same wiring 36 as the wiring 36 to which the sense amplifier 24a is connected. The sense amplifier 24f connected to is simultaneously selected with the sense amplifier 24a. As a result, when the anode of the diode 33 of the selected memory cell 32 located at the intersection of the selected word line 28 and the selected bit line 31b is connected to the bit line 31b, the sense amplifier 24 A current flows to the word line 28 via the bit line 31 b and the diode 33. At this time, the sense amplifier 24f detects that a predetermined current or more flows through the bit line 31b, and outputs an H level signal. The output circuit 26b receives the output signal of the sense amplifier 24f via the NAND circuit 25b and outputs an H level signal to the outside.

  When the anode of the diode 33 of the selected memory cell 32 located at the intersection of the selected word line 28 and the selected bit line 31a (31b) is not connected to the bit line 31a (31b), No current flows from the bit line 31a (31b) to the word line 28. In this case, the sense amplifier 24a (24f) detects that no current flows and outputs an L level signal. The output circuit 26a (25b) receives the output signal of the sense amplifier 24a (24f) via the NAND circuit 25a (25b) and outputs an L level signal to the outside.

  In the second embodiment, as described above, the diode ROM includes the sense amplifier 24a connected to the plurality of bit lines 31 from the end portion to the vicinity of the center portion of the bit lines 31 of the first block. (24c) and a sense amplifier 24f (24h) connected to a plurality of bit lines 31 from which data is read from the vicinity of the center toward the end of the bit lines 31 of the second block. . Thus, since the sense amplifier 24a (24c) and the sense amplifier 24f (24h) are simultaneously selected, the bit line 31 at the end of the first block with a large amount of flowing current and the center of the second block with a small amount of flowing current The bit line 31 in the vicinity of the unit can be called simultaneously. Therefore, unlike the case where data is read from the bit line located at the end in both the first block and the second block, the amount of current that flows is larger than when large currents flow through a plurality of bit lines 31 that are called simultaneously. Can be reduced. Thereby, it is possible to suppress an increase in current consumption (power consumption). Similarly, the diode ROM includes a sense amplifier 24b (24d) connected to a plurality of bit lines 31 from which data is read from the vicinity of the center toward the end of the bit lines 31 of the first block, and the second block. The bit line 31 includes a sense amplifier 24e (24g) connected to a plurality of bit lines 31 from which data is read from the end toward the vicinity of the center. Thus, since the sense amplifier 24b (24d) and the sense amplifier 24e (24g) are configured to be selected at the same time, the bit line 31 near the center of the first block with a small amount of flowing current and the amount of flowing current are Many bit lines 31 at the end of the second block can be called simultaneously. Therefore, unlike the case where data is read from the bit line located at the end in both the first block and the second block, the amount of current that flows is larger than when large currents flow through a plurality of bit lines 31 that are called simultaneously. Can be reduced. Of the sense amplifiers 24a to 24h, the sense amplifiers not selected are controlled in the sense amplifiers 24a to 24h so as to be separated from the bit line 31.

  In the second embodiment, the wiring 36 provided between the sense amplifiers 24 a to 24 h and the bit line 31 is provided as described above. The wiring 36 connects the sense amplifiers 24a, 24b, 24c, and 24d to the sense amplifiers 24f, 24e, 24h, and 24g, respectively. This makes it easy to simultaneously select the sense amplifiers connected to the bit line 31 at one end of the first block and the second block and the bit line 31 near the other central portion at the same time. it can.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first and second embodiments, the present invention is applied to the cross-point type mask ROM. However, the present invention is not limited to this, and a memory cell including a diode other than the cross-point type mask ROM is provided. It can be widely applied to memories.

  In the first and second embodiments, the example in which the backing wiring is arranged for each of the 8 and 32 bit lines has been described. However, the present invention is not limited to this, and 8 and 32 are provided. A backing wiring may be arranged for each bit line other than.

  In the first and second embodiments, the bit lines of the first block are sequentially selected from the end side toward the center side, and the bit lines of the second block are shifted from the center side to the end side. However, the present invention is not limited to this, and the bit line 10 of the first block shown in FIG. 1 is replaced with the bit lines 10b, 10a, 10c, 10d, 10f, 10e, 10g, and 10h. The bit lines 10 in the second block may be selected in the order of bit lines 10n, 10m, 10o, 10p, 10j, 10i, 10k, and 10l. That is, the bit line 10 of the first block is selected substantially from the end side toward the center side, and the bit line 10 of the second block is selected substantially from the center side toward the end side. May be.

1 is a circuit diagram showing a configuration of a cross-point type mask ROM according to a first embodiment of the present invention. FIG. 6 is a plan layout diagram illustrating a configuration of a cross-point type mask ROM according to a second embodiment of the present invention. It is an enlarged view of a configuration of a cross-point type mask ROM according to a second embodiment of the present invention.

Explanation of symbols

4 sense amplifier 5, 26a, 26b output circuit 7, 28 word line 8, 29 conductive layer 9, 30 backing wiring 10, 31 bit line 11, 32 memory cell 13, 34 transistor 14 wiring (first wiring)
24a, 24c, 24e, 24g Sense amplifier (first sense amplifier)
24b, 24d, 24f, 24h Sense amplifier (second sense amplifier)
36 Wiring (second wiring)

Claims (8)

Multiple word lines,
A plurality of bit lines arranged to intersect the plurality of word lines;
A conductive layer provided to extend parallel to the word line;
A memory cell disposed at a position where the conductive layer and the bit line intersect;
Provided for each of a predetermined number of the memory cells, and comprising a plurality of backing wirings connecting the word line and the conductive layer;
In the first block and the second block in which a predetermined number of the bit lines are respectively arranged, the positions of the bit lines of the first block that are simultaneously selected at the time of data reading with reference to the end of the first block; The memory is configured such that the position of the bit line of the second block is different from the position of the end of the second block as a reference. Multiple word lines,
A plurality of bit lines arranged to intersect the plurality of word lines;
A conductive layer provided to extend parallel to the word line;
A memory cell disposed at a position where the conductive layer and the bit line intersect;
Provided for each of a predetermined number of the memory cells, and comprising a plurality of backing wirings connecting the word line and the conductive layer;
In the plurality of first blocks and the plurality of second blocks, each of which a predetermined number of the bit lines are respectively arranged, the bit of the first block of the plurality of first blocks selected simultaneously when reading data The position on the basis of the end of the first block of the line is different from the position on the basis of the end of the second block of the bit line of one of the plurality of second blocks. Configured as a memory.   When a bit line arranged on the end side among the plurality of bit lines of the first block is selected, a bit line arranged on the center side among the plurality of bit lines of the second block is selected. The memory of claim 1 or 2, configured to be selected.   Arranged in the vicinity of the central portion of the bit lines on the center side of the second block when a bit line disposed on the end portion of the bit lines on the end portion side of the first block is selected. 4. The memory of claim 3, wherein the memory is configured to be selected. A sense amplifier connected to a predetermined number of the bit lines;
A transistor disposed between the bit line and the sense amplifier and connected to each of the bit lines;
A first wiring connected to the gate of the transistor,
The first wiring includes a transistor connected to each of the bit lines included in the first block when the bit lines of the first block and the second block are simultaneously selected at the time of reading data. The transistor disposed on the end side is turned on, and the transistor disposed on the center side among the transistors connected to each of the bit lines included in the second block is turned on. The memory according to claim 3 or 4, wherein the memory is configured to. A first sense amplifier connected to the plurality of bit lines included in the first block; and a second sense amplifier connected to the plurality of bit lines included in the second block;
The first sense amplifier is connected to the plurality of bit lines from which data is read substantially from the end side toward the vicinity of the central portion, and the second sense amplifier is substantially from the central portion side to the end portion side. Connected to the plurality of bit lines from which data is read out,
The memory according to claim 3, wherein the first sense amplifier and the second sense amplifier are configured to be selected simultaneously. A second wiring provided between the sense amplifier and the bit line;
The memory according to claim 6, wherein the second wiring is configured to connect the first sense amplifier and the second sense amplifier. A first output circuit and a second output circuit for outputting data output from the bit line;
A plurality of sense amplifiers having one end connected to a certain number of bit lines of the plurality of bit lines and the other end connected to the first output circuit or the second output circuit;
The plurality of sense amplifiers connected to the first output circuit are connected to bit lines arranged in the plurality of first blocks, and to the plurality of sense amplifiers connected to the second output circuit. Are connected to bit lines arranged in the plurality of second blocks,
In the sense amplifier, among the plurality of sense amplifiers connected to the first output circuit, the certain number of bit lines connected to the first sense amplifier are directed from the end of the first block toward the center. Among the plurality of sense amplifiers connected to the second output circuit, the fixed number of bit lines connected to the second sense amplifier are end-connected from the vicinity of the central portion of the second block. Data is read out
The memory according to claim 2, wherein the first sense amplifier and the second sense amplifier are configured to be selected simultaneously.

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