KR100960931B1 - Phase change random access memory and layout method of the same - Google Patents

Abstract

The present invention relates to a phase change memory device, comprising: a first active region electrically connected to each of the global word lines at an intersection point between bit lines in a cell array region and global word lines crossing the bit lines and the bit lines. Each of the phase change memory cells formed in a second voltage supply circuit, wherein a first voltage is supplied to any one of the bit lines, and a second voltage having a level lower than the first voltage level is supplied to the global word line crossing the bit line. A plurality of memory cell strings in which a phase change of a memory cell connected to the plurality is performed; And a phase change structure identical to that of the memory cells, each formed between the bit lines and the second active region electrically connected to a dummy line to which a third voltage having a level equal to or greater than the first voltage is supplied in the cell array region. And one or more dummy cell strings each including a plurality of dummy cells having a plurality of dummy cells, wherein the dummy cell strings are turned off by the third voltage supplied through the dummy lines.

Description

Phase change memory device and its layout method {PHASE CHANGE RANDOM ACCESS MEMORY AND LAYOUT METHOD OF THE SAME}

The present invention relates to a phase change memory device, and more particularly, to a phase change memory device including dummy cells and a layout method thereof.

In general, in a memory cell configuration of a phase change random access memory (PRAM), a cell array is repeatedly arranged of a memory cell string including diodes formed by selective epitaxial growth. It can be configured as.

That is, an 8-bit memory cell string may be arranged in one cell array in the global word line direction, and a global row decoding connected to the global X-decoder together with the 8-bit memory cell string in the bit line direction. Lines can be arranged.

Here, the global row decoding line is used for the bias transfer purpose applied to the gate of the local switch transistor located between the cell array and the cell array, and thus is not connected to the memory cells disposed in the cell array. In addition, a dummy cell is formed under the global row decoding line to create a process condition similar to that of the memory cell.

Referring to FIG. 1, the global row decoding line 10 is formed on the upper layer of the bit lines BL0 to BL7, that is, on the same layer as the global word line, thereby creating a condition similar to that of a memory cell. For this purpose, a dummy cell string 12 having the same structure as an 8-bit memory cell string may be formed. Here, the global row decoding line 10 refers to a line for transmitting a signal for selecting a global word line output from the global row decoder.

In order to block the electrical connection between the global row decoding line 10 and the dummy cell string 12, the dummy active region 14 and the global row under the dummy cell string 12, as shown by the dotted circle 18 of FIG. Vias that electrically connect between the decoding lines 10 are not formed. In addition, the dummy active region 14 is left at the ground VSS state.

However, since the dummy cell string 12 is also electrically connected to the bit lines BL0 to BL7 like other memory cells, the dummy cell string 12 may be electrically connected to the selected bit line BL5 when one bit line (eg, BL5) is selected. The current Ipara may flow through the dummy cell 13 connected to the dummy active region 14.

That is, when one bit line BL5 is selected, a predetermined voltage (generally, a boosted voltage VPP) is supplied to the selected bit line BL5 to access data to the memory cell. In this case, since the lower dummy active region 14 of the global row decoding line 10 is in the ground VSS state, the lower dummy active region 14 in the bit line BL5 through the dummy cell 13 connected to the selected bit line BL5. Current Ipara flows.

The parasitic current Ipara through the dummy cell 13 may affect the data state according to the phase change of the memory cell. Accordingly, a malfunction of a sense amplifier (not shown) that senses and amplifies the data may occur. There is a problem that may be difficult to distinguish the '1' and '0' of the data.

The present invention provides a phase change memory device capable of preventing data access errors due to parasitic currents occurring in dummy cells in a cell array.

A phase change memory device according to an aspect of the present invention includes a first active region and the bit lines electrically connected to each of the global word lines at an intersection point between bit lines in a cell array region and global word lines crossing them. Each of the phase change memory cells formed therebetween, when a first voltage is supplied to any one of the bit lines and a second voltage having a level lower than the first voltage level is supplied to the global word line crossing the bit line. A plurality of memory cell strings in which phase changes of the memory cells connected thereto are made; And a phase change structure identical to that of the memory cells, each formed between the bit lines and the second active region electrically connected to a dummy line to which a third voltage having a level equal to or greater than the first voltage is supplied in the cell array region. And one or more dummy cell strings each including a plurality of dummy cells having a plurality of dummy cells.

Here, the first voltage is a boosted voltage having a level higher than an external power supply voltage, the second voltage is a ground voltage, and the third voltage is a voltage having a level higher than or equal to the boosted voltage.

In the above configuration, each of the memory cells includes a switching element and a phase change resistor electrically connected between the first active region and the bit line, respectively, wherein each dummy cell includes the second active region and the bit line. It is preferable to include a dummy switching element and a dummy phase change resistor electrically connected therebetween. Here, each switching element includes a diode having a cathode terminal electrically connected to the first active region and an anode terminal electrically connected to each of the phase change resistors, wherein each dummy switching element includes the second active region. And a dummy diode having a cathode terminal electrically connected to the anode terminal and an anode terminal electrically connected to each of the dummy phase change resistors.

Each dummy cell string is formed in the second active region below the global row decoding line disposed in parallel to the global word lines in the cell array region, and between the global row decoding line and the second active region. Is preferably electrically blocked.

In addition, the dummy line may be electrically connected to the second active area through vias formed in an outer portion of the dummy cell array in the second active area, and the dummy line is a lower layer than the global word lines. It is preferably formed in.

According to another aspect of the present invention, a phase change memory device may be formed at an intersection point between bit lines and global word lines crossing them so that the potential of each bit line is higher than the potential of each global word line crossing it. When the phase change is made, the plurality of memory cells for accessing data, the dummy active region electrically connected to the dummy line and the bit lines are respectively formed so that the potential of each bit line is higher than the potential of the dummy active region. A cell array including a plurality of dummy cells in which a phase change occurs; And select one of the plurality of global word lines during data access to supply a first voltage to the selected global word line, and select one of the plurality of bit lines during data access to the selected bit line. And a cell array controller supplying a second voltage having a level higher than a first voltage and supplying a third voltage equal to or greater than the second voltage level to the dummy line.

The first voltage may be a ground voltage, the second voltage may be a boosted voltage having a level higher than an external power supply voltage, and the third voltage may be a voltage having a level higher than or equal to the boosted voltage.

In the above configuration, a global row decoding line for selecting global word lines is formed on the plurality of dummy cells, and the global row decoding line and the dummy active region are electrically blocked.

Each of the memory cells includes a switching element and a phase change resistor electrically connected between each of the global word lines and each of the bit lines, and each of the dummy cells is electrically connected between the dummy active region and each of the bit lines. It is preferable to include a dummy switching element and a dummy phase change resistor connected to each other. Here, each switching element includes a diode having a cathode terminal electrically connected to each of the global word lines and an anode terminal electrically connected to each of the phase change resistors, wherein each dummy switching element is connected to the dummy active region. It is preferable to include a dummy diode having a cathode terminal electrically connected to each other and an anode terminal electrically connected to each of the dummy phase change resistors.

In the layout method of a phase change memory device according to the present invention, a plurality of first active regions and one or more second active regions are formed in a cell array region; A plurality of memory cells having a phase change structure are formed in each of the first active regions, and a plurality of dummy cells having the same phase change structure as the memory cells are formed in each of the second active regions; A plurality of bit lines electrically connected to each of the memory cells and each of the dummy cells, each bit line having a second voltage level state that is maintained at a first voltage level state when inactive and is higher than the first voltage level when activated. And an upper portion of each of the dummy cells to intersect the first and second active regions; A plurality of global wordlines electrically connected to the respective first active regions, the plurality of global wordlines having the first voltage level state when inactive and being maintained at the second voltage level state when inactive; 1 overlapping with the active region; And a dummy line electrically connected to the second active region and maintaining a level above the second voltage, outside the dummy cells.

The first voltage may be a ground voltage, the second voltage may be a boosted voltage having a level higher than an external power supply voltage, and the third voltage may be a voltage having a level higher than or equal to the boosted voltage.

In the method, the dummy line is formed on the same layer as the plurality of bit lines on top of the second active region, and a via is formed between the second active region and the dummy line so that the second line passes through the via. Preferably, the active region and the dummy line are electrically connected to each other.

In addition, a third active region extending from the second active region to the outside of the cell array region is further formed, and the dummy line is formed on the third active region, and between the third active region and the dummy line. The via is formed in the second and third active region and the dummy line is preferably electrically connected to each other through the via.

In addition, it is preferable that a global row decoding line for selecting the plurality of global word lines is further formed on the plurality of bit lines overlapping each of the second active regions.

Each of the memory cells may include a switching element including a first N-type semiconductor and a first P-type semiconductor formed on the first active region; And a phase change resistor formed on the first P-type semiconductor and electrically connected to the switching device.

Each dummy cell may include a dummy switching element including a second N-type semiconductor and a second P-type semiconductor formed on the second active region, corresponding to the configuration of each memory cell; And a dummy phase change resistor formed on the second P-type semiconductor and electrically connected to the dummy switching device.

The present invention provides a phase change memory device for supplying a voltage higher than a bit line activation voltage level to a dummy active region where dummy cells are formed to keep the dummy cells turned off at all times, thereby providing parasitic current generated in the dummy cells. There is an effect that can prevent the data access error caused.

The present invention discloses a phase change memory device capable of removing parasitic currents caused by the dummy cells by supplying a predetermined voltage to the dummy active region where the dummy cells are formed so that the dummy cells do not operate when bit lines are activated.

Specifically, the phase change memory device according to the present invention includes a plurality of cell array units, and one cell array unit includes a cell array 20 and a cell array controller 28 as illustrated in FIG. 2. Can be.

The cell array 20 includes a plurality of memory cell strings 22 and one or more dummy cell strings 24.

Here, each of the memory cell strings 23 has a global word line GWL0 to GWL7 at an intersection point between the bit lines BL0 to BL7 and the global word lines GWL0 to GWL7 crossing them in the cell array 20 region. Each of the phase change memory cells formed between the active region and bit lines BL0 to BL7 electrically connected to each other), and a global word line having a potential of one of the bit lines BL0 to BL7 intersected therewith. When higher than the potential of (e.g., GWL0), a phase change of the memory cells connected to them occurs.

The dummy cell strings 24 are formed between the dummy active regions electrically connected to the dummy lines DL and the bit lines BL0 to BL7, respectively, and have a plurality of dummy cells having the same phase change structure as those of the memory cells. Each includes.

In the cell array 20 having the above configuration, one memory cell string 23 may include, for example, eight memory cells in one global word line (eg, GWL0) corresponding to the bit lines BL0 to BL7. It may have a connected structure. The dummy cell string 24 is formed in a dummy active area adjacent to the plurality of memory cells 22 in the cell array 20 area, in particular, a dummy active area under the global row decoding line GXDEC. The same number of dummy cells as the memory cells 23 connected to the global word line (eg, GWL0).

The cell array controller 28 selects any one of a plurality of global word lines GWL0 to GWL7 during data access to supply the first voltage to the selected global word line, and a plurality of bit lines BL0 during data access. Select one of ˜BL7) to supply the second voltage to the selected bit line, and to raise the level above the second voltage to a dummy active region in which a plurality of dummy cells 24 are formed through the dummy line DL. Supplying the third voltage. Here, the first voltage is a ground voltage VSS, the second voltage is a boosted voltage VPP having a level higher than the external power supply voltage VDD, and the third voltage is a boosted voltage VPP or a voltage higher than the boosted voltage VPP. Do.

As such, the cell array controller 28 that controls data access of the cell array 20 includes a plurality of first switching elements that control activation of the global word lines GWL0 to GWL7, and bit lines BL0 to BL7. It may be configured to include a plurality of second switching elements for controlling the activation of.

Here, each of the first switching elements may be configured by a MOS transistor M1, and a gate of each MOS transistor M1 is commonly connected to the global row decoding line GXDEC. One end of each of the MOS transistors M1 is connected to each of the global word lines GWL0 to GWL7, and the other end of each of the MOS transistors M1 optionally has a boost voltage VPP or a ground voltage VSS depending on the command and row address information. Supplied.

These MOS transistors M1 are enabled when the global row decoding signal is transmitted through the global row decoding line GXDEC to supply a boosted voltage VPP or ground voltage VSS to the global word lines GWL0 to GWL7, in particular. The ground voltage VSS is supplied to the selected global word line (eg, GWL0) according to the row address information, and the boosted voltage VPP is supplied to the remaining global word lines GWL1 to GWL7.

Each of the second switching elements for controlling activation of each of the bit lines BL0 to BL7 may be configured by a MOS transistor M2, and gates of the respective MOS transistors M2 may be formed according to command and column address information. Selection signals that are enabled are input. One end of each MOS transistor M2 is connected to each bit line BL0 to BL7, and the other end of each MOS transistor M2 is commonly connected to the global bit line GBL.

These MOS transistors M2 are provided with a bit line corresponding to the enabled selection signal when the boosted voltage VPP is supplied through the global bit line GBL and one of the selection signals is enabled. To boost voltage VPP.

As described above, the phase change memory device according to the present invention includes a plurality of memory cells 22 and a plurality of dummy cells 24 in the cell array 20, each memory cell 22 having a global word line GWL0. The phase change is selectively performed according to the potential difference between the ~ GWL7) and each of the bit lines BL0 to BL7 to access data.

Each dummy cell 24 is formed in the same phase change structure as each memory cell 22, and the dummy active region in which the dummy cells 24 are formed is connected to the global word lines GWL0 to DWL through the dummy line DL. A space other than GWL7), for example, is disposed below the global row decoding line GXDEC to receive a voltage having a level equal to or higher than the activated bit line potential.

The structures of the memory cells 22 and the dummy cells 24 will be described below in detail with reference to FIGS. 3 and 4.

First, referring to FIG. 3, the structure of the memory cell string 23 connected to the global word line GWL0 among the plurality of memory cells 22 is defined as the active region 30 and is formed on the active region 30. A plurality of switching elements 31 is formed in the. Here, the switching element 31 includes a diode formed by selectively epitaxially growing on the active region 30, and the N-type semiconductor 31a constituting the diode, that is, the cathode terminal of the diode is the active region 30. The P-type semiconductor 31b constituting the diode, that is, the anode terminal of the diode is electrically connected to the phase change resistor 33 through the lower electrode contact 32 described above.

The lower electrode contact 32 is formed on the P-type semiconductor 31b of each switching element 31, and the phase change resistor 33 is formed on each lower electrode contact 32. That is, the switching element 31 is electrically connected to the phase change resistor 33 through the lower electrode contact 32. Here, the phase change resistor 33 may be composed of the phase change film 33a and the upper electrode 33b, and may further include a lower electrode (not shown).

An upper electrode contact 34 is formed on the upper electrode 33b of each phase change resistor 33, and bit lines BL0 to BL7 are formed on each upper electrode contact 34. That is, the phase change resistor 33 is electrically connected to the bit line (eg, BL0) through the upper electrode contact 34.

In the active region 30, two vias 35 and 36 are formed outside the region where the memory cell string 23 is formed, and a global word line GWL0 is formed on the upper via 36. In other words, the active region 30 is electrically connected to the global word line GWL0 through the lower via 35 and the upper via 36.

In the above structure, the global word line GWL0 is maintained at the boosted voltage VPP level when the data access operation is not performed, and the bit lines BL0 to BL7 are maintained at the ground voltage VSS level. Therefore, a reverse bias is formed in the diode constituting the switching element 31 of the memory cell string 23 so that current does not flow to the phase change resistor 33.

On the other hand, when the global word line GWL0 is activated and any one of the bit lines BL0 to BL7 (for example, BL0) is activated when a data access operation is performed by a read or write command, the global word line The ground voltage VSS is supplied to the GWL0, and the boosted voltage VPP is supplied to the bit line BL0. Therefore, a forward bias is formed in the diode constituting the switching element 31 of the memory cell string 23 so that current flows to the phase change resistor 33.

That is, when the global word line GWL0 and the bit line BL0 are activated, a current path is formed from the bit line BL0 to the active region 30. As the current path is formed, the amount of current varies according to the resistance of the crystalline state and the amorphous state of the phase change film 33a constituting the phase change resistor 33, and the amount of current changes in the sense amplifier (not shown). The data is divided into '1' and '0'.

At this time, the ground voltage VSS is applied to all of the bit lines BL1 to BL7 that are not activated, that is, not selected, and the boosted voltage VPP is applied to all the global word lines GWL1 to GWL7 that are not selected. Accordingly, the selected bit line BL0 and the non-selected global word lines GWL1 to GWL7 connected to each other are at the same potential p state at the boosted voltage VPP level so that no current path is formed. Similarly, the non-selected bit lines BL1 to BL7 and the selected global word line GWL0 are all at the same potential at the ground voltage VSS level, so that no current path is formed.

Next, referring to FIG. 4, a structure of the dummy cell string 24 corresponding to the structure of the memory cell string 23 of FIG. 3 is defined, and a plurality of dummy active regions 40 are defined on the dummy active regions 40. A dummy switching element 41 is formed. Here, the dummy switching element 41 includes a dummy diode formed by selective epitaxial growth on the dummy active region 40, and the N-type semiconductor 41a constituting the dummy diode, that is, the cathode of the dummy diode The terminal is electrically connected to the dummy active region 40, and the P-type semiconductor 41b constituting the dummy diode, that is, the anode terminal of the dummy diode is connected to the phase change resistor through the lower electrode contact 42 to be described above. 43) is electrically connected.

A lower electrode contact 42 is formed on the P-type semiconductor 41b of each dummy switching element 41, and a dummy phase change resistor 43 is formed on each lower electrode contact 42. That is, the switching element 41 is electrically connected to the dummy phase change resistor 43 through the lower electrode contact 42. Here, the dummy phase change resistor 43 may be composed of a phase change film 43a and an upper electrode 43b, and may further include a lower electrode (not shown) corresponding to the structure of the memory cell.

An upper electrode contact 44 is formed on the upper electrode 43b of each phase change resistor 43, and bit lines BL0 to BL7 are formed on each upper electrode contact 44. That is, the phase change resistor 43 is electrically connected to the bit line (eg, BL0) through the upper electrode contact 44.

On the other hand, vias 45 are formed outside the region where the dummy cell strings 24 are formed in the dummy active region 40, and global row decoding lines GXDEC are formed on the vias 45 at predetermined intervals. . In other words, the dummy active region 40 is not electrically connected to the global row decoding line GXDEC.

In addition, a via 46 is formed on the edge of the dummy active region 40 corresponding to the edge of the region of the cell array 20 of FIG. 2, and the via 46 receives a voltage having a level equal to or higher than the boost voltage VPP. The dummy line DL is formed. In this case, the dummy line DL may be formed on the upper portion of the dummy active region 40 except for the region where the dummy cell string 24 is formed. In addition, the dummy active region 40 may extend outside the region of the cell array 20, and a dummy line DL may be formed on the extended dummy active region 40.

In the above structure, the bit lines BL0 to BL7 are maintained at the ground voltage VSS level when the data access operation is not performed, and the dummy active region 40 is maintained at the level higher than the boosted voltage VPP, so that the dummy cell string 24 The reverse bias is formed in the dummy diode constituting the dummy switching element 41 of Fig. 2) so that no current flows to the dummy phase change resistor 43.

In addition, when any one of the bit lines BL0 to BL7 (eg, BL0) is activated when a data access operation is performed by a read or write command, the boosted voltage VPP is supplied to the bit line BL0. Therefore, an equipotential is formed at both ends of the dummy diode constituting the dummy switching element 41 of the dummy cell string 24, or a reverse bias is formed at the dummy diode so that no current flows to the phase change resistor 43.

A structure in which the dummy active region 40 extends outside the cell array 20 region to be electrically connected to the dummy line DL may have a layout structure as illustrated in FIG. 5. In FIG. 5, the same reference numerals as in the above-described drawing indicate the same members having the same function.

As shown in FIG. 5, a memory cell region 50 and a dummy cell region 52 are defined in the cell array 20, and a plurality of active regions 30 are defined in the memory cell region 50. Not shown). In addition, a memory cell string 23 is formed in each active region 30, and a plurality of bit lines BL0 to BL7 are formed on the memory cell string 23.

In addition, a dummy active region 40 corresponding to a global row decoding line (not shown) and having one end extending outward of the cell array 20 is disposed in the dummy cell region 52, and a dummy in the cell array 20. The dummy cell string 24 is formed in the active region 40. In addition, a via 46 is formed in the dummy active region 40 extending outside the cell array 20 so that the dummy active region 40 is formed on the outside of the cell array 20 through the via 46. Electrically).

Referring to the layout structure of the dummy cell disposed at the end of the dummy cell string 24 in the dummy cell region 52 and the dummy line DL electrically connected to the dummy cell, it may have a structure as shown in FIG. 6. have. Likewise, in Fig. 6, the same reference numerals as those in the previously shown drawings indicate the same members having the same function.

Referring to FIG. 6, a dummy active region 40 is defined over a cell array (not shown) and an outer side of the cell array, and a dummy switching element is formed at one side of the dummy active region 40 defined in the cell array. 41 is disposed and the via 45 is disposed on the other side.

The lower electrode contact 42 is disposed on the dummy switching element 41, and the dummy phase change resistor 43 is disposed on the lower electrode contact 42. Here, the dummy switching element 41 and the dummy phase change resistor 43 are electrically connected to each other through the lower electrode contact 42.

An upper electrode contact 44 is disposed above the phase change resistor 43, and a bit line BL7 is disposed above the upper electrode contact 44. Here, the phase change resistor 43 and the bit line BL7 are electrically connected to each other through the upper electrode contact 44.

The global row decoding line GXDEC is disposed on the bit line BL7 and the via 45. Here, the global row decoding line GXDEC is not electrically connected to the bit line BL7 and the via 45.

On the other hand, the via 46 is disposed above the dummy active region 40 defined outside the cell array, and the dummy line DL is disposed above the via 46. Here, the dummy active region 40 and the dummy line DL are electrically connected to each other through the via 46.

As described above, in the phase change memory device according to the present invention, in a cell array including a plurality of memory cells and a plurality of dummy cells, a potential higher than a bit line activation potential may be applied to a dummy active region where the plurality of dummy cells are formed. By walking, both ends of the plurality of dummy cells are maintained at an equipotential or the plurality of dummy cells in a reverse bias state.

Therefore, since parasitic current does not flow through the plurality of dummy cells when the bit line is activated, a current sensing margin of the sense amplifier can be secured, thereby preventing an error in data access by the current sensing. have.

1 is a cross-sectional view illustrating a structure of a dummy cell string provided in a conventional phase change memory device.

2 is a circuit diagram illustrating a phase change memory device according to the present invention.

3 is a cross-sectional view for explaining the structure of the cell memory string 23 of FIG.

4 is a cross-sectional view illustrating the structure of the dummy cell string 24 of FIG. 2.

5 is a plan view showing a layout structure of a phase change memory device according to the present invention;

FIG. 6 is a plan view illustrating a layout structure of one dummy cell provided in the dummy cell string 24 of FIG. 5 and a dummy line DL electrically connected thereto.

Claims (19)

Each of the first active region electrically connected to each of the global word lines and a phase change memory cell formed between the bit lines at an intersection point between bit lines and global word lines crossing them in a cell array region; And a phase change of a memory cell connected thereto when a first voltage is supplied to one of the bit lines and a second voltage having a level lower than the first voltage level is supplied to the global word line crossing the bit line. A memory cell string; A plurality of dummy cells each formed between the second active region and the bit lines below the global row decoding line disposed in the cell array region in parallel with the global word lines and having the same phase change structure as the memory cells; One or more dummy cell strings each including; Including; And the second active region is electrically disconnected from the global row decoding line and electrically connected to a dummy line supplied with a third voltage having a level equal to or greater than the first voltage. The method of claim 1, And the first voltage is a boosted voltage having a level higher than an external power supply voltage, the second voltage is a ground voltage, and the third voltage is a voltage having a level equal to or higher than the boosted voltage. The method of claim 1, Each of the memory cells includes a switching element and a phase change resistor electrically connected between the first active region and the bit line, and each dummy cell is electrically connected between the second active region and the bit line. A phase change memory device comprising a dummy switching element and a dummy phase change resistor. The method of claim 3, wherein Each switching element includes a diode having a cathode terminal electrically connected to the first active region and an anode terminal electrically connected to each phase change resistor, wherein each dummy switching element is electrically connected to the second active region. And a dummy diode having a cathode terminal connected to each other and an anode terminal electrically connected to each of the dummy phase change resistors. delete The method of claim 1, And the dummy line is electrically connected to the second active region through vias formed in an outer portion of the dummy cell array in the second active region. The method of claim 6, The dummy line is formed in a lower layer than the global word lines. A plurality of memory cells each formed at an intersection point between bit lines and global word lines crossing the bit lines, and having a phase change when the potential of each bit line is higher than the potential of each global word line crossing it; And a dummy active region under the global row decoding line arranged in parallel with the global word lines and between the dummy active region and the bit lines, which are electrically disconnected from the global row decoding line and electrically connected to the dummy line. A cell array including a plurality of dummy cells in which a phase change occurs when the potential of each bit line is higher than the potential of the dummy line; And Select one of the plurality of global word lines to supply a first voltage to the selected global word line during data access, and select one of the plurality of bit lines to access the selected bit line to the selected bit line during data access And a cell array controller configured to supply a second voltage having a level higher than one voltage, and supply a third voltage equal to or greater than the second voltage level to the dummy line. The method of claim 8, And the first voltage is a ground voltage, the second voltage is a boosted voltage having a level higher than an external power supply voltage, and the third voltage is a voltage having a level equal to or higher than the boosted voltage. delete The method of claim 8, Each memory cell includes a switching element and a phase change resistor electrically connected between each global word line and each bit line, and each dummy cell is electrically connected between the dummy active region and each bit line. A phase change memory device comprising a dummy switching element and a dummy phase change resistor. The method of claim 11, Each switching element includes a diode having a cathode terminal electrically connected to each of the global word lines and an anode terminal electrically connected to each of the phase change resistors, wherein each dummy switching element is electrically connected to the dummy active region. And a dummy diode having a cathode terminal connected to each other and an anode terminal electrically connected to each of the dummy phase change resistors. A plurality of first active regions and one or more second active regions are formed in the cell array region, A plurality of memory cells having a phase change structure are formed in each of the first active regions, and a plurality of dummy cells having the same phase change structure as the memory cells are formed in each of the second active regions, A plurality of bit lines electrically connected to each of the memory cells and each of the dummy cells, each bit line having a second voltage level state that is maintained at a first voltage level state when inactive and is higher than the first voltage level when activated. And an upper portion of each of the dummy cells to intersect the first and second active regions, A plurality of global wordlines electrically connected to the respective first active regions, the plurality of global wordlines having the first voltage level state when inactive and being maintained at the second voltage level state when inactive; 1 is formed to overlap the active area, A global row decoding line for selecting the plurality of global word lines is formed to overlie the second active regions on top of the plurality of bit lines, And a dummy line electrically connected to the second active region and maintaining a level above the second voltage is formed outside the dummy cells. The method of claim 13, And the first voltage is a ground voltage, the second voltage is a boosted voltage having a level higher than an external power supply voltage, and the third voltage is a voltage having a level equal to or higher than the boosted voltage. The method of claim 13, The dummy line is formed on the same layer as the plurality of bit lines on the second active region, and a via is formed between the second active region and the dummy line, so that the second active region and the second line are formed through the via. A layout method of a phase change memory device in which dummy lines are electrically connected to each other. The method of claim 13, A third active region extending from the second active region to the outside of the cell array region is further formed, and the dummy line is formed on the third active region, and a via is formed between the third active region and the dummy line. Is formed to electrically connect the second and third active regions and the dummy line to each other through the vias. delete The method of claim 13, Each of the memory cells, A switching element including a first N-type semiconductor and a first P-type semiconductor formed on the first active region; And And a phase change resistor formed on the first P-type semiconductor and electrically connected to the switching element. The method of claim 18, Each dummy cell, A dummy switching element including a second N-type semiconductor and a second P-type semiconductor formed on the second active region; And And a dummy phase change resistor formed on the second P-type semiconductor and electrically connected to the dummy switching element.

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