CN101964211B - Chip erasing method - Google Patents
Chip erasing method Download PDFInfo
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- CN101964211B CN101964211B CN201010504613.0A CN201010504613A CN101964211B CN 101964211 B CN101964211 B CN 101964211B CN 201010504613 A CN201010504613 A CN 201010504613A CN 101964211 B CN101964211 B CN 101964211B
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- predetermined portions
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Abstract
A kind of chip erasing method, comprises and obtains corresponding wordline by decoding, wherein also comprise: the wordline of described correspondence decoding obtained is divided into predetermined portions, chooses the wordline of each several part respectively successively; Chip erase operation is performed simultaneously to all wordline chosen.The present invention by wordline being carried out decoding and portions is chosen, avoid wordline decoding simultaneously and choose in a flash to the huge consumption of power, alleviate the impact on supply voltage, can effectively realize chip erase action.
Description
Technical field
The present invention relates to flush memory device, the chip erasing method especially in flush memory device.
Background technology
Flash memory (FlashMemory) is a kind of non-volatile storer, under powering-off state, still can keep stored data message.Flash memory is the mutation of Electrical Erasable ROM (read-only memory) (EEPROM), and be different from EEPROM and only can carry out deleting and rewriteeing in byte-level, flash memory can perform the erasable of whole chip, thus has than EEPROM speed faster.
Chip erase (chiperase) is a kind of important operation in flash memory.In prior art, usually adopt such chip erasing method: first, decoding is carried out to the whole wordline in chip, to obtain the address of all wordline; Then, choose whole wordline according to decode results simultaneously; Then, carry out set to chosen wordline, such as unification sets high level or low level simultaneously, thus wipes numerical value original in whole wordline.
With reference to figure 1, flash memory at least comprises code translator 110, for carrying out decoding to wordline; And wordline array 120.When flash memory performs chip erase function, first carry out decoding by code translator 110 pairs of wordline.Such as, described flash memory has 4nk bar wordline, and code translator 100 can comprise n bit lines accordingly, by the value of each bit lines being set to 1 or be set to 0, with the wordline corresponding to the decode results determining code translator 100.Then, with reference to figure 2, choose all wordline by enable signal simultaneously, such as, described enable signal X can be pulse signal, or rising edge signal, when there is described enable signal, all wordline corresponding to decoding are all applied in a scheduled voltage, such as supply voltage value.To choose described wordline.Then, then by erase signal, set is carried out to all wordline simultaneously, to complete erase operation.
But in the prior art, when all wordline are carried out decoding and choose in simultaneously to chip, all wordline are by pre-applied to same magnitude of voltage, and this makes the moment all wordline are selected can produce very large power consumption.The moment high power consumption produced can bring problems, such as, dragged down the value of supply voltage, thus affects the normal work of chip, and the not selected situation of meeting generating portion wordline, thus cannot complete the operation of chip erase.Even, also can produce and will produce some negative effects at chip internal, such as, produce the forward bias of P type FET, and then cause breech lock (latchup) effect.
In order to avoid the problems referred to above, be necessary to provide a kind of chip erasing method.
Summary of the invention
The technical matters that the present invention solves is to provide a kind of chip erasing method, to solve the instantaneous high power consumption existed when performing chip erase operation and the contingency question that may bring thereof.
For solving the problems of the technologies described above, the invention provides a kind of chip erasing method, comprising and obtaining corresponding wordline by decoding, wherein also comprising: the wordline of described correspondence decoding obtained is divided into predetermined portions, chooses the wordline of each several part respectively successively; Chip erase operation is performed simultaneously to all wordline chosen.
Optionally, the number of the predetermined portions described wordline be divided into is determined according to the power consumption of chip power size and word line decoding.
Optionally, the number of described predetermined portions is the natural number power of 2.
Optionally, described predetermined portions is one of in 2,4,8 and 16.
Compared with prior art, the present invention is easy and simple to handle, can complete according to the power consumption of chip power size and word line decoding to a word line decoding point portions, achieves the equilibrium of work consumption and decoding effect, reduce instantaneous power consumption during decoding, avoid the problems brought therefrom.
Accompanying drawing explanation
Fig. 1 is the structural representation of code translator and wordline array in prior art;
Fig. 2 be in prior art all wordline by the waveform schematic diagram chosen simultaneously;
Fig. 3 is the schematic flow sheet of a kind of embodiment of chip erasing method of the present invention;
Fig. 4 is the structural representation that in a kind of embodiment of chip erasing method of the present invention, wordline is divided into 4 predetermined portions;
Fig. 5 is that the wordline being divided into predetermined portions in a kind of embodiment of chip erasing method of the present invention distinguishes selected waveform schematic diagram.
Embodiment
Inventor is after summarizing a large amount of practical experiences, propose a kind of novel chip erasing method, be divided into predetermined portions by wordline decoding obtained and choose the wordline of each several part respectively, after this erasing is performed again, thus avoid due to simultaneously to the instantaneous high power consumption that all wordline are carried out decoding and chosen and bring, and due to moment power consumption increase and the problems such as supply voltage reduction brought, effectively save man-hour and energy consumption, ensure that the normal work of chip.
Below in conjunction with the drawings and specific embodiments, the embodiment of chip erasing method of the present invention is described further.
With reference to figure 3, a kind of embodiment of chip erasing method of the present invention can comprise:
Step S1, obtains corresponding wordline by decoding;
Step S2, the wordline of described correspondence decoding obtained is divided into predetermined portions, chooses the wordline of each several part respectively successively;
Step S3, after the decoding completing all wordline, performs chip erase action.
Wherein, the interpretation method adopted in step S1 can be the mode of bit by bit decoding, such as, determining corresponding described wordline according to the value of each word bit, (being respectively a for comprising 8 bit lines
7a
6a
5a
4a
3a
2a
1a
0) code translator, its decode results may correspond in 2
8bar wordline, wherein, the bit line value of the code translator corresponding with the decode results of acquisition the 35th article of wordline is 00100011.In addition, decoding described in step S1 also can comprise other interpretation method, and those skilled in the art will be understood that the selection about concrete interpretation method does not impact the present invention's design.
In step s 2, the number of the predetermined portions that described wordline is divided into can be determined according to the power consumption of chip power size and word line decoding.Specifically, the power consumption produced when all wordline are chosen simultaneously compare chip power larger time, then described wordline can be divided into more multiple predetermined portions; Otherwise, then described wordline can be divided into less predetermined portions.
Wherein, the number of described predetermined portions can be the natural number power of 2, reduces hardware implementing complexity.When the number of described predetermined portions is more, the number of the wordline that every part comprises is fewer, and the risk producing moment high power consumption is less, but increases the time performing chip erase and consume; And when the number of described predetermined portions is fewer, the possibility of high power consumption generation is larger instantaneously.In addition, inventor is found by repeatedly research experiment, owing to wordline being divided into predetermined portions and gradation chooses the time phase difference of required time and decoding more, therefore, by when the number of described predetermined portions is less, larger delay can't be caused to the overall time performing chip erase.According to the specific design requirement of chip, such as, according to the power consumption of chip power size and word line decoding, the number of suitable predetermined portions can be selected, thus obtain balance in instantaneous lower power consumption with between the execution time.Such as, the number of described predetermined portions can be set to 2,4,8,16 etc.
In a specific embodiment, 4 parts such as described wordline are divided into choose respectively.With reference to figure 4, can choose two bits from described wordline, described wordline is divided into described 4 parts by the combination according to these two bit values.Such as, wordline WL forms b by 8 bits
7b
6b
5b
4b
3b
2b
1b
0, get two the bit b in its end
1b
0.B
1b
0wordline WL1 corresponding when=00 is Part I; b
1b
0wordline WL2 corresponding when=01 is Part II; b
1b
0wordline WL3 corresponding when=10 is Part III; b
1b
0wordline WL4 corresponding when=11 is Part IV.Wherein, above-mentioned wordline WL1, wordline WL2, wordline WL3 and wordline WL4 comprise 2 respectively
6bar wordline.
In other embodiments, also described wordline can be divided into 2 parts, or be divided into 8 parts.Wherein, when described wordline being divided into 2 parts, a bit b can be chosen from described wordline
i, i is any one integer in 0-7; Every part wordline comprises 2
7bar wordline.And when described wordline being divided into 8 parts, can from described wordline optional three bit b
mb
nb
l, m, n, l are respectively integers different in 0-7 respectively; b
mb
nb
lwordline WL1 corresponding when=000 is Part I; b
mb
nb
lwordline WL2 corresponding when=001 is Part II; b
mb
nb
lwordline WL3 corresponding when=010 is Part III; b
mb
nb
lwordline WL4 corresponding when=011 is Part IV; b
mb
nb
lwordline WL5 corresponding when=100 is Part V; b
mb
nb
lwordline WL6 corresponding when=101 is Part VI; b
mb
nb
lwordline WL7 corresponding when=110 is Part VII; b
mb
nb
lwordline WL8 corresponding when=111 is Part VIII.Wherein, above-mentioned wordline WL1, wordline WL2, wordline WL3, wordline WL4, wordline WL5, wordline WL6, wordline WL7 and wordline WL8 comprise 2 respectively
5bar wordline.
Then, the wordline of every part is chosen by part.With reference to figure 5, by arranging enable signal X, making when each rising edge, the wordline of corresponding part being pulled up to the first magnitude of voltage VDD1, thus realize choosing described corresponding part wordline.Enable signal X also can be other signal form, such as, can be square-wave signal, or pulse signal etc.Because wordline is divided into some parts, the decreased number of the wordline that every part comprises,
Then, when all wordline are all selected, perform step S3, carry out chip erase, specifically, with reference to figure 5, by the Voltage Cortrol of all wordline chosen to a certain magnitude of voltage VEE, thus erasing move can be realized.
Compared to prior art, the invention described above chip erasing method is by being divided into predetermined portions by described wordline, and by part, described wordline is chosen, thus avoid due to simultaneously to the instantaneous high power consumption that all wordline are carried out decoding and chosen and bring, and due to moment power consumption increase and the problems such as supply voltage reduction brought, effectively save man-hour and energy consumption, ensure that the normal work of chip.。
Although the present invention illustrates as above by preferred embodiment, these preferred embodiments are also not used to limit the present invention.Those skilled in the art, without departing from the spirit and scope of the present invention, should have the ability make various correction to this preferred embodiment and supplement, therefore, protection scope of the present invention is as the criterion with the scope of claims.
Claims (3)
1. a chip erasing method, comprises and obtains corresponding wordline by decoding, it is characterized in that, also comprise:
Determine the number of the predetermined portions described wordline be divided into according to the power consumption of chip power size and word line decoding, the wordline of described correspondence decoding obtained is divided into predetermined portions, chooses the wordline of each several part respectively successively;
Chip erase operation is performed simultaneously to all wordline chosen.
2. chip erasing method as claimed in claim 1, it is characterized in that, the number of described predetermined portions is the natural number power of 2.
3. chip erasing method as claimed in claim 2, is characterized in that, described predetermined portions is one of in 2,4,8 and 16.
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| CN201010504613.0A CN101964211B (en) | 2010-10-12 | 2010-10-12 | Chip erasing method |
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| CN201010504613.0A CN101964211B (en) | 2010-10-12 | 2010-10-12 | Chip erasing method |
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| CN101964211A CN101964211A (en) | 2011-02-02 |
| CN101964211B true CN101964211B (en) | 2015-12-02 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719815A (en) * | 1988-05-13 | 1998-02-17 | Hitachi, Ltd. | Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle |
| US7248518B2 (en) * | 2003-01-21 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Self-timed memory device providing adequate charging time for selected heaviest loading row |
| CN101079323A (en) * | 2006-05-23 | 2007-11-28 | 恩益禧电子股份有限公司 | Nonvolatile semiconductor memory device capable of stably performing erase operation and method of operating the same |
| CN101488368A (en) * | 2007-11-07 | 2009-07-22 | 三洋电机株式会社 | Memory |
-
2010
- 2010-10-12 CN CN201010504613.0A patent/CN101964211B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719815A (en) * | 1988-05-13 | 1998-02-17 | Hitachi, Ltd. | Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle |
| US7248518B2 (en) * | 2003-01-21 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Self-timed memory device providing adequate charging time for selected heaviest loading row |
| CN101079323A (en) * | 2006-05-23 | 2007-11-28 | 恩益禧电子股份有限公司 | Nonvolatile semiconductor memory device capable of stably performing erase operation and method of operating the same |
| CN101488368A (en) * | 2007-11-07 | 2009-07-22 | 三洋电机株式会社 | Memory |
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