JP4363384B2 - Line drive circuit and display device - Google Patents

Description

The present invention relates Viewing apparatus using line driving circuit and the same.

  For example, a display panel such as a liquid crystal panel is used for a display unit of an electronic device such as a mobile phone, and the power consumption and size and weight of the electronic device are reduced. With respect to this display panel, when a still image or a moving image having high information properties is distributed due to the spread of mobile phones in recent years, higher image quality is required.

  An active matrix liquid crystal panel using a thin film transistor (hereinafter abbreviated as TFT) liquid crystal is known as a liquid crystal panel that realizes high image quality in the display unit of such an electronic device. In addition, an organic EL panel using an organic EL element is known.

  For example, in an active matrix liquid crystal panel using TFT liquid crystal, a high voltage is required for display driving depending on the liquid crystal material and the transistor capability of the TFT. For this reason, a driver circuit (line drive circuit) and a power supply circuit for driving the display of a liquid crystal panel or the like need to be manufactured by a high breakdown voltage process.

  Therefore, when the liquid crystal panel is driven for display, there is a problem that even if the process is miniaturized, the merit of cost reduction due to the miniaturization cannot be enjoyed.

  Also, with advances in mounting technology and communication technology, for example, mobile phones are rapidly spreading, and communication services for acquiring users are being improved among communication carriers. Therefore, it is necessary for mobile phone manufacturers to quickly put products corresponding to each communication service on the market. For this reason, it is essential for manufacturers to shorten the product development TAT.

  Taking a cellular phone as an example, the arrangement of various semiconductor devices for driving the display panel of the display unit may differ depending on the mounting method, or the display control timing may differ due to specification changes during development. In such a case, it is desirable to be able to reduce the development TAT in a flexible manner even in the above-described case, which causes a delay in market introduction due to product redesign or the like.

The present invention has been made in view of the above technical problems, it is an object, the display device using efficiently achieve line driving circuit and this cost reduction due to miniaturization of the process Is to provide.

Another object of the present invention is to provide a Viewing device using the line drive circuit can be effectively shortened and this development TAT of the display panel.

In order to solve the above-described problems, the present invention provides a line driving circuit that drives a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines that intersect each other. And
A first terminal group to which a signal group to be supplied to a second line driving circuit that drives the second line is input from a display controller that controls display of the electro-optical device;
A second terminal group for outputting the signal group to the second line driving circuit;
An I / O circuit region including a circuit for outputting a signal group input via the first terminal group to the second terminal group;
Including
The I / O circuit area has an I / O circuit provided for each terminal,
The I / O circuit is
Multiple selector lines,
A first selector circuit for connecting any one of the first terminal groups and any one of the plurality of selector lines based on a given first selection signal;
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
Of the first side of the line driving circuit and the second side facing the first side, the first side close to the electro-optical device is parallel to the arrangement direction of the plurality of second lines. To be arranged as
The I / O circuit area relates to a line driving circuit disposed on the second side of the line driving circuit.

The present invention also provides a line drive circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other,
A first terminal group to which a signal group to be supplied to a second line driving circuit that drives the second line is input from a display controller that controls display of the electro-optical device;
A second terminal group for outputting the signal group to the second line driving circuit;
An I / O circuit region including a circuit for outputting a signal group input via the first terminal group to the second terminal group;
Including
The I / O circuit area has an I / O circuit provided for each terminal,
The I / O circuit is
Multiple selector lines,
A first selector circuit for connecting any one of the first terminal groups and any one of the plurality of selector lines based on a given first selection signal;
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
Of the first side of the line driving circuit and the second side facing the first side, the first side close to the electro-optical device is parallel to the arrangement direction of the plurality of second lines. To be arranged as
The first terminal group relates to a line driving circuit disposed at least in a central portion of the second side of the line driving circuit.

The present invention also provides a line drive circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other,
A first terminal group to which a signal group to be supplied to a second line driving circuit that drives the second line is input from a display controller that controls display of the electro-optical device;
A second terminal group for outputting the signal group to the second line driving circuit;
An I / O circuit region including a circuit for outputting a signal group input via the first terminal group to the second terminal group;
Including
The I / O circuit area has an I / O circuit provided for each terminal,
The I / O circuit is
Multiple selector lines,
A first selector circuit for connecting any one of the first terminal groups and any one of the plurality of selector lines based on a given first selection signal;
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
The I / O circuit region is disposed in a region below a power supply wiring for supplying a power supply voltage to an internal circuit of the line driving circuit.
The power supply wiring is
The present invention relates to a line driving circuit arranged in the chip peripheral part on one side of the line driving circuit.

In the line driving circuit according to the present invention,
The I / O circuit area may include a switching circuit for switching the second terminal group to any one of a plurality of given terminal groups.

In the line driving circuit according to the present invention,
A first output buffer circuit for converting the voltage of the first selector line into a low withstand voltage voltage and supplying the converted voltage to the output terminal;
A second output buffer circuit that converts the voltage of the first selector line into a high withstand voltage voltage and supplies the voltage to the output terminal;
A first input buffer circuit for supplying a low withstand voltage voltage supplied to the input terminal to the first selector line as a low withstand voltage;
A second input buffer circuit for converting a high voltage system voltage supplied to the input terminal into a low voltage system voltage and supplying the converted voltage to the first selector line;
Including
Exclusive operation control is performed so that one of the first and second output buffer circuits and the first and second input buffer circuits is in an operating state and the other buffer circuit is in a non-operating state. May be.

In the line driving circuit according to the present invention,
A phase inversion circuit in which at least one of the first and second output buffer circuits and the first and second input buffer circuits inverts the phase of the output signal or the input signal based on a given inversion control signal Can be included.

In the line driving circuit according to the present invention,
Inserted between the first selector line and the first node where the input terminals of the first and second input buffer circuits and the output terminals of the first and second output buffer circuits are connected in common Switching means may be included.

The present invention also provides a line drive circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other,
A first terminal group to which a signal group to be supplied to a second line driving circuit and a power supply circuit for driving the second line is input from a display controller for controlling display of the electro-optical device;
A second terminal group for outputting the signal group to the second line driving circuit;
An I / O circuit region including a circuit for outputting a signal group input via the first terminal group to the second terminal group;
A third terminal group for outputting the signal group to the power supply circuit;
Including
The I / O circuit area has an I / O circuit provided for each terminal,
The I / O circuit is
Multiple selector lines,
A first selector circuit for connecting any one of the first terminal groups and any one of the plurality of selector lines based on a given first selection signal;
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
Of the first side of the line driving circuit and the second side facing the first side, the first side close to the electro-optical device is parallel to the arrangement direction of the plurality of second lines. To be arranged as
The present invention relates to a line drive circuit arranged in the order of the second and third terminal groups from the center of the second side to the corner.

In the line driving circuit according to the present invention,
The I / O circuit area may include a switching circuit for switching the second or third terminal group to any one of a plurality of given terminal groups.

In the line driving circuit according to the present invention,
The first line may be a signal line to which a voltage based on image data is supplied.

The present invention also provides a pixel specified by a plurality of first lines and a plurality of second lines intersecting each other;
The line drive circuit described above;
A second line driving circuit for driving the second line;
Related to an electro-optical device.

The present invention also provides an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
The line drive circuit described above;
A second line driving circuit for driving the second line;
Related to the display device.

  According to another aspect of the invention, there is provided a line driving circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines that intersect with each other. A first terminal group to which a signal group to be supplied from a display controller for display control to a second line driving circuit that drives a second line is input, and the second line driving circuit, A second terminal group for outputting the signal group; and an I / O circuit region including a circuit for outputting the signal group input via the first terminal group to the second terminal group. It is characterized by including.

  Here, as the electro-optical device, for example, the first to Nth scanning lines and the first to Mth signal lines intersecting with each other, and the first to Nth scanning lines and the first to Mth signal lines are connected. The N × M switching unit and the N × M pixel electrode connected to the switching unit may be provided. The electro-optical device may be an organic EL panel.

  According to the present invention, among the line driving circuit and the second line driving circuit that perform display driving in cooperation with the display controller under control of the pixels specified by the first and second lines, line driving is performed. In the circuit, a signal to be supplied from the display controller to the second line driving circuit is received by the first group of terminals, and this is received via the second terminal group to the second line driving circuit. I tried to supply. Therefore, by arranging the first and second terminal groups, it is possible to avoid the intersection of wirings necessary for display driving, and to provide a low-cost line driving circuit that does not need to cope with multi-layering.

  In the invention, it is preferable that the I / O circuit area includes a switching circuit for switching the second terminal group to any one of a plurality of terminal groups.

  According to the present invention, since the second terminal group can be arbitrarily switched in the I / O circuit region, it is possible to avoid a situation in which wiring crossing occurs depending on the mounting method, Development TAT can be shortened and implementation flexibility can be greatly improved.

  In the invention, it is preferable that the I / O circuit region is disposed on a second side facing the first side on the electro-optical device side.

  According to the present invention, it is possible to improve the flexibility of arrangement of the line drive circuit and the second line drive circuit that supply various control signals and image data necessary for display drive to the electro-optical device.

  In the invention, it is preferable that the first terminal group is arranged at least in a central portion of a second side facing the first side on the electro-optical device side.

  According to the present invention, by arranging the first terminal group to which the signal group is input in the vicinity of the center portion of the second side, the terminal group for outputting the signal group is set to the corner portion of the second side. Therefore, the intersection of the input signal group wiring and the output signal group wiring can be efficiently avoided.

  Further, the present invention is characterized in that the I / O circuit region is disposed in a region under a power supply wiring for supplying a power supply voltage therein.

  According to the present invention, the above-described I / O circuit region can be efficiently arranged in a chip shape, and the chip area can be reduced.

  According to the present invention, the I / O circuit area includes an I / O circuit provided for each terminal, and the I / O circuit is based on a plurality of selector lines and a given first selection signal. The first selector circuit for connecting any one of the first terminal groups and any one of the plurality of selector lines to the first selector circuit and a given second selection signal And a second selector circuit for connecting any one of the second terminal groups to the first selector line.

  According to the present invention, the first and second selector circuits connect the first and second terminal groups via any one of the plurality of selector lines. A plurality of combinations of the second terminal group can be set. Accordingly, a signal from the display controller can be received at an arbitrary terminal of the line driving circuit, and a signal to be supplied can be output from the arbitrary terminal.

  The present invention also provides a first output buffer circuit that converts the voltage of the first selector line into a low-breakdown-voltage voltage and supplies the voltage to the output terminal; A second output buffer circuit that converts the voltage into a system voltage and supplies the voltage to the output terminal; and supplies the low voltage system voltage supplied to the input terminal to the first selector line while maintaining the low voltage system voltage. And a second input buffer circuit that converts a high voltage system voltage supplied to the input terminal into a low voltage system voltage and supplies the converted voltage to the first selector line. Exclusive operation control is performed so that any one of the first and second output buffer circuits and the first and second input buffer circuits is in an operating state and the other buffer circuits are in a non-operating state. It is characterized by There.

  According to the present invention, the first and second output buffer circuits and the first and second input buffer circuits supply the internal low voltage system voltage as it is as the low voltage system voltage or the high voltage system. Or a circuit that takes in a low withstand voltage or high withstand voltage from the outside as a low withstand voltage voltage can be provided for each terminal. Or it can set to an output terminal. Thereby, a user's usability can be improved significantly.

  According to the present invention, at least one of the first and second output buffer circuits and the first and second input buffer circuits adjusts the phase of the output signal or the input signal based on a given inversion control signal. A phase inverting circuit for inverting is included.

  According to the present invention, the phase inversion circuit that inverts the phase (logic level) of the input signal or the output signal based on the inversion control signal is provided in at least one of the buffer circuits. Thus, even when the display control timing such as the rising edge or the falling edge is changed, the delay in product development due to the redesign of the circuit can be eliminated.

  The present invention also provides a first node in which the input terminals of the first and second input buffer circuits and the output terminals of the first and second output buffer circuits are connected in common, and the first selector line. And switching means inserted between them.

  According to the present invention, the output load of the buffer circuit can be reduced by electrically disconnecting the first node and the first selector line as appropriate by the switching means. Therefore, the circuit scale can be reduced.

  According to another aspect of the invention, there is provided a line driving circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines that intersect with each other. A first terminal group to which a signal group to be supplied to a second line driving circuit for driving a second line and a power supply circuit is input from a display controller for controlling display, and the second line driving circuit. On the other hand, an I / O circuit including a second terminal group for outputting the signal group and a circuit for outputting the signal group input via the first terminal group to the second terminal group And a third terminal group for outputting the signal group to the power supply circuit, and the second terminal group includes a first side on the side where the electro-optical device is disposed Along the corner from the center of the opposing second side, Serial second is characterized by being arranged in the order of the third group of terminals.

  According to the present invention, the output terminal group for supplying to the second line driving circuit and the output terminal group for supplying to the power supply circuit are arranged in order from the center portion of the second side to the corner portion. Therefore, when the power supply circuit is arranged at an intermediate position between the line drive circuit and the second line drive circuit, the power supply wiring for supplying the power supply voltage from the power supply circuit to the line drive circuit, the second line drive circuit, etc. No signal line.

  In the invention, it is preferable that the I / O circuit area includes a switching circuit for switching the second or third terminal group to any one of a plurality of terminal groups. .

  According to the present invention, since the second or third terminal group can be arranged at an arbitrary position, it is possible to provide a line driving circuit that realizes optimum wiring without depending on the mounting method. it can.

  In the invention, it is preferable that the first line is a signal line to which a voltage based on image data is supplied.

  According to the present invention, since it is applied to, for example, a signal drive circuit that drives a signal line, it is possible to reduce the cost of a display controller that controls the signal drive circuit and shorten the development TAT of the signal drive circuit itself. Become.

  The electro-optical device according to the aspect of the invention may include pixels specified by a plurality of first lines and a plurality of second lines that intersect with each other, the line drive circuit described above, and a second line that drives the second line. 2 line driving circuits.

  According to the present invention, it is possible to provide an electro-optical device that can reduce the cost of a display controller by shortening the development TAT and miniaturizing the process.

  The display device according to the present invention includes an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other, the above-described line driving circuit, and the second line. And a second line driving circuit for driving the first line driving circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which can implement | achieve cost reduction of a display controller by shortening development TAT and refinement | miniaturization of a process can be provided.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.

1. 1. Display Device 1.1 Configuration of Display Device FIG. 1 shows an outline of the configuration of a display device including a line driving circuit in the present embodiment.

  A liquid crystal device 10 as a display device includes a liquid crystal display (hereinafter abbreviated as LCD) panel 20, a signal driver (signal drive circuit, line drive circuit) (a source driver in a narrow sense) 30, a scan driver ( It includes a scanning drive circuit, a second line drive circuit (gate driver in a narrow sense) 50, an LCD controller (display controller in a broad sense) 60, and a power supply circuit (voltage supply circuit in a broad sense) 80.

The LCD panel (electro-optical device in a broad sense) 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of scanning lines arranged in the Y direction and extending in the X direction (in the narrow sense, gate lines) (second lines) G _{1 to} G _N (N is a natural number of 2 or more), A plurality of signal lines (in a narrow sense, source lines) (first lines) S _{1 to} S _M (M is a natural number of 2 or more) arranged in the X direction and extending in the Y direction are arranged. The TFT 22 _nm (switching means in a broad sense) corresponds to the intersection of the scanning line G _n (1 ≦ n ≦ N, n is a natural number) and the signal line S _m (1 ≦ m ≦ M, m is a natural number). ) Is provided.

The gate electrode of the TFT 22 _nm is connected to the scanning line G _n . The source electrode of the TFT 22 _nm is connected to the signal line S _m. A drain electrode of the TFT 22 _nm is connected to a pixel electrode 26 _nm of a liquid crystal capacitor (liquid crystal element in a broad sense) 24 _nm .

In the liquid crystal capacitance 24 _nm , liquid crystal is sealed between the counter electrode 28 _nm facing the pixel electrode 26 _nm and the transmittance of the pixel changes according to the applied voltage between these electrodes. Yes.

The counter electrode voltage Vcom generated by the power supply circuit 80 is supplied to the counter electrode 28 _nm .

The signal driver 30 drives the signal lines S _{1 to} S _M of the LCD panel 20 based on the image data of one horizontal scanning unit.

  More specifically, the signal driver 30 sequentially latches the serially input image data to generate image data for one horizontal scanning unit. The signal driver 30 drives each signal line with a driving voltage based on the image data in synchronization with the horizontal synchronizing signal.

The scan driver 50 sequentially scans and drives the scan lines G _{1 to} G _N of the LCD panel 20 in synchronization with the horizontal synchronizing signal within one vertical scanning period.

  More specifically, the scan driver 50 has a flip-flop corresponding to each scan line, and has a shift register in which the flip-flops are sequentially connected. The scan driver 50 sequentially selects the scan lines within one vertical scan period by sequentially shifting the vertical synchronization signals supplied from the LCD controller 60.

  The LCD controller 60 controls the signal driver 30, the scan driver 50, and the power supply circuit 80 according to the contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). More specifically, the LCD controller 60 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the signal driver 30 and the scan driver 50, and supplies to the power supply circuit 80. Supplies the polarity inversion timing of the counter electrode voltage Vcom.

  The power supply circuit 80 generates a voltage level necessary for driving the liquid crystal of the LCD panel 20 and a counter electrode voltage Vcom based on a reference voltage supplied from the outside. Such various voltage levels are supplied to the signal driver 30, the scan driver 50, and the LCD panel 20. The counter electrode voltage Vcom is supplied to a counter electrode provided to face the pixel electrode of the TFT of the LCD panel 20.

  In the liquid crystal device 10 having such a configuration, the signal driver 30, the scanning driver 50, and the power supply circuit 80 cooperate to display and drive the LCD panel 20 based on image data supplied from outside under the control of the LCD controller 60. To do.

  In FIG. 1, the liquid crystal device 10 includes the LCD controller 60, but the LCD controller 60 may be provided outside the liquid crystal device 10. Alternatively, a host may be included in the liquid crystal device 10 together with the LCD controller 60.

1.2 Liquid Crystal Drive Waveform FIG. 2 shows an example of the drive waveform of the LCD panel 20 of the liquid crystal device 10 having the above-described configuration. Here, a case of driving by a line inversion driving method is shown.

  In the liquid crystal device 10, the signal driver 30, the scan driver 50, and the power supply circuit 80 are controlled according to the display timing generated by the LCD controller 60. The LCD controller 60 sequentially transfers the image data of one horizontal scanning unit to the signal driver 30 and supplies the internally generated horizontal synchronization signal and the polarity inversion signal POL indicating the inversion driving timing. In addition, the LCD controller 60 supplies an internally generated vertical synchronization signal to the scan driver 50. Further, the LCD controller 60 supplies the common electrode voltage polarity inversion signal VCOM to the power supply circuit 80.

  Thereby, the signal driver 30 drives the signal line based on the image data of one horizontal scanning unit in synchronization with the horizontal synchronizing signal. The scan driver 50 sequentially scans the scan lines connected to the gate electrodes of the TFTs arranged in a matrix on the LCD panel 20 with the drive voltage Vg using the vertical synchronization signal as a trigger. The power supply circuit 80 supplies the internally generated counter electrode voltage Vcom to each counter electrode of the LCD panel 20 while performing polarity inversion in synchronization with the counter electrode voltage polarity inversion signal VCOM.

The liquid crystal capacitor is charged with a charge corresponding to the voltage Vcom between the pixel electrode connected to the drain electrode of the TFT and the counter electrode. When the pixel electrode voltage Vp held by the charge accumulated in the liquid crystal capacitor exceeds a given threshold value _VCL , an image can be displayed. When the pixel electrode voltage Vp exceeds a given threshold value _VCL , the transmittance of the pixel changes according to the voltage level, and gradation expression becomes possible.

2. 2. Features of the Present Embodiment 2.1 Manufacturing Process By the way, in the liquid crystal device, the voltage required for display driving differs for each semiconductor device (LCD controller, signal driver, scan driver, power supply circuit).

  FIG. 3 shows an example of the connection relationship between the semiconductor devices constituting the liquid crystal device.

  Here, the value of the power supply voltage level of signals transmitted and received between the semiconductor devices is also shown.

  The LCD panel 120, the signal driver 130, the scanning driver 150, the LCD controller 160, and the power supply circuit 180 that constitute the liquid crystal device 100 have the same functions as the respective components that constitute the liquid crystal device 10 shown in FIG.

  For example, since the circuit configuration of the signal driver 130 is not so complicated, the signal driver 130 is manufactured not by a state-of-the-art miniaturization process but by a medium withstand voltage process (for example, 0.35 μ process) that can achieve both integration and cost reduction. The

  Further, since the scan driver 150 has a simple circuit configuration, it is not required to reduce the chip size, and the scan driver 150 has a high voltage (for example, 20 V to 50 V) determined by the relationship between the liquid crystal material and the transistor capability of the TFT. Is manufactured by a high withstand voltage process.

  Further, the power supply circuit 180 is manufactured by a high withstand voltage process in order to generate a high voltage supplied to the scan driver 150.

  On the other hand, since the LCD controller 160 has a complicated circuit configuration and high versatility, the cost can be further reduced by reducing the chip size. Therefore, the LCD controller 160 is manufactured by a state-of-the-art miniaturization process (for example, a 0.18 μ process). That is, since the LCD controller 160 is manufactured in a low withstand voltage process, it has both an interface circuit for a low withstand voltage process and an interface circuit for a high withstand voltage process.

  The interface circuit for the low withstand voltage process supplies a signal generated at the power level of the miniaturization process with the low withstand voltage to the signal driver 130 manufactured in the medium withstand voltage process. The high-breakdown-voltage process interface circuit supplies a signal converted to a high-breakdown-voltage process power supply level to the scan driver 150 and the power supply circuit 180 manufactured in the high-breakdown-voltage process.

  Thus, the LCD controller 160 includes an interface circuit for a high voltage process. The above-described interface circuit for a high withstand voltage process cannot reduce the area in the IC because the physical limit value for ensuring the withstand voltage exists in the design rule even if the process is miniaturized. Therefore, the merit of cost reduction by miniaturization cannot be enjoyed much.

  On the other hand, in the liquid crystal device 10 according to the present embodiment, a signal group to be supplied from the LCD controller 60 manufactured by the low breakdown voltage process to the scan driver 50 and the power supply circuit 80 manufactured by the high breakdown voltage process. The signal driver 30 is once relayed by the signal driver 30 manufactured by the medium withstand voltage process, and the signal driver 30 supplies these signal groups to the scanning driver 50 and the power supply circuit 80.

  FIG. 4 shows an example of the connection relationship of each semiconductor device constituting the liquid crystal device in this embodiment.

  As described above, the signal driver 30 according to the present embodiment includes the interface circuit that converts the low withstand voltage system voltage into the high withstand voltage system voltage using the medium withstand voltage process in the interface unit 200. A voltage group is received and converted into a high voltage with a high breakdown voltage, and then supplied to the scan driver 50 or the power supply circuit 80.

  By doing so, the interface unit 210 of the LCD controller 60 does not need to be provided with an interface circuit that drives a high voltage. Therefore, with the miniaturization of the process, the circuit of a complicated configuration is reduced and the cost is reduced. It becomes possible to plan.

2.2 Mounting method In addition, in the liquid crystal device, the signal driver, the scanning driver and the power supply circuit cooperate to drive the LCD panel. Therefore, each circuit is connected depending on the mounting position of the LCD panel, each driver and the power supply circuit. There are cases where the signal lines to be crossed.

  Therefore, if the substrate does not support multi-layer wiring, wiring can no longer be performed. Further, even when the substrate is compatible with multilayer wiring, the cost is increased.

  Hereinafter, this point will be described in detail by taking a COG (Chip On Glass) mounting method and a COF (Chip On Film) mounting method as examples.

  5A, 5B, and 5C show an outline of a configuration of a liquid crystal device mounted with COG.

  In the case of the COG mounting method, as shown in FIG. 5A, as a COG module, an additional circuit such as a signal driver 30, a scanning driver 50, and other capacitive elements is formed on a glass substrate 250 on which the LCD panel 20 is built. Is implemented. A connector portion 252A of this COG module and a connector portion 252B of a PCB (Printed Circuit Board) 254 on which a CPU, a memory, etc. as shown in FIG. 5B are mounted, as shown in FIG. It is electrically connected via a spring connector.

  6A, 6B, and 6C show an outline of the configuration of a liquid crystal device mounted with COF.

  In the case of the COF mounting method, as shown in FIG. 6A, a flexible tape 260 on which an additional circuit such as a signal driver 30 and a scanning driver 50 and other capacitive elements are mounted as a COF module, and the LCD panel 20 are formed. The glass substrate 262 thus made is electrically connected. The connector portion 264A of this COF module and the connector portion 264B of the PCB 266 on which the CPU, memory, etc. as shown in FIG. 6B are mounted are electrically connected via, for example, a spring connector as shown in FIG. 6C. Connected.

  In the case of the COG mounting method, since the chip is flip-chip mounted directly on the glass substrate 250, the active surface of the chip faces the glass substrate 250 in a face-down state because of easy connection to the take-out electrode of the LCD panel 20. May be implemented.

  On the other hand, in the case of the COF mounting method, in order to mount the semiconductor device on which the chip is mounted on the flexible tape 260, the extraction electrode of the LCD panel 20 and the terminal of this semiconductor device are electrically connected. That is, in the case of the COF mounting method, the active surface of the chip is on the upper side.

  As described above, the orientation of the active surface of the chip such as the signal driver 30 for driving the LCD panel 20 is changed depending on the mounting method in the housing. That is, the position of the terminal of the signal driver 30 or the like changes depending on the mounting method, and depending on the mounting method, it means that the wiring of the LCD panel 20 and the signal driver 30 or the like may or may not intersect.

3. FIG. 7 shows a principle configuration of the signal driver 30 according to this embodiment.

  The signal driver 30 includes an I / O circuit area 280, and includes an input terminal group (first terminal group) 282 to which an input signal group is input, and an output terminal group (second terminal group) from which an output signal group is output. , A third terminal group) 284.

  The I / O circuit area 280 includes a circuit that outputs a signal group input via the first terminal group to the second or third terminal group. More specifically, the I / O circuit area 280 includes a phase inverting circuit 286 that inverts the phase of the input signal group input via the input terminal group 282, and a signal group that is phase-inverted by the phase inverting circuit 286. A level conversion circuit (Level Shifter: hereinafter abbreviated as L / S) 288 for converting a low withstand voltage system voltage into a high withstand voltage system voltage.

  Therefore, the input terminal group 282 is connected to the LCD controller 60 manufactured by the low withstand voltage process, and the output terminal group 284 is connected to either the scan driver 50 or the power supply circuit 80 manufactured by the high withstand voltage process. It is not necessary to provide the controller 60 with a high voltage interface circuit, and the cost can be reduced by miniaturizing the LCD controller 60.

  In addition, since the phase (logic level) can be appropriately reversed by the phase inversion circuit 286, even when the display control timing is changed due to a change in the interface specification during development, the circuit redesign is accompanied. Product development delays can be eliminated.

  FIGS. 8A, 8B, and 8C show an example of a more specific configuration of the signal driver 30. FIG.

  In FIG. 8A, the signal group input via the input terminal group 282 is subjected to level conversion to a high voltage system voltage by the L / S 288 and then the exclusive OR (EXclusive OR) as the phase inverting circuit 286. : Hereinafter abbreviated as EXOR.) The signal is input to the circuit 290. The EXOR circuit 290 further receives an inversion control signal. When the logic level of the inversion control signal is “H”, the logic level of the output signal of the L / S 288 is inverted and output from the output terminal group 284. To do. On the other hand, when the logic level of the inversion control signal is “L”, the logic level of the L / S output signal is output from the output terminal group 284 as it is. Such an inversion control signal can be generated according to the register contents set by the LCD controller 60, for example. In this case, phase inversion can be arbitrarily performed by software.

  In FIG. 8B, the inversion control signal described above is generated by cutting the fuse 292. That is, by disconnecting one of the fuses connected between the node to which the inversion control signal of the EXOR circuit 290 is input and the power supply voltage level and the ground level, the logic level of this node is set to “H” or It can be fixed to “L”. In this case, since a control circuit for generating an inversion control signal is not necessary, the circuit can be simplified.

  In FIG. 8C, the signal group input via the input terminal group 282 is input to the EXOR circuit 290 as the phase inverting circuit 286, and the output signal of the EXOR circuit 290 is converted into a high voltage system voltage by the L / S288. The signal is level-converted and output from the output terminal group 284. In this case, as compared with FIGS. 8A and 8B, the EXOR circuit 290 can be configured with a low-breakdown-voltage transistor, and the EXOR circuit 290 can be further downsized.

  In the present embodiment, the above-described phase inverting circuit 286 and L / S 288 are provided in the I / O circuit region, and a switching circuit that arbitrarily switches an input terminal group and an output terminal group from among a plurality of terminal groups of the signal driver 30. Is provided. Therefore, as shown in FIGS. 9A and 9B, the side opposite to the signal driving electrode for the signal line of the LCD panel 20 (the second side facing the first side on the electro-optical device (pixel) side) ) Is provided with an I / O circuit area 280, and the positions of the input terminal group and the output terminal group are arbitrarily switched according to the mounting method, whereby the position of the terminal of the signal to be connected to the take-out electrode of the LCD panel according to the mounting method Even if the change occurs, the wiring does not intersect with the glass substrate or the flexible tape, and the cost of the liquid crystal device can be reduced.

4). Signal driver (line drive circuit) in this embodiment
Hereinafter, such a signal driver (line driving circuit) 30 will be described in detail.

  FIG. 10 shows an outline of the configuration of the signal driver 30 in the present embodiment.

The signal driver 30 has input / output pads 400 _{1 to} 400 _Q (Q is a natural number) provided corresponding to each terminal of the semiconductor device.

The signal driver 30 further has an I / O circuit 410 _j corresponding to the input / output pad 400 _j (1 ≦ j ≦ Q, j is a natural number), and forms an I / O circuit region. One or a plurality of selector lines 430 are commonly connected to the I / O circuits 410 _{1 to} 410 _Q. In the following, it is assumed that there are 16 selector lines.

The I / O circuit 410 _j includes a plurality of input buffer circuits and a plurality of output buffer circuits, and functions as either an input I / O circuit or an output I / O circuit according to a given selection signal. It has become. For example, when the I / O circuit 410 ₁ is set as an input I / O circuit and the I / O circuit 410 _Q is set as an output I / O circuit, a signal input via the input / output pad 400 ₁ is given by by the first selection signal, the I / O circuits 410 ₁ of the selector circuit, is outputted to one of the selector line 430 (first selector line). At this time, the input high-voltage or low-voltage signal is converted into a low-voltage voltage level.

In the I / O circuit 410 _Q , the first selector line and the input / output pad 410Q are electrically connected by the selector circuit according to a given second selection signal. At this time, the signal that has passed through the first selector line is converted to a voltage level of a high withstand voltage system or a low withstand voltage system.

  In this way, a signal from an arbitrary input terminal can be level-converted to a given voltage and output from an arbitrary output terminal.

FIG. 11 schematically shows a layout image of the I / O circuit 410 _j described above.

I / O circuit _{410 j (1 ≦ j ≦ Q} ) is output pad 400 _j electrically connected to the LV (Low Voltage) -LV buffer circuit _{412 j, LV-HV (High} Voltage) buffer circuit 418 _j , A selector circuit 424 _j and a gate array (hereinafter abbreviated as G / A) circuit 426 _j .

The LV-LV buffer circuit 412 _j includes an LV-LV output buffer circuit 414 _j and an LV-LV input buffer circuit 416 _j .

The LV-LV output buffer circuit (first output buffer circuit) 414 _j buffers the input / output voltage of the low withstand voltage (LV) signal with a buffer circuit connected to the LV power supply voltage level. This circuit outputs to the pad 400 _j .

The LV-LV input buffer circuit (first input buffer circuit) 416 _j is a buffer circuit in which the voltage of the LV signal input through the input / output pad 400 _j is connected to the LV power supply voltage level. This is a circuit for buffering and outputting to the selector circuit 424 _j .

The LV-HV buffer circuit 418 _j includes an LV-HV output buffer circuit 420 _j and an HV-LV input buffer circuit 422 _j .

The LV-HV output buffer circuit (second output buffer circuit) 420 _j is a circuit that converts the voltage of the LV signal into the voltage of the HV signal and outputs it to the input / output pad 400 _j .

The HV-LV input buffer circuit (second input buffer circuit) 422 _j is a buffer circuit in which the voltage of the HV signal input via the input / output pad 400 _j is connected to the LV power supply voltage level. This is a circuit for buffering and outputting to the selector circuit 424 _j .

The selector circuit 424 _j is one of the LV-LV output buffer circuit 414 _j , the LV-LV input buffer circuit 416 _j , the LV-HV output buffer circuit 420 _j , and the HV-LV input buffer circuit 422 _j. 430 is a circuit for connecting any one of 430.

The G / A circuit 426 _{j excludes any one} of the LV-LV output buffer circuit 414 _j , the LV-LV input buffer circuit 416 _j , the LV-HV output buffer circuit 420 _j , and the HV-LV input buffer circuit 422 _j. It is a logic circuit that generates a control signal for controlling the operation and a selection signal for the selector circuit 424 _j .

Such an I / O circuit 410 _j includes an LV-LV output buffer circuit 414 _j , an LV-LV input buffer circuit 416 _j , an LV-HV output buffer circuit 420 _j , and an HV-LV input by a G / A circuit 426 _j . Only one of the buffer circuits 422 _j is controlled exclusively. That is, the input buffer circuit and the output buffer circuit that are not selected are controlled so that at least their outputs are in a high impedance state. The selected input buffer circuit or output buffer circuit is electrically selected as one of the selector lines selected by the G / A circuit 426 _j . The selected selector line is electrically connected to the input / output pad via another I / O circuit.

  In this way, an I / O circuit and an input / output pad are arbitrarily selected, and these selected I / O circuits are electrically connected via a selector line, whereby an LV system is connected between arbitrary terminals. Alternatively, the voltage of the HV signal can be converted and output.

Incidentally, as shown in FIG. 11, A-A line, B-B line, along either line C-C, for example, Al is disconnects the input-output pads 400 _j deposited, electrically from each other By forming separate pads, the LV and HV signal interface functions may be provided in the I / O circuit 410 _j .

FIG. 12 shows an outline of an example of the circuit configuration of the I / O circuit 410 _j .

The input / output pad 400 _j includes an output terminal of the LV-LV output buffer circuit 414 _j, an input terminal of the LV-LV input buffer circuit 416 _j, an output terminal of the LV-HV output buffer circuit 420 _j , and an HV-LV input buffer circuit 422. _It is electrically connected to the _j input terminal.

The input terminal of the LV-LV output buffer circuit 414 _j , the output terminal of the LV-LV input buffer circuit 416 _j , the input terminal of the LV-HV output buffer circuit 420 _j , and the output terminal of the HV-LV input buffer circuit 422 _j are switches. It is electrically connected to a node ND (first node) as one end of the circuit SWA.

The other end of the switch circuit SWA is connected via a selector circuit 424 _j that a selector switch SW1～SW16, are connected to the selector line SL1～SL16.

The control signals SB1 to SB4 that exclusively control each buffer circuit, the switch control signal SA that performs on / off control of the switch circuit SWA, and the selection signals SEL1 to SEL16 that selectively select the selector switches SW1 to SW16 are: , Generated by the control circuit 440 _j . The control circuit 440 _j is configured by G / A as shown in FIG. The control circuit 440 _j generates control signals SB1 to SB4 and selection signals SEL1 to SEL16 according to the setting contents by a host (not shown).

The switch circuit SWA reduces output loads of the LV-LV input buffer circuit 416 _j and the HV-LV input buffer circuit 422 _j by electrically disconnecting each buffer circuit and the selector switches SW1 to SW16. Therefore, it is possible to reduce the size of the LV-LV input buffer circuit 416 _j and the HV-LV input buffer circuit 422 _j .

In the present embodiment, the LV-LV output buffer circuit 414 _j , the LV-LV input buffer circuit 416 _j , the LV-HV output buffer circuit 420 _j , and the HV-LV input buffer circuit 422 _j are used together with the control signals SB1 to SB4. the inversion control signal INV1~INV4 supplied from the control circuit 440 _j, inverted (reversed phase) the logic level of the input signal, and is capable of outputting. Here, a phase inverting circuit is provided in each buffer circuit, but the present invention is not limited to this.

  Hereinafter, a specific configuration example of each buffer circuit will be described.

  Here, it is assumed that the LV power supply voltage is VCC, the HV power supply voltage is VDD, and the ground level is VSS. For example, an inverted signal of the control signal CONT is expressed as XCONT.

FIG. 13 shows an example of the circuit configuration of the LV-LV output buffer circuit 414 _j .

The LV-LV output buffer circuit 414 _j includes inverter circuits 500 _j and 504 _j , an EXOR circuit 502 _j , a level shifter (hereinafter abbreviated as LS) 506 _j , and a transfer circuit 508 _j .

The LS 506 _j and the transfer circuit 508 _j are configured by HV transistors. The inverter circuits 500 _j and 504 _j and the EXOR circuit 502 _j are composed of LV transistors. In the HV transistor, for example, the oxide film thickness of the LV transistor is formed thicker to improve the high voltage resistance. Therefore, the design rule of the HV transistor must be looser than the design rule of the LV transistor, and the circuit area becomes large.

The LS 506 _j converts the potential difference between the control signal SB1 and its inverted signal XSB1 into an HV system voltage, and controls the on / off of the transfer circuit 508 _j .

Input node ND is connected to an input node of inverter circuit 500 _j .

An input node and an output node of the inverter circuit 500 _j are connected to the EXOR circuit 502 _j . The EXOR circuit 502 _j calculates an exclusive OR of the inversion control signal INV1 and the logic level of the input node ND, and the result is supplied to the input node of the inverter circuit 504 _j .

The output node of the inverter circuit 504 _j is connected to the input / output pad 400 _j via the transfer circuit 508 _j .

In this manner, the LV-LV output buffer circuit 414 _j arbitrarily inverts the logic level of the input node ND by the inversion control signal INV1. The output node is connected to the input / output pad 400 _j via the HV transfer circuit 508 _j . As a result, the HV system voltage is erroneously supplied to the input / output pad 400 _j , and the reliability can be maintained without destroying the LV system transistor. Further, since the logic level can be arbitrarily inverted by the inversion control signal INV1, it is possible to avoid a design change accompanying a change in the external interface specification and shorten the development period.

FIG. 14 shows an example of the circuit configuration of the LV-LV input buffer circuit 416 _j .

The LV-LV input buffer circuit 416 _j includes an LS 520 _j , a transfer circuit 522 _j , an inverter circuit 524 _j , and an EXOR circuit 526 _j .

The LS 520 _j and the transfer circuit 522 _j are configured by HV transistors. The inverter circuit 524 _j and the EXOR circuit 526 _j are composed of LV transistors.

LS520 _j includes a control signal SB2 the potential difference between the inverted signal XSB2 converted into a voltage of the HV controls the transfer circuit 522 _j of on or off.

Through such a transfer circuit 522 _j , the input / output pad 400 _j is connected to an inverter circuit 524 _j constituted by an LV transistor.

An n-type transistor 528 _j is connected between the input node of the inverter circuit 524 _j and the ground level VSS. An inverted signal XSB2 of the control signal SB2 is supplied to the gate electrode of the n-type transistor 528 _j . Therefore, when the inverted signal XSB2 is “H”, the LV-LV input buffer circuit 416 _j is in a non-selected state, and therefore the voltage of the input node of the inverter circuit 524 _j is set to the ground level VSS via the n-type transistor 528 _j. It can be fixed, and the through current of the inverter circuit 524 _j in the non-selected state is reduced.

An input node and an output node of the inverter circuit 524 _j are connected to the EXOR circuit 526 _j . EXOR circuit 526 _j includes an inversion control signal INV2, calculates the exclusive OR between the logical level of the input node of the inverter circuit 524 _j, the result is a logical level of the node ND.

The EXOR circuit 526 _j is connected to the LV power supply voltage VCC via the p-type transistor 530 _j and to the ground level VSS via the n-type transistor 532 _j . The gate electrode of the p-type transistor 530 _j, an inverted signal XSB2 supplied to the gate electrode of the n-type transistor 532 _j, the control signal SB2 is supplied.

Therefore, when the LV-LV input buffer circuit 416 _j is in the selected state, the node ND outputs the above-described exclusive OR operation result, and when in the non-selected state, the node ND is in the high impedance state.

As described above, the LV-LV input buffer circuit 416 _j receives the signal from the input / output pad 400 _j by the HV transfer circuit 522 _j and arbitrarily inverts the logic level by the EXOR circuit 526 _j . As a result, even if an HV voltage is accidentally supplied to the input / output pad 400 _j , reliability is not impaired, and an LV voltage can be supplied to the node ND. In addition, since the logic level can be arbitrarily reversed by the inversion control signal INV2, it is possible to avoid a design change accompanying a change in external interface specifications and to shorten a development period.

FIG. 15 shows an example of the circuit configuration of the LV-HV output buffer circuit 420 _j .

The LV-HV output buffer circuit 420 _j includes inverter circuits 540 _j and 544 _j and an EXOR circuit 542 _j . The LV-HV output buffer circuit 420 _j includes a NAND circuit 546 _j , inverter circuits 548 _j , 552 _j , and LS550 _j . Further, the LV-HV output buffer circuit 420 _j includes a NOR circuit 554 _j , inverter circuits 556 _j , 560 _j , and LS 558 _j .

In the LV-HV output buffer circuit 420 _j , the drain terminals of the HV-HV output buffer circuit 420 _j are connected between the HV power supply voltage VDD and the ground level VSS in order to perform high impedance control on the output to the input / output pad 400 _j . A p-type transistor 562 _j and an n-type transistor 564 _j are connected.

The inverter circuits 540 _j , 544 _j , 548 _j , 556 _j , the EXOR circuit 542 _j , the NOR circuit 546 _j , and the NAND circuit 554 _j are configured by LV transistors. The LS 550 _j , 558 _j , the inverter circuits 552 _j , 560 _j , the p-type transistor 562 _j , and the n-type transistor 564 _j are composed of HV transistors.

Input node ND is connected to an input node of inverter circuit 540 _j .

An input node and an output node of the inverter circuit 540 _j are connected to the EXOR circuit 542 _j . The EXOR circuit 542 _j calculates the exclusive OR of the inversion control signal INV3 and the logic level of the input node ND, and the result is supplied to the input node of the inverter circuit 544 _j .

An output node of the inverter circuit 544 _j is connected to the NOR circuit 546 _j and the NAND circuit 554 _j .

The NOR circuit 546 _j calculates the inverted logical sum (NOR) of the logic level of the control signal SB3 and the logic level of the output node of the inverter circuit 544 _j , and supplies the result to the input node of the inverter circuit 548 _j .

The NAND circuit 554 _j calculates an inverted logical product (NAND) of the logic level of the control signal SB3 and the logic level of the output node of the inverter circuit 544 _j and supplies the result to the input node of the inverter circuit 556 _j .

The LS 550 _j converts the potential difference between the input node and the output node of the inverter circuit 548 _j into an HV system voltage, and supplies it to the input node of the inverter circuit 552 _j configured by the HV system transistor. The output node of the inverter circuit 552 _j is connected to the gate electrode of the p-type transistor 562 _j .

The LS 558 _j converts the potential difference between the input node and the output node of the inverter circuit 556 _j into an HV system voltage, and supplies it to the input node of the inverter circuit 560 _j configured by the HV system transistor. The output node of inverter circuit 560 _j is connected to the gate electrode of n-type transistor 564 _j .

In this manner, the LV-HV output buffer circuit 420 _j arbitrarily inverts the logic level of the input node ND by the inversion control signal INV3. Also, the gate control signal generated by the output node and the control signal SB3, and converts the voltage of the HV system by LS550 _j, 558 _j, so as to control the p-type transistor 562 _j and n-type transistor 564 _j Yes.

  Thereby, the logic level can be arbitrarily inverted by the inversion control signal INV3, so that the design change accompanying the change of the external interface specification can be avoided, and the development period can be shortened. Also provided is an output buffer circuit capable of level-converting an LV voltage to an HV voltage and controlling the output of the voltage with a high impedance.

FIG. 16 shows an example of the circuit configuration of the HV-LV input buffer circuit 422 _j .

The HV-LV input buffer circuit 422 _j includes an inverter circuit 570 _j and an EXOR circuit 572 _j .

  The inverter circuit 570j is configured by an HV transistor, and an LV power supply voltage VCC is supplied as a power supply voltage level.

The input / output pad 400 _j is connected to the input node of the inverter circuit 570 _j . Thus, when the voltage of the LV signal is supplied to the input / output pad 400 _j , the inverter circuit 570 _j detects this signal and generates an inverted signal at the output node.

An input node and an output node of the inverter circuit 570 _j are connected to the EXOR circuit 572 _j . EXOR circuit 572 _j includes an inversion control signal INV4, calculates the exclusive OR between the logical level of the output pad 400 _j, the result is a logical level of the node ND.

The EXOR circuit 572 _j is connected to the LV power supply voltage VCC via a p-type transistor 574 _j and to the ground level VSS via an n-type transistor 576 _j . The gate electrode of the p-type transistor 574 _j, an inverted signal XSB4 supplied to the gate electrode of the n-type transistor 576 _j, the control signal SB4 is supplied.

Therefore, when the HV-LV input buffer circuit 422 _j is in the selected state, the node ND outputs the above-described exclusive OR operation result, and when in the non-selected state, the node ND is in the high impedance state.

In this way, the HV-LV input buffer circuit 422 _j receives the signal from the input / output pad 400 _j by the HV inverter circuit 570 _{j to} which the LV power supply voltage VCC is connected, and the EXOR circuit 526 _j has a logic level. Is reversed arbitrarily. As a result, even if an HV voltage is accidentally supplied to the input / output pad 400 _j , reliability is not impaired, and an LV voltage can be supplied to the node ND. In addition, since the logic level can be arbitrarily reversed by the inversion control signal INV2, it is possible to avoid a design change accompanying a change in external interface specifications and to shorten a development period.

As described above, the control circuit 440 _j that exclusively controls the various buffer circuits generates the control signals SB1 to SB4, the selection signals SEL1 to SEL16, and the switch control signal SA.

FIG. 17 shows an example of a circuit configuration of the control circuit 440 _j .

The control circuit 440 _j generates the control signals SB1 to SB4, the selection signals SEL1 to SEL16, and the switch control signal SA described above by setting a given command register using the LCD controller 60, for example.

  For example, the data bus D7-D0 is held in the flip-flop bit by bit in synchronization with the address decode pulse generated when the LCD controller 60 accesses a given command register and the clock signal CK. . Each flip-flop is set and reset by, for example, bit data corresponding to initial data S7 to S0 for initial state setting or an inverted reset signal XRES. In this case, the initial state can be collectively set by fixing the initial data S7-S0 to the power supply voltage or the ground level by Al switching.

Thus, the data held in each flip-flop is decoded and output by the decoder circuit as control signals SB1 to SB4. With such a control circuit 440 _j , the selector circuit 424 _j can select one arbitrary selector line among the selector lines 430, and the operation of the four buffer circuits can be exclusively controlled.

  The output load can be reduced by electrically disconnecting the buffer circuit and the selector line as appropriate by the switch control signal SA.

  Further, the inversion control signals INV1 to INV4 can be generated similarly.

5. Liquid Crystal Device to which Signal Driver in This Embodiment is Applied FIG. 18 shows an outline of the configuration of the liquid crystal device 10 to which the signal driver in this embodiment is applied.

  4 identical to those in FIG. 4 are assigned the same reference numerals as in FIG.

  The LCD controller 60 transmits a clock signal CPH, a latch pulse LP as a horizontal synchronization signal, a command signal CMD for designating a command, an inverted signal INV, image data and command data to the signal driver 30. Data D0 to D17, a polarity inversion signal POL as a polarity inversion drive timing, an output enable signal OE, an enable input / output signal EIO, and an inversion reset signal XRESH are supplied to perform signal drive control.

  In addition, the LCD controller 60 provides the scan driver 50 with a clock signal CPV, a start signal STV as a vertical synchronization signal, an inverted output enable signal XOEV, an output control signal XOHV that controls the output of all scanning lines, and an inverted reset signal XRESV. The scanning drive control can be performed. In the present embodiment, control signals to be supplied from the LCD controller 60 to the scan driver 50 are relayed by the signal driver 30 having the I / O circuit as described above, and after level conversion, the control signal is sent to the scan driver 50. In contrast, it is designed to supply.

  Further, the LCD controller 60 supplies a standby control signal XSTBY, a boost mode setting signal PMDE, primary and secondary boost system clocks PCK1, PCK2, and a polarity inversion signal VCOM of the counter electrode voltage to the power supply circuit 80, Power supply control can be performed. In the present embodiment, the control signal to be supplied from the LCD controller 60 to the power supply circuit 80 is relayed by the signal driver 30 having the I / O circuit as described above, and after level conversion, the control signal is supplied to the power supply circuit 80. In contrast, it is designed to supply.

  In this way, in the LCD controller 60 having a more complicated circuit configuration, it is not necessary to provide an HV interface circuit, and level conversion is performed by the signal driver 30 manufactured by a medium withstand voltage process for relaying. Therefore, the LCD controller 60 has high versatility, and the cost can be significantly reduced by reducing the chip size by the miniaturization process.

  FIGS. 19A and 19B show an example of the arrangement of the signal driver 30 and the like for driving the display of the liquid crystal device 10 described above.

  As shown in FIG. 19A, a power supply circuit is adjacent to both sides of the signal driver 30 on the side facing the signal line driving side of the LCD panel 20 (second side facing the first side on the electro-optical device side). An input terminal group to which a control input signal group is input and an input terminal group to which a scan driver control input signal group is input are set. Furthermore, an output terminal group for a power supply circuit that outputs an output signal group obtained by level conversion of the input signal group input through the input terminal group for power supply circuit control at both ends, as described above, and scanning As described above, the output terminal group for the scanning driver from which the output signal group obtained by level-converting the input signal group input through the driver control input terminal group is set.

  In this case, as shown in FIG. 19B, in the central portion on the side facing the signal line driving side of the signal driver 30 (the second side facing the first side on the electro-optical device side), Input signal groups for signal driver control, power supply circuit control, and scan driver control are input from the LCD controller 60, and output signal groups for power supply circuit and scan driver control relayed from both ends thereof are output. The control signals do not cross each other.

  20A and 20B show another example of the arrangement of signal drivers and the like for driving the liquid crystal device 10 described above.

  As shown in FIG. 20A, the I / O circuit region is on the side facing the signal line driving side of the LCD panel 20 of the signal driver 30 (second side facing the first side on the electro-optical device side). In order from the center to the corner, an input terminal group to which various input signal groups from the LCD controller 60 are input, an output terminal group to which an output signal group for scanning driver control is output, and power supply circuit control The output terminal group from which the output signal group is output is set.

  In this case, as shown in FIG. 20B, since the power supply circuit 80 can be arranged between the signal driver 30 and the scan driver 50, a given power supply voltage is applied to the LCD panel 20 and the scan driver 50. The wiring of the power supply line for supplying the power can be efficiently wired without intersecting with the wiring of other signals.

  As shown in FIG. 21, for example, in the case of a bus such as A0-A2, the input terminals are set in the order of A0, A1, A2 along the direction E for the input signal group, and the direction for the output signal group. By setting output terminals in the order of A2, A1, and A0 along E, it is possible to relay the signals that have undergone the above-described level conversion and phase inversion while maintaining the bus arrangement direction.

  As shown in FIG. 22, the signal driver 30 has a power supply line for supplying the HV power supply voltage VDD, a power supply line for supplying the LV power supply voltage VCC, and a ground level VSS. When the power supply lines are arranged so as to circulate along the periphery of the chip, an I / O circuit region 700 having the above-described functions is provided at the lower part of each power supply line to avoid an increase in the area of the chip. Thus, it is possible to provide a signal driver effectively for cost reduction.

6). Others In the present embodiment, a liquid crystal device provided with an LCD panel using TFT liquid crystal has been described as an example. However, the present invention is not limited to this. For example, the present invention can also be applied to a signal driver and a scan driver that display-drive an organic EL panel including an organic EL element provided corresponding to a pixel specified by a signal line and a scan line.

  FIG. 23 shows an example of a two-transistor pixel circuit in an organic EL panel whose display is controlled by such a signal driver and scan driver.

The organic EL panel has a driving TFT 800 _nm , a switch TFT 810 _nm , a holding capacitor 820 _nm, and an organic LED 830 _{nm at} the intersection of the signal line S _m and the scanning line G _n . The driving TFT 800 _nm is configured by a p-type transistor.

The driving TFT 800 _nm and the organic LED 830 _nm are connected in series to the power supply line.

Switch TFT 810 _nm has a gate electrode of the driving TFT 800 _nm, is inserted between the signal line S _m. The gate electrode of the switching TFT 810 _nm is connected to the scanning line G _m.

The holding capacitor 820 _nm is inserted between the gate electrode of the driving TFT 800 _nm and the capacitor line.

In such an organic EL element, when the scanning line G _n is driven and the switch TFT 810 _nm is turned on, the voltage of the signal line S _m is written to the holding capacitor 820 _nm and applied to the gate electrode of the driving TFT 800 _nm . The gate voltage Vgs of the driving TFT 800 _nm is determined by the voltage of the signal line S _m, the current flowing through the driving TFT 800 _nm is determined. Since the driving TFT 800 _nm and the organic LED 830 _nm are connected in series, the current flowing through the driving TFT 800 _nm becomes the current flowing through the organic LED 830 _{nm as} it is.

Therefore, by holding the gate voltage Vgs corresponding to the voltage of the signal line S _m by the hold capacitor 820 _nm, for example, during one frame period, by flowing a current corresponding to the gate voltage Vgs to the organic LED 830 _nm, the frame A pixel that continues to shine can be realized.

  FIG. 24A shows an example of a 4-transistor pixel circuit in an organic EL panel whose display is controlled by the signal driver and scan driver described above. FIG. 24B shows an example of the display control timing of this pixel circuit.

Again, the organic EL panel includes a drive TFT 900 _nm, a switch TFT 910 _nm, a storage capacitor 920 _nm, and an organic LED 930 _nm.

A difference from the two-transistor pixel circuit shown in FIG. 23 is that a constant current Idata from a constant current source 950 _nm is supplied to the pixel via a p-type TFT 940 _nm as a switching element instead of a constant voltage. The point is that the power supply line is connected to the holding capacitor 920 _nm and the driving TFT 900 _nm via the p-type TFT 960 _nm as a switching element.

In such an organic EL element, first, the p-type TFT 960 is turned off by the gate voltage Vgp to cut off the power supply line, the p-type TFT 940 _nm and the switch TFT 910 _nm are turned on by the gate voltage Vsel, and the constant current source 950 _nm A constant current Idata is passed through the driving TFT 900 _nm .

Until the current flowing through the driving TFT 900 _nm is stabilized, the holding capacitor 920 _nm holds a voltage corresponding to the constant current Idata.

Then, turn off the p-type TFT 940 _nm and the switch TFT 910 _nm by the gate voltage Vsel, further to turn on the p-type TFT 960 _nm by the gate voltage Vgp, to electrically connect the driving TFT 900 _nm and the organic LED 930 _nm and a power supply line. At this time, the voltage held in the hold capacitor 920 _nm, or approximately equal to the constant current Idata, or the magnitude of the current corresponding thereto is supplied to the organic LED 930 _nm.

  In such an organic EL element, for example, the scanning line can be configured as a gate voltage Vsel and the signal line can be configured as a data line.

  In the organic LED, a light emitting layer may be provided on the transparent anode (ITO), and a metal cathode may be provided on the light emitting layer. A light emitting layer, a light transmitting cathode, and a transparent seal may be provided on the metal anode. However, the present invention is not limited to the element structure.

  By configuring the signal driver for displaying and driving the organic EL panel including the organic EL element as described above as described above, the display controller for controlling the display of the organic EL panel can be miniaturized.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention can be applied to a plasma display device.

  In this embodiment, the signal driver is described as an example of the line drive circuit, but the present invention is not limited to this.

It is a block diagram which shows the outline | summary of a structure of the display apparatus containing the line drive circuit in this embodiment. It is explanatory drawing which shows an example of the drive waveform of the LCD panel of the liquid crystal device in this embodiment. It is explanatory drawing which shows an example of the connection relation of each semiconductor device which comprises a liquid crystal device as a comparative example. It is explanatory drawing which shows an example of the connection relation of each semiconductor device which comprises the liquid crystal device in this embodiment. FIG. 5A is a schematic diagram of a COG module in which an LCD panel, a signal driver, and the like are mounted on a glass substrate. FIG. 5B is a schematic diagram showing a PCB on which a CPU and the like are mounted. FIG. 5C is a schematic view of the COG module and the PCB viewed from the lateral direction. FIG. 6A is a schematic diagram of a COF module in which an LCD panel is mounted on a glass substrate and a signal driver is mounted on a flexible tape. FIG. 6B is a schematic diagram showing a PCB on which a CPU and the like are mounted. FIG. 6C is a schematic view of the COF module and the PCB viewed from the lateral direction. It is a block diagram which shows the fundamental structure of the signal driver in this embodiment. FIG. 8A is an explanatory diagram illustrating a first example of a more specific signal driver configuration. FIG. 8B is an explanatory diagram illustrating a second example of a more specific configuration of the signal driver. FIG. 8C is an explanatory diagram illustrating a third example of a more specific signal driver configuration. FIG. 9A is an explanatory diagram illustrating a first example of the signal driver 30 in which an input terminal group and an output terminal group are set. FIG. 9B is an explanatory diagram illustrating a second example of the signal driver 30 in which the input terminal group and the output terminal group are set. It is a block diagram which shows the outline | summary of the structure of the signal driver in this embodiment. It is a schematic diagram which shows typically the layout image of the I / O circuit of the signal driver in this embodiment. It is a block diagram which shows the outline | summary of an example of a circuit structure of the I / O circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the LV-LV output buffer circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the LV-LV input buffer circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the LV-HV output buffer circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the HV-LV input buffer circuit in this embodiment. It is a block diagram which shows an example of the circuit structure of the control circuit in this embodiment. It is explanatory drawing which shows the outline | summary of a structure of the liquid crystal device to which the signal driver in this embodiment was applied. FIG. 19A is an explanatory diagram of a signal driver when an input terminal group to which an input signal group for signal driver control is input is set near the center of the I / O circuit area. FIG. 19B is an explanatory diagram showing an example of signal wiring of the liquid crystal device when this signal driver is applied. FIG. 20A shows an input terminal group to which various input signal groups of the LCD controller are input, an output terminal group from which an output signal group for scanning driver control is output, and a power supply circuit in order from the center to the corner. It is explanatory drawing of the signal driver at the time of setting the output terminal group from which the output signal group for control is output. FIG. 20B is an explanatory diagram showing an example of signal wiring of the liquid crystal device when this signal driver is applied. In the signal driver in this embodiment, it is explanatory drawing for demonstrating the setting order of a terminal in the case of relaying a bus | bath. In the signal driver in this embodiment, it is explanatory drawing for demonstrating arrangement | positioning of an I / O circuit area | region. It is a circuit diagram which shows an example of the pixel circuit of a 2 transistor system in an organic electroluminescent panel. FIG. 24A is a circuit diagram illustrating an example of a four-transistor pixel circuit in an organic EL panel. FIG. 24B is a timing chart showing an example of display control timing of a four-transistor pixel circuit.

Explanation of symbols

10, 100 liquid crystal device, 20, 120 LCD panel, 22 _nm TFT,
24 _nm liquid crystal capacitance, 26 _nm pixel electrode, 28 _nm counter electrode, 30, 130 Signal driver 50, 150 Scan driver, 60, 160 LCD controller,
80, 180 power supply circuit, 200, 210 interface unit,
280 I / O circuit area, 282 input terminal group, 284 output terminal group,
286 phase inversion circuit, 288 L / S, 400 _{1 to} 400 _Q input / output pad,
410 _{1 to} 410 _Q I / O circuit, 412 _j LV-LV buffer circuit,
414 _j LV-LV output buffer circuit, 416 _j LV-LV input buffer circuit,
418 _j LV-HV buffer circuit, 420 _j LV-HV output buffer circuit,
422 _j HV-LV input buffer circuit, 424 _j selector circuit,
426 _j G / A circuit, 430 selector line, 440 _j control circuit,
_{500 j, 504 j, 524 j} , 540 j, 544 j, 548 j, 552 j, 556 j, 560 j, 570 j inverter _{circuit, 502 j, 526 j, 542} j, 572 j EXOR circuit, 506 _j, 520 _{j, 550 j, 558 j LS} , 508 j, 522 j transfer _{circuit, 528 j, 532 j, 564} j, 576 j n -type _{transistor, 530 j, 562 j, 574} j p -type transistor, 546 _j NAND circuit, 554 _j NOR circuit

Claims (11)

A line driving circuit for driving the plurality of first lines of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A first terminal group signal group is inputted from the display controller for display control of the electro-optical device,
A second terminal group for outputting the signal group to a second line driving circuit for driving the plurality of second lines ;
The signal group input via said first terminal group, and I / O circuits including a circuit for outputting to the second terminal group,
A plurality of signal drive electrodes corresponding to the plurality of first lines;
Including
The I / O circuit group includes a plurality of I / O circuits,
A plurality of selector lines are commonly connected to each of the plurality of I / O circuits,
One of the I / O circuit of said plurality of I / O circuits,
Based on the first selection signal given Tokoro, a first selector circuit for the one of the first selector line among the first and one of the terminal groups of the plurality of selectors lines, connecting,
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
In plan view, the shape of the line drive circuit for driving the plurality of first lines, a rectangle and a second side facing the first side first side,
The plurality of signal drive electrodes are disposed along the first side,
The I / O circuits are line driver circuit, characterized by being arranged before SL along the second side. A line driving circuit for driving the plurality of first lines of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A first terminal group signal group is inputted from the display controller for display control of the electro-optical device,
A second terminal group for outputting the signal group to a second line driving circuit for driving the plurality of second lines ;
The signal group input via said first terminal group, and I / O circuits including a circuit for outputting to the second terminal group,
A plurality of signal drive electrodes corresponding to the plurality of first lines;
Including
The I / O circuit group includes a plurality of I / O circuits,
A plurality of selector lines are commonly connected to each of the plurality of I / O circuits,
Any one of the I / O circuits is:
Based on the first selection signal given Tokoro, a first selector circuit for the one of the first selector line among the first and one of the terminal groups of the plurality of selectors lines, connecting,
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
In plan view, the shape of the line drive circuit for driving the plurality of first lines, a rectangle and a second side facing the first side first side,
The plurality of signal drive electrodes are disposed along the first side,
The first terminal group includes a line driver circuit, characterized by being arranged along a central portion of the at least before Symbol second side. A line driving circuit for driving the plurality of first lines of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A chip substrate;
A first terminal group signal group is inputted from the display controller for display control of the electro-optical device,
A second terminal group for outputting the signal group to a second line driving circuit for driving the plurality of second lines ;
The signal group input via said first terminal group, and I / O circuits including a circuit for outputting to the second terminal group,
Internal circuitry,
Power supply wiring for supplying a power supply voltage to the internal circuit;
Including
The I / O circuit group includes a plurality of I / O circuits,
A plurality of selector lines are commonly connected to each of the plurality of I / O circuits,
One of the I / O circuit of said plurality of I / O circuits,
A first selector circuit for connecting any one of the first terminal groups and any one of the plurality of selector lines based on a given first selection signal;
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
In a plan view, the shape of the line driving circuit that drives the plurality of first lines includes a first side, a second side, a third side, and the third side that face the first side. A rectangle having an opposing fourth side;
A part of the power supply wiring is disposed along one of the first side, the second side, the third side, and the fourth side ,
The line driving circuit, wherein the I / O circuit group is formed in a layer between the chip substrate and a part of the power supply wiring . In any one of Claims 1 thru | or 3,
The line drive circuit, wherein the I / O circuit group includes a switching circuit for switching the second terminal group to any one of a plurality of given terminal groups. In any one of Claims 1 thru | or 4,
A first output buffer circuit for converting the voltage of the first selector line into a low withstand voltage system voltage and supplying the converted voltage to an output terminal;
A second output buffer circuit for converting the voltage of the first selector line into a high withstand voltage system voltage and supplying the converted voltage to an output terminal;
A first input buffer circuit for supplying a low withstand voltage voltage supplied to the input terminal to the first selector line while maintaining the low withstand voltage voltage;
A second input buffer circuit for converting a high voltage system voltage supplied to the input terminal into a low voltage system voltage and supplying the converted voltage to the first selector line;
Including
Any one of the first output buffer circuit, the second output buffer circuit, the first input buffer circuit, and the second input buffer circuit is set in an operating state, and the other buffer circuits are A line driving circuit characterized in that exclusive operation control for bringing into a non-operating state is performed. In claim 5,
At least one of the first output buffer circuit, the second output buffer circuit, the first input buffer circuit, and the second input buffer circuit outputs an output signal based on a given inversion control signal A line driving circuit comprising a phase inverting circuit for inverting the phase of an input signal. In claim 5 or 6,
An input terminal of the first output buffer circuit, an input terminal of the second output buffer circuit, an output terminal of the first input buffer circuit, and an output terminal of the second input buffer circuit are commonly connected. A line drive circuit comprising switching means inserted between one node and the first selector line. A line driving circuit for driving the plurality of first lines of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A first terminal group signal group is inputted from the display controller for display control of the electro-optical device,
A second terminal group for outputting a part of the signal group to a second line driving circuit for driving the plurality of second lines ;
An I / O circuit group including a circuit for outputting a part of the input signal group input via the first terminal group to the second terminal group;
A third terminal group for outputting the remainder of the signal group to the power supply circuit;
A plurality of signal drive electrodes corresponding to the plurality of first lines;
Including
The I / O circuit group includes a plurality of I / O circuits,
A plurality of selector lines are commonly connected to each of the plurality of I / O circuits,
Any one of the I / O circuits is:
Based on the first selection signal given Tokoro, a first selector circuit for the one of the first selector line among the first and one of the terminal groups of the plurality of selectors lines, connecting,
A second selector circuit for connecting any one of the second terminal groups and the first selector line based on a given second selection signal;
Including
In a plan view, the shape of the line driving circuit that drives the plurality of first lines includes a first side, a second side, a third side, and the third side that face the first side. A rectangle having an opposing fourth side;
The plurality of signal drive electrodes are disposed along the first side,
The second terminal group and the third terminal group are arranged along the second side, and one end of the second side and the fourth side from the center of the second side line driver circuit characterized in that one end are arranged in order of the second terminal group and the third group of terminals I toward the corner portion in contact with the. In claim 8,
Line the I / O circuit group, which comprises the second terminal group or the third group of terminals, a switching circuit for switching to one of the terminal groups of a given plurality of terminal groups Driving circuit. In any one of Claims 1 thru | or 9,
The line driving circuit according to claim 1, wherein the first line is a signal line to which a voltage based on image data is supplied. An electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A line driving circuit according to claim 10;
A second line driving circuit for driving the second line;
A display device comprising:

Images