JP2006079114A - Line driving circuit, electrooptical device, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a line driving circuit in which cost reduction by micronizing the process is efficiently conducted and to provide a electrooptical device and a display device using the circuit. <P>SOLUTION: A liquid crystal device 10 includes an LCD panel 20, a signal driver 30, a scanning driver 50, and a power supply circuit 80 and these are controlled by an LCD controller 60. The signal driver 30 includes an interface circuit which converts voltage of low breakdown system to the voltages of high breakdown system using a middle breakdown process in an interface section 200. The section 200 receives a signal group of a low breakdown system supplied from the controller 60, converts the group into voltages of the high breakdown system and supplies these voltages to the driver 50 or the circuit 80. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a line driving circuit, an electro-optical device using the same, and a display device.

  For example, a display panel such as a liquid crystal panel is used for a display unit of an electronic device such as a mobile phone, and the power consumption and size and weight of the electronic device are reduced. With respect to this display panel, when a still image or a moving image having high information properties is distributed due to the spread of mobile phones in recent years, higher image quality is required.

  An active matrix liquid crystal panel using a thin film transistor (hereinafter abbreviated as TFT) liquid crystal is known as a liquid crystal panel that realizes high image quality in the display unit of such an electronic device. In addition, an organic EL panel using an organic EL element is known.

  However, for example, in an active matrix liquid crystal panel using TFT liquid crystal, a high voltage is required for display driving depending on the liquid crystal material and the transistor capability of the TFT. For this reason, a driver circuit (line drive circuit) and a power supply circuit for driving the display of a liquid crystal panel or the like need to be manufactured by a high breakdown voltage process.

  Therefore, when the liquid crystal panel is driven for display, there is a problem that even if the process is miniaturized, the merit of cost reduction due to the miniaturization cannot be enjoyed.

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a line drive circuit that efficiently achieves cost reduction through process miniaturization and an electro-optical device using the same. It is to provide a display device.

  In order to solve the above-described problems, the present invention provides a line driving circuit that drives a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines that intersect each other. An input terminal to which a signal to be supplied to a second line driving circuit for driving the second line is input from a display controller that controls the display of the electro-optical device, and a signal input to the input terminal is determined. The circuit includes a level conversion circuit that shifts to a given voltage, and an output terminal that outputs the signal shifted to the given voltage to the second line driving circuit.

  Here, as the electro-optical device, for example, the first to Nth scanning lines and the first to Mth signal lines intersecting with each other, and the first to Nth scanning lines and the first to Mth signal lines are connected. It is also possible to have a configuration in which the switching means for the N pixels M and the pixel electrode for the N pixels M connected to the switching means are included. The electro-optical device may be an organic EL panel.

  According to the present invention, among the line driving circuit and the second line driving circuit that perform display driving in cooperation with the display controller under control of the pixels specified by the first and second lines, line driving is performed. In the circuit, a signal to be supplied from the display controller to the second line driving circuit is received and shifted to a given voltage, and then supplied to the second line driving circuit. Therefore, a signal to be supplied from a display controller having high versatility and a complicated circuit configuration to the second line driving circuit that requires high voltage driving necessary for display driving is relatively simple and inexpensive. It can be relayed by a line driving circuit manufactured by a simple process. This eliminates the need for the display controller to provide a high-breakdown-voltage interface circuit that is necessary for supplying a signal directly to the second line drive circuit. Therefore, the cost can be reduced.

  According to another aspect of the invention, there is provided a line driving circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines that intersect with each other. An input terminal to which a signal to be supplied to a power supply circuit is input from a display controller that performs display control, a level conversion circuit that shifts the signal input to the input terminal to a given voltage, and the given voltage And an output terminal for outputting the shifted signal to the power supply circuit.

  Here, the power supply circuit may have a function of supplying a multi-value voltage such as a grayscale voltage as well as a high-potential side voltage and a low-potential side voltage.

  According to the present invention, among the line drive circuit and the power supply circuit that perform display drive in cooperation with the display controller, the display is performed in the line drive circuit with respect to the pixels specified by the first and second lines. A signal to be supplied from the controller to the power supply circuit is received, shifted to a given voltage, and then supplied to the power supply circuit. Therefore, a signal that should be supplied from a display controller with high versatility and a complicated circuit configuration to a power supply circuit that requires high voltage drive necessary for display drive is manufactured by a relatively simple and inexpensive process. Can be relayed by a line driving circuit. This eliminates the need for the display controller to provide a high-breakdown-voltage interface circuit that is required for supplying signals directly to the power supply circuit, and reduces the costs associated with miniaturization through cutting-edge, low-breakdown microprocesses. Can be achieved.

  In the invention, it is preferable that the first line is a signal line to which a voltage based on image data is supplied.

  According to the present invention, for example, a signal to be supplied to each circuit is relayed by a signal driving circuit that drives a signal line. Thereby, the cost of the display controller that controls the signal driving circuit can be reduced.

  According to the present invention, a plurality of selector lines and a first selector line for connecting any one of the plurality of selector lines to the input terminal based on a given first selection signal. 1 selector circuit and a second selector circuit for connecting the output terminal and the first selector line based on a given second selection signal.

  According to the present invention, since the first and second selector circuits connect the input terminal and the output terminal via any one of the plurality of selector lines, any input terminal and output terminal can be connected. A plurality of combinations can be set. Accordingly, a signal from the display controller can be received at an arbitrary terminal of the line driving circuit, and a signal to be supplied can be output from the arbitrary terminal.

  The present invention also provides a first output buffer circuit that converts the voltage of the first selector line into a low-breakdown-voltage voltage and supplies the voltage to the output terminal; A second output buffer circuit that converts the voltage into a system voltage and supplies the voltage to the output terminal; and supplies the low voltage system voltage supplied to the input terminal to the first selector line while maintaining the low voltage system voltage. And a second input buffer circuit that converts a high voltage system voltage supplied to the input terminal into a low voltage system voltage and supplies the converted voltage to the first selector line. Exclusive operation control is performed so that any one of the first and second output buffer circuits and the first and second input buffer circuits is in an operating state and the other buffer circuits are in a non-operating state. It is characterized by There.

  According to the present invention, the first and second output buffer circuits and the first and second input buffer circuits supply the internal low voltage system voltage as it is as the low voltage system voltage or the high voltage system. Or a circuit that takes in a low withstand voltage or high withstand voltage from the outside as a low withstand voltage voltage can be provided for each terminal. Or it can set to an output terminal. Thereby, a user's usability can be improved significantly.

  In addition, the electro-optical device according to the present invention drives the pixels specified by the plurality of first lines and the plurality of second lines intersecting each other, the line driving circuit described above, and the second line. And a second line driving circuit.

  According to the present invention, it is possible to provide an electro-optical device that can realize cost reduction of a display controller by miniaturization of a process.

  According to another aspect of the invention, there is provided a display device including: an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other; the line driving circuit according to any one of the above; And a second line driving circuit for driving the other line.

  ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which can implement | achieve cost reduction of a display controller by refinement | miniaturization of a process can be provided.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. 1. Display Device 1.1 Configuration of Display Device FIG. 1 shows an outline of the configuration of a display device including a line driving circuit in the present embodiment.

  A liquid crystal device 10 as a display device includes a liquid crystal display (hereinafter abbreviated as LCD) panel 20, a signal driver (signal driving circuit, line driving circuit) (a source driver in a narrow sense) 30, a scanning driver ( It includes a scanning drive circuit (gate driver in a narrow sense) 50, an LCD controller (display controller in a broad sense) 60, and a power supply circuit 80.

The LCD panel (electro-optical device in a broad sense) 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of scanning lines arranged in the Y direction and extending in the X direction (in the narrow sense, gate lines) (second lines) G _{1 to} G _N (N is a natural number of 2 or more), A plurality of signal lines (in a narrow sense, source lines) (first lines) S _{1 to} S _M (M is a natural number of 2 or more) arranged in the X direction and extending in the Y direction are arranged. The TFT 22 _nm (switching means in a broad sense) corresponds to the intersection of the scanning line G _n (1 ≦ n ≦ N, n is a natural number) and the signal line S _m (1 ≦ m ≦ M, m is a natural number). ) Is provided.

The gate electrode of the TFT 22 _nm is connected to the scanning line G _n . The source electrode of the TFT 22 _nm is connected to the signal line S _m. A drain electrode of the TFT 22 _nm is connected to a pixel electrode 26 _nm of a liquid crystal capacitor (liquid crystal element in a broad sense) 24 _nm .

In the liquid crystal capacitance 24 _nm , liquid crystal is sealed between the counter electrode 28 _nm facing the pixel electrode 26 _nm and the transmittance of the pixel changes according to the applied voltage between these electrodes. Yes.

The counter electrode voltage Vcom generated by the power supply circuit 80 is supplied to the counter electrode 28 _nm .

The signal driver 30 drives the signal lines S _{1 to} S _M of the LCD panel 20 based on the image data of one horizontal scanning unit.

  More specifically, the signal driver 30 sequentially latches the serially input image data to generate image data for one horizontal scanning unit. The signal driver 30 drives each signal line with a driving voltage based on the image data in synchronization with the horizontal synchronizing signal.

The scan driver 50 sequentially scans and drives the scan lines G _{1 to} G _N of the LCD panel 20 in synchronization with the horizontal synchronizing signal within one vertical scanning period.

  More specifically, the scan driver 50 has a flip-flop corresponding to each scan line, and has a shift register in which the flip-flops are sequentially connected. The scan driver 50 sequentially selects the scan lines within one vertical scan period by sequentially shifting the vertical synchronization signals supplied from the LCD controller 60.

  The LCD controller 60 controls the signal driver 30, the scan driver 50, and the power supply circuit 80 according to the contents set by a host such as a central processing unit (CPU) (not shown). More specifically, the LCD controller 60 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the signal driver 30 and the scan driver 50, and supplies to the power supply circuit 80. Supplies the polarity inversion timing of the counter electrode voltage Vcom.

  The power supply circuit 80 generates a voltage level necessary for driving the liquid crystal of the LCD panel 20 and a counter electrode voltage Vcom based on a reference voltage supplied from the outside. Such various voltage levels are supplied to the signal driver 30, the scan driver 50, and the LCD panel 20. The counter electrode voltage Vcom is supplied to a counter electrode provided to face the pixel electrode of the TFT of the LCD panel 20.

  In the liquid crystal device 10 having such a configuration, the signal driver 30, the scanning driver 50, and the power supply circuit 80 cooperate to display and drive the LCD panel 20 based on image data supplied from outside under the control of the LCD controller 60. To do.

  In FIG. 1, the liquid crystal device 10 includes the LCD controller 60, but the LCD controller 60 may be provided outside the liquid crystal device 10. Alternatively, a host may be included in the liquid crystal device 10 together with the LCD controller 60.

1.2 Liquid Crystal Drive Waveform FIG. 2 shows an example of the drive waveform of the LCD panel 20 of the liquid crystal device 10 having the above-described configuration. Here, a case of driving by a line inversion driving method is shown.

  In the liquid crystal device 10, the signal driver 30, the scan driver 50, and the power supply circuit 80 are controlled according to the display timing generated by the LCD controller 60. The LCD controller 60 sequentially transfers the image data of one horizontal scanning unit to the signal driver 30 and supplies the internally generated horizontal synchronization signal and the polarity inversion signal POL indicating the inversion driving timing. In addition, the LCD controller 60 supplies an internally generated vertical synchronization signal to the scan driver 50. Further, the LCD controller 60 supplies the common electrode voltage polarity inversion signal VCOM to the power supply circuit 80.

  Thereby, the signal driver 30 drives the signal line based on the image data of one horizontal scanning unit in synchronization with the horizontal synchronizing signal. The scan driver 50 sequentially scans the scan lines connected to the gate electrodes of the TFTs arranged in a matrix on the LCD panel 20 with the drive voltage Vg using the vertical synchronization signal as a trigger. The power supply circuit 80 supplies the internally generated counter electrode voltage Vcom to each counter electrode of the LCD panel 20 while performing polarity inversion in synchronization with the counter electrode voltage polarity inversion signal VCOM.

The liquid crystal capacitor is charged with a charge corresponding to the voltage Vcom between the pixel electrode connected to the drain electrode of the TFT and the counter electrode. When the pixel electrode voltage Vp held by the charge accumulated in the liquid crystal capacitor exceeds a given threshold value _VCL , an image can be displayed. When the pixel electrode voltage Vp exceeds a given threshold value _VCL , the transmittance of the pixel changes according to the voltage level, and gradation expression becomes possible.

2. By the way, in the liquid crystal device, the voltage required for display driving differs for each semiconductor device (LCD controller, signal driver, scan driver, power supply circuit).

  FIG. 3 shows an example of the connection relationship between the semiconductor devices constituting the liquid crystal device.

  Here, the value of the power supply voltage level of signals transmitted and received between the semiconductor devices is also shown.

  The LCD panel 120, the signal driver 130, the scanning driver 150, the LCD controller 160, and the power supply circuit 180 that constitute the liquid crystal device 100 have the same functions as the respective components that constitute the liquid crystal device 10 shown in FIG.

  For example, since the circuit configuration of the signal driver 130 is not so complicated, the signal driver 130 is manufactured not by a state-of-the-art miniaturization process but by a medium withstand voltage process (for example, a 0.35 μ process) that can achieve both integration and cost reduction. The

  Further, since the scan driver 150 has a simple circuit configuration, it is not required to reduce the chip size, and the scan driver 150 has a high voltage (for example, 20 V to 50 V) determined by the relationship between the liquid crystal material and the transistor capability of the TFT. Is manufactured by a high withstand voltage process.

  Further, the power supply circuit 180 is manufactured by a high withstand voltage process in order to generate a high voltage supplied to the scan driver 150.

  On the other hand, since the LCD controller 160 has a complicated circuit configuration and high versatility, the cost can be further reduced by reducing the chip size. Therefore, the LCD controller 160 is manufactured by a state-of-the-art miniaturization process (for example, a 0.18 μ process). That is, since the LCD controller 160 is manufactured in a low withstand voltage process, it has both an interface circuit for a low withstand voltage process and an interface circuit for a high withstand voltage process.

  The interface circuit for the low withstand voltage process supplies a signal generated at the power level of the miniaturization process with the low withstand voltage to the signal driver 130 manufactured in the medium withstand voltage process. The high-breakdown-voltage process interface circuit supplies a signal converted to a high-breakdown-voltage process power supply level to the scan driver 150 and the power supply circuit 180 manufactured in the high-breakdown-voltage process.

  Thus, the LCD controller 160 includes an interface circuit for a high voltage process. The above-described interface circuit for a high withstand voltage process cannot reduce the area in the IC because the physical limit value for ensuring the withstand voltage exists in the design rule even if the process is miniaturized. Therefore, the merit of cost reduction by miniaturization cannot be enjoyed much.

  On the other hand, in the liquid crystal device 10 according to the present embodiment, a signal group to be supplied from the LCD controller 60 manufactured by the low breakdown voltage process to the scan driver 50 and the power supply circuit 80 manufactured by the high breakdown voltage process. The signal driver 30 is once relayed by the signal driver 30 manufactured by the medium withstand voltage process, and the signal driver 30 supplies these signal groups to the scanning driver 50 and the power supply circuit 80.

  FIG. 4 shows an example of the connection relationship of each semiconductor device constituting the liquid crystal device in this embodiment.

  As described above, the signal driver 30 according to the present embodiment includes the interface circuit that converts the low withstand voltage system voltage into the high withstand voltage system voltage using the medium withstand voltage process in the interface unit 200. A voltage group is received and converted into a high voltage with a high breakdown voltage, and then supplied to the scan driver 50 or the power supply circuit 80.

  By doing so, the interface unit 210 of the LCD controller 60 does not need to be provided with an interface circuit that drives a high voltage. Therefore, with the miniaturization of the process, the circuit of a complicated configuration is reduced and the cost is reduced. It becomes possible to plan.

2.1 Principle Configuration of the Present Embodiment FIG. 5 shows the principle configuration of the signal driver 30 in the present embodiment.

The signal driver 30 includes I / O circuits 300 _{1 to} 300 _P (P is a natural number), and an input terminal 310 _i and an output corresponding to the I / O circuit 300 _i (1 ≦ i ≦ P, i is a natural number). A terminal 320 _i is provided.

The I / O circuit 300 _i includes a level conversion circuit (Level Shifter: hereinafter abbreviated as L / S) 302 _i for converting a low withstand voltage system voltage into a high withstand voltage system voltage.

The L / S 302 _i converts the voltage of the low withstand voltage signal input from the input terminal 310 _i into a high withstand voltage system voltage and supplies it to the output terminal 320 _i . Accordingly, the input terminals 310 _{1 to} 310 _P are connected to the LCD controller 60 manufactured by the low withstand voltage process, and the output terminals 320 _{1 to} 320 _P are connected to either the scan driver 50 or the power supply circuit 80 manufactured by the high withstand voltage process. By connecting, the cost can be reduced by miniaturization of the LCD controller 60.

3. Signal driver (line drive circuit) in this embodiment
Hereinafter, such a signal driver (line driving circuit) 30 will be described in detail.

  FIG. 6 shows an outline of the configuration of the signal driver 30 in the present embodiment.

The signal driver 30 has input / output pads 400 _{1 to} 400 _Q (Q is a natural number) provided corresponding to each terminal of the semiconductor device.

The signal driver 30 further includes an I / O circuit 410 _j corresponding to the input / output pad 400 _j (1 ≦ j ≦ Q, j is a natural number). One or a plurality of selector lines 430 are commonly connected to the I / O circuits 410 _{1 to} 410 _Q. In the following, it is assumed that there are 16 selector lines.

The I / O circuit 410 _j includes a plurality of input buffer circuits and a plurality of output buffer circuits, and functions as either an input I / O circuit or an output I / O circuit according to a given selection signal. It has become. For example, when the I / O circuit 410 ₁ is set as an input I / O circuit and the I / O circuit 410 _Q is set as an output I / O circuit, a signal input via the input / output pad 400 ₁ is given by by the first selection signal, the I / O circuits 410 ₁ of the selector circuit, is outputted to one of the selector line 430 (first selector line). At this time, the input high-voltage or low-voltage signal is converted into a low-voltage voltage level.

In the I / O circuit 410 _Q , the first selector line and the input / output pad 410Q are electrically connected by the selector circuit according to a given second selection signal. At this time, the signal that has passed through the first selector line is converted to a voltage level of a high withstand voltage system or a low withstand voltage system.

  In this way, a signal from an arbitrary input terminal can be level-converted to a given voltage and output from an arbitrary output terminal.

FIG. 7 schematically shows a layout image of the I / O circuit 410 _j described above.

I / O circuit _{410 j (1 ≦ j ≦ Q} ) is output pad 400 _j electrically connected to the LV (Low Voltage) -LV buffer circuit _{412 j, LV-HV (High} Voltage) buffer circuit 418 _j , A selector circuit 424 _j and a gate array (hereinafter abbreviated as G / A) circuit 426 _j .

The LV-LV buffer circuit 412 _j includes an LV-LV output buffer circuit 414 _j and an LV-LV input buffer circuit 416 _j .

The LV-LV output buffer circuit (first output buffer circuit) 414 _j buffers the input / output voltage of the low withstand voltage (LV) signal with a buffer circuit connected to the LV power supply voltage level. This circuit outputs to the pad 400 _j .

The LV-LV input buffer circuit (first input buffer circuit) 416 _j is a buffer circuit in which the voltage of the LV signal input through the input / output pad 400 _j is connected to the LV power supply voltage level. This is a circuit for buffering and outputting to the selector circuit 424 _j .

The LV-HV buffer circuit 418 _j includes an LV-HV output buffer circuit 420 _j and an HV-LV input buffer circuit 422 _j .

The LV-HV output buffer circuit (second output buffer circuit) 420 _j is a circuit that converts the voltage of the LV signal into the voltage of the HV signal and outputs it to the input / output pad 400 _j .

The HV-LV input buffer circuit (second input buffer circuit) 422 _j is a buffer circuit in which the voltage of the HV signal input via the input / output pad 400 _j is connected to the LV power supply voltage level. This is a circuit for buffering and outputting to the selector circuit 424 _j .

The selector circuit 424 _j is one of the LV-LV output buffer circuit 414 _j , the LV-LV input buffer circuit 416 _j , the LV-HV output buffer circuit 420 _j , and the HV-LV input buffer circuit 422 _j. 430 is a circuit for connecting any one of 430.

The G / A circuit 426 _{j excludes any one} of the LV-LV output buffer circuit 414 _j , the LV-LV input buffer circuit 416 _j , the LV-HV output buffer circuit 420 _j , and the HV-LV input buffer circuit 422 _j. It is a logic circuit that generates a control signal for controlling the operation and a selection signal for the selector circuit 424 _j .

Such an I / O circuit 410 _j includes an LV-LV output buffer circuit 414 _j , an LV-LV input buffer circuit 416 _j , an LV-HV output buffer circuit 420 _j , and an HV-LV input by a G / A circuit 426 _j . Only one of the buffer circuits 422 _j is controlled exclusively. That is, the input buffer circuit and the output buffer circuit that are not selected are controlled so that at least their outputs are in a high impedance state. The selected input buffer circuit or output buffer circuit is electrically selected as one of the selector lines selected by the G / A circuit 426 _j . The selected selector line is electrically connected to the input / output pad via another I / O circuit.

  In this way, an I / O circuit and an input / output pad are arbitrarily selected, and these selected I / O circuits are electrically connected via a selector line, whereby an LV system is connected between arbitrary terminals. Alternatively, the voltage of the HV signal can be converted and output.

Incidentally, as shown in FIG. 7, A-A line, B-B line, along either line C-C, for example, Al is disconnects the input-output pads 400 _j deposited, electrically from each other By forming separate pads, the LV and HV signal interface functions may be provided in the I / O circuit 410 _j .

FIG. 8 shows an outline of an example of the circuit configuration of the I / O circuit 410 _j .

The input / output pad 400 _j includes an output terminal of the LV-LV output buffer circuit 414 _j, an input terminal of the LV-LV input buffer circuit 416 _j, an output terminal of the LV-HV output buffer circuit 420 _j , and an HV-LV input buffer circuit 422. _It is electrically connected to the _j input terminal.

The input terminal of the LV-LV output buffer circuit 414 _j , the output terminal of the LV-LV input buffer circuit 416 _j , the input terminal of the LV-HV output buffer circuit 420 _j , and the output terminal of the HV-LV input buffer circuit 422 _j are switches. It is electrically connected to a node ND as one end of the circuit SWA.

The other end of the switch circuit SWA is connected via a selector circuit 424 _j that a selector switch SW1～SW16, are connected to the selector line SL1～SL16.

The control signals SB1 to SB4 that exclusively control each buffer circuit, the switch control signal SA that performs on / off control of the switch circuit SWA, and the selection signals SEL1 to SEL16 that selectively select the selector switches SW1 to SW16 are: , Generated by the control circuit 440 _j . The control circuit 440 _j is configured by G / A as shown in FIG. The control circuit 440 _j generates control signals SB1 to SB4 and selection signals SEL1 to SEL16 according to the setting contents by a host (not shown).

The switch circuit SWA reduces output loads of the LV-LV input buffer circuit 416 _j and the HV-LV input buffer circuit 422 _j by electrically disconnecting each buffer circuit and the selector switches SW1 to SW16. Therefore, it is possible to reduce the size of the LV-LV input buffer circuit 416 _j and the HV-LV input buffer circuit 422 _j .

In the present embodiment, the LV-LV output buffer circuit 414 _j , the LV-LV input buffer circuit 416 _j , the LV-HV output buffer circuit 420 _j , and the HV-LV input buffer circuit 422 _j are used together with the control signals SB1 to SB4. the inversion control signal INV1~INV4 supplied from the control circuit 440 _j, inverted (reversed phase) the logic level of the input signal, and is capable of outputting.

  Hereinafter, a specific configuration example of each buffer circuit will be described.

  Here, it is assumed that the LV power supply voltage is VCC, the HV power supply voltage is VDD, and the ground level is VSS. For example, an inverted signal of the control signal CONT is expressed as XCONT.

FIG. 9 shows an example of the circuit configuration of the LV-LV output buffer circuit 414 _j .

The LV-LV output buffer circuit 414 _j includes inverter circuits 500 _j and 504 _j , an exclusive OR (hereinafter abbreviated as EXOR) circuit 502 _j , and a level shifter (hereinafter abbreviated as LS) 506. _j and transfer circuit 508 _j .

The LS 506 _j and the transfer circuit 508 _j are configured by HV transistors. The inverter circuits 500 _j and 504 _j and the EXOR circuit 502 _j are composed of LV transistors. In the HV transistor, for example, the oxide film thickness of the LV transistor is formed thicker to improve the high voltage resistance. Therefore, the design rule of the HV transistor must be looser than the design rule of the LV transistor, and the circuit area becomes large.

The LS 506 _j converts the potential difference between the control signal SB1 and its inverted signal XSB1 into an HV system voltage, and controls the on / off of the transfer circuit 508 _j .

Input node ND is connected to an input node of inverter circuit 500 _j .

An input node and an output node of the inverter circuit 500 _j are connected to the EXOR circuit 502 _j . The EXOR circuit 502 _j calculates an exclusive OR of the inversion control signal INV1 and the logic level of the input node ND, and the result is supplied to the input node of the inverter circuit 504 _j .

The output node of the inverter circuit 504 _j is connected to the input / output pad 400 _j via the transfer circuit 508 _j .

In this manner, the LV-LV output buffer circuit 414 _j arbitrarily inverts the logic level of the input node ND by the inversion control signal INV1. The output node is connected to the input / output pad 400 _j via the HV transfer circuit 508 _j . As a result, the HV system voltage is erroneously supplied to the input / output pad 400 _j , and the reliability can be maintained without destroying the LV system transistor. Further, since the logic level can be arbitrarily inverted by the inversion control signal INV1, it is possible to avoid a design change accompanying a change in the external interface specification and shorten the development period.

FIG. 10 shows an example of the circuit configuration of the LV-LV input buffer circuit 416 _j .

The LV-LV input buffer circuit 416 _j includes an LS 520 _j , a transfer circuit 522 _j , an inverter circuit 524 _j , and an EXOR circuit 526 _j .

The LS 520 _j and the transfer circuit 522 _j are configured by HV transistors. The inverter circuit 524 _j and the EXOR circuit 526 _j are composed of LV transistors.

LS520 _j includes a control signal SB2 the potential difference between the inverted signal XSB2 converted into a voltage of the HV controls the transfer circuit 522 _j of on or off.

Through such a transfer circuit 522 _j , the input / output pad 400 _j is connected to an inverter circuit 524 _j constituted by an LV transistor.

An n-type transistor 528 _j is connected between the input node of the inverter circuit 524 _j and the ground level VSS. An inverted signal XSB2 of the control signal SB2 is supplied to the gate electrode of the n-type transistor 528 _j . Therefore, when the inverted signal XSB2 is “H”, the LV-LV input buffer circuit 416 _j is in a non-selected state, and therefore the voltage of the input node of the inverter circuit 524 _j is set to the ground level VSS via the n-type transistor 528 _j. It can be fixed, and the through current of the inverter circuit 524 _j in the non-selected state is reduced.

An input node and an output node of the inverter circuit 524 _j are connected to the EXOR circuit 526 _j . EXOR circuit 526 _j includes an inversion control signal INV2, calculates the exclusive OR between the logical level of the input node of the inverter circuit 524 _j, the result is a logical level of the node ND.

The EXOR circuit 526 _j is connected to the LV power supply voltage VCC via the p-type transistor 530 _j and to the ground level VSS via the n-type transistor 532 _j . The gate electrode of the p-type transistor 530 _j, an inverted signal XSB2 supplied to the gate electrode of the n-type transistor 532 _j, the control signal SB2 is supplied.

Therefore, when the LV-LV input buffer circuit 416 _j is in the selected state, the node ND outputs the above-described exclusive OR operation result, and when in the non-selected state, the node ND is in the high impedance state.

As described above, the LV-LV input buffer circuit 416 _j receives the signal from the input / output pad 400 _j by the HV transfer circuit 522 _j and arbitrarily inverts the logic level by the EXOR circuit 526 _j . As a result, even if an HV voltage is accidentally supplied to the input / output pad 400 _j , reliability is not impaired, and an LV voltage can be supplied to the node ND. In addition, since the logic level can be arbitrarily reversed by the inversion control signal INV2, it is possible to avoid a design change accompanying a change in external interface specifications and to shorten a development period.

FIG. 11 shows an example of the circuit configuration of the LV-HV output buffer circuit 420 _j .

The LV-HV output buffer circuit 420 _j includes inverter circuits 540 _j and 544 _j and an EXOR circuit 542 _j . The LV-HV output buffer circuit 420 _j includes a NAND circuit 546 _j , inverter circuits 548 _j , 552 _j , and LS550 _j . Further, the LV-HV output buffer circuit 420 _j includes a NOR circuit 554 _j , inverter circuits 556 _j , 560 _j , and LS 558 _j .

In the LV-HV output buffer circuit 420 _j , the drain terminals of the HV-HV output buffer circuit 420 _j are connected between the HV power supply voltage VDD and the ground level VSS in order to perform high impedance control on the output to the input / output pad 400 _j . A p-type transistor 562 _j and an n-type transistor 564 _j are connected.

The inverter circuits 540 _j , 544 _j , 548 _j , 556 _j , the EXOR circuit 542 _j , the NOR circuit 546 _j , and the NAND circuit 554 _j are configured by LV transistors. The LS 550 _j , 558 _j , the inverter circuits 552 _j , 560 _j , the p-type transistor 562 _j , and the n-type transistor 564 _j are composed of HV transistors.

Input node ND is connected to an input node of inverter circuit 540 _j .

An input node and an output node of the inverter circuit 540 _j are connected to the EXOR circuit 542 _j . The EXOR circuit 542 _j calculates the exclusive OR of the inversion control signal INV3 and the logic level of the input node ND, and the result is supplied to the input node of the inverter circuit 544 _j .

An output node of the inverter circuit 544 _j is connected to the NOR circuit 546 _j and the NAND circuit 554 _j .

The NOR circuit 546 _j calculates the inverted logical sum (NOR) of the logic level of the control signal SB3 and the logic level of the output node of the inverter circuit 544 _j , and supplies the result to the input node of the inverter circuit 548 _j .

The NAND circuit 554 _j calculates an inverted logical product (NAND) of the logic level of the control signal SB3 and the logic level of the output node of the inverter circuit 544 _j and supplies the result to the input node of the inverter circuit 556 _j .

The LS 550 _j converts the potential difference between the input node and the output node of the inverter circuit 548 _j into an HV system voltage, and supplies it to the input node of the inverter circuit 552 _j configured by the HV system transistor. The output node of the inverter circuit 552 _j is connected to the gate electrode of the p-type transistor 562 _j .

The LS 558 _j converts the potential difference between the input node and the output node of the inverter circuit 556 _j into an HV system voltage, and supplies it to the input node of the inverter circuit 560 _j configured by the HV system transistor. The output node of inverter circuit 560 _j is connected to the gate electrode of n-type transistor 564 _j .

In this manner, the LV-HV output buffer circuit 420 _j arbitrarily inverts the logic level of the input node ND by the inversion control signal INV3. Also, the gate control signal generated by the output node and the control signal SB3, and converts the voltage of the HV system by LS550 _j, 558 _j, so as to control the p-type transistor 562 _j and n-type transistor 564 _j Yes.

  Thereby, the logic level can be arbitrarily inverted by the inversion control signal INV3, so that the design change accompanying the change of the external interface specification can be avoided, and the development period can be shortened. Also provided is an output buffer circuit capable of level-converting an LV voltage to an HV voltage and controlling the output of the voltage with a high impedance.

FIG. 12 shows an example of the circuit configuration of the HV-LV input buffer circuit 422 _j .

The HV-LV input buffer circuit 422 _j includes an inverter circuit 570 _j and an EXOR circuit 572 _j .

  The inverter circuit 570j is configured by an HV transistor, and an LV power supply voltage VCC is supplied as a power supply voltage level.

The input / output pad 400 _j is connected to the input node of the inverter circuit 570 _j . Thus, when the voltage of the LV signal is supplied to the input / output pad 400 _j , the inverter circuit 570 _j detects this signal and generates an inverted signal at the output node.

An input node and an output node of the inverter circuit 570 _j are connected to the EXOR circuit 572 _j . EXOR circuit 572 _j includes an inversion control signal INV4, calculates the exclusive OR between the logical level of the output pad 400 _j, the result is a logical level of the node ND.

The EXOR circuit 572 _j is connected to the LV power supply voltage VCC via a p-type transistor 574 _j and to the ground level VSS via an n-type transistor 576 _j . The gate electrode of the p-type transistor 574 _j, an inverted signal XSB4 supplied to the gate electrode of the n-type transistor 576 _j, the control signal SB4 is supplied.

Therefore, when the HV-LV input buffer circuit 422 _j is in the selected state, the node ND outputs the above-described exclusive OR operation result, and when in the non-selected state, the node ND is in the high impedance state.

In this way, the HV-LV input buffer circuit 422 _j receives the signal from the input / output pad 400 _j by the HV inverter circuit 570 _{j to} which the LV power supply voltage VCC is connected, and the EXOR circuit 526 _j has a logic level. Is reversed arbitrarily. As a result, even if an HV voltage is accidentally supplied to the input / output pad 400 _j , reliability is not impaired, and an LV voltage can be supplied to the node ND. In addition, since the logic level can be arbitrarily reversed by the inversion control signal INV2, it is possible to avoid a design change accompanying a change in external interface specifications and to shorten a development period.

As described above, the control circuit 440 _j that exclusively controls the various buffer circuits generates the control signals SB1 to SB4, the selection signals SEL1 to SEL16, and the switch control signal SA.

FIG. 13 shows an example of the circuit configuration of the control circuit 440 _j .

The control circuit 440 _j generates the control signals SB1 to SB4, the selection signals SEL1 to SEL16, and the switch control signal SA described above by setting a given command register using the LCD controller 60, for example.

  For example, the data bus D7-D0 is held in the flip-flop bit by bit in synchronization with the address decode pulse generated when the LCD controller 60 accesses a given command register and the clock signal CK. . Each flip-flop is set and reset by, for example, bit data corresponding to initial data S7 to S0 for initial state setting or an inverted reset signal XRES. In this case, the initial state can be collectively set by fixing the initial data S7-S0 to the power supply voltage or the ground level by Al switching.

Thus, the data held in each flip-flop is decoded and output by the decoder circuit as control signals SB1 to SB4. With such a control circuit 440 _j , the selector circuit 424 _j can select one arbitrary selector line among the selector lines 430, and the operation of the four buffer circuits can be exclusively controlled.

  The output load can be reduced by electrically disconnecting the buffer circuit and the selector line as appropriate by the switch control signal SA.

  Further, the inversion control signals INV1 to INV4 can be generated similarly.

4). FIG. 14 shows an outline of the configuration of the liquid crystal device 10 to which the signal driver in this embodiment is applied.

  4 identical to those in FIG. 4 are assigned the same reference numerals as in FIG.

  The LCD controller 60 transmits a clock signal CPH, a latch pulse LP as a horizontal synchronization signal, a command signal CMD for designating a command, an inverted signal INV, image data and command data to the signal driver 30. Data D0 to D17, a polarity inversion signal POL as a polarity inversion drive timing, an output enable signal OE, an enable input / output signal EIO, and an inversion reset signal XRESH are supplied to perform signal drive control.

  In addition, the LCD controller 60 provides the scan driver 50 with a clock signal CPV, a start signal STV as a vertical synchronization signal, an inverted output enable signal XOEV, an output control signal XOHV that controls the output of all scanning lines, and an inverted reset signal XRESV. The scanning drive control can be performed. In the present embodiment, control signals to be supplied from the LCD controller 60 to the scan driver 50 are relayed by the signal driver 30 having the I / O circuit as described above, and after level conversion, the control signal is sent to the scan driver 50. In contrast, it is designed to supply.

  Further, the LCD controller 60 supplies a standby control signal XSTBY, a boost mode setting signal PMDE, primary and secondary boost system clocks PCK1, PCK2, and a polarity inversion signal VCOM of the counter electrode voltage to the power supply circuit 80, Power supply control can be performed. In the present embodiment, the control signal to be supplied from the LCD controller 60 to the power supply circuit 80 is relayed by the signal driver 30 having the I / O circuit as described above, and after level conversion, the control signal is supplied to the power supply circuit 80. In contrast, it is designed to supply.

  In this way, in the LCD controller 60 having a more complicated circuit configuration, it is not necessary to provide an HV interface circuit, and level conversion is performed by the signal driver 30 manufactured by a medium withstand voltage process that does not require miniaturization. I went and relayed it. Therefore, the LCD controller 60 has high versatility, and the cost can be significantly reduced by reducing the chip size by the miniaturization process.

5. Others In the present embodiment, a liquid crystal device provided with an LCD panel using TFT liquid crystal has been described as an example. However, the present invention is not limited to this. For example, the present invention can also be applied to a signal driver and a scan driver that display-drive an organic EL panel including an organic EL element provided corresponding to a pixel specified by a signal line and a scan line.

  FIG. 15 shows an example of a two-transistor pixel circuit in an organic EL panel whose display is controlled by such a signal driver and scan driver.

The organic EL panel has a driving TFT 800 _nm , a switch TFT 810 _nm , a holding capacitor 820 _nm, and an organic LED 830 _{nm at} the intersection of the signal line S _m and the scanning line G _n . The driving TFT 800 _nm is configured by a p-type transistor.

The driving TFT 800 _nm and the organic LED 830 _nm are connected in series to the power supply line.

Switch TFT 810 _nm has a gate electrode of the driving TFT 800 _nm, it is inserted between the signal line S _m. The gate electrode of the switching TFT 810 _nm is connected to the scanning line G _m.

The holding capacitor 820 _nm is inserted between the gate electrode of the driving TFT 800 _nm and the capacitor line.

In such an organic EL element, when the scanning line G _n is driven and the switch TFT 810 _nm is turned on, the voltage of the signal line S _m is written to the holding capacitor 820 _nm and applied to the gate electrode of the driving TFT 800 _nm . The gate voltage Vgs of the driving TFT 800 _nm is determined by the voltage of the signal line S _m, the current flowing through the driving TFT 800 _nm is determined. Since the driving TFT 800 _nm and the organic LED 830 _nm are connected in series, the current flowing through the driving TFT 800 _nm becomes the current flowing through the organic LED 830 _{nm as} it is.

Therefore, by holding the gate voltage Vgs corresponding to the voltage of the signal line S _m by the hold capacitor 820 _nm, for example, during one frame period, by flowing a current corresponding to the gate voltage Vgs to the organic LED 830 _nm, the frame A pixel that continues to shine can be realized.

  FIG. 16A shows an example of a 4-transistor pixel circuit in an organic EL panel whose display is controlled by the signal driver and scan driver described above. FIG. 16B shows an example of the display control timing of this pixel circuit.

Again, the organic EL panel includes a drive TFT 900 _nm, a switch TFT 910 _nm, a storage capacitor 920 _nm, and an organic LED 930 _nm.

The difference from the two-transistor pixel circuit shown in FIG. 15 is that a constant current Idata from a constant current source 950 _nm is supplied to the pixel via a p-type TFT 940 _nm as a switching element instead of a constant voltage. The point is that the power supply line is connected to the holding capacitor 920 _nm and the driving TFT 900 _nm via the p-type TFT 960 _nm as a switching element.

In such an organic EL element, first, the p-type TFT 960 is turned off by the gate voltage Vgp to cut off the power supply line, the p-type TFT 940 _nm and the switch TFT 910 _nm are turned on by the gate voltage Vsel, and the constant current source 950 _nm A constant current Idata is passed through the driving TFT 900 _nm .

Until the current flowing through the driving TFT 900 _nm is stabilized, the holding capacitor 920 _nm holds a voltage corresponding to the constant current Idata.

Then, turn off the p-type TFT 940 _nm and the switch TFT 910 _nm by the gate voltage Vsel, further to turn on the p-type TFT 960 _nm by the gate voltage Vgp, to electrically connect the driving TFT 900 _nm and the organic LED 930 _nm and a power supply line. At this time, the voltage held in the hold capacitor 920 _nm, or approximately equal to the constant current Idata, or the magnitude of the current corresponding thereto is supplied to the organic LED 930 _nm.

  In such an organic EL element, for example, the scanning line can be configured as a gate voltage Vsel and the signal line can be configured as a data line.

  In the organic LED, a light emitting layer may be provided on the transparent anode (ITO), and a metal cathode may be provided on the light emitting layer. A light emitting layer, a light transmitting cathode, and a transparent seal may be provided on the metal anode. However, the present invention is not limited to the element structure.

  By configuring the signal driver for displaying and driving the organic EL panel including the organic EL element as described above as described above, the display controller for controlling the display of the organic EL panel can be miniaturized.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention can be applied to a plasma display device.

  In this embodiment, the signal driver is described as an example of the line drive circuit, but the present invention is not limited to this.

It is a block diagram which shows the outline | summary of a structure of the display apparatus containing the line drive circuit in this embodiment. It is explanatory drawing which shows an example of the drive waveform of the LCD panel of the liquid crystal device in this embodiment. It is explanatory drawing which shows an example of the connection relation of each semiconductor device which comprises a liquid crystal device as a comparative example. It is explanatory drawing which shows an example of the connection relation of each semiconductor device which comprises the liquid crystal device in this embodiment. It is a block diagram which shows the fundamental structure of the signal driver in this embodiment. It is a block diagram which shows the outline | summary of the structure of the signal driver in this embodiment. It is a schematic diagram which shows typically the layout image of the I / O circuit of the signal driver in this embodiment. It is a block diagram which shows the outline | summary of an example of a circuit structure of the I / O circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the LV-LV output buffer circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the LV-LV input buffer circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the LV-HV output buffer circuit in this embodiment. It is a circuit diagram which shows an example of the circuit structure of the HV-LV input buffer circuit in this embodiment. It is a block diagram which shows an example of the circuit structure of the control circuit in this embodiment. It is explanatory drawing which shows the outline | summary of a structure of the liquid crystal device to which the signal driver in this embodiment was applied. It is a circuit diagram which shows an example of the pixel circuit of a 2 transistor system in an organic electroluminescent panel. FIG. 16A is a circuit diagram illustrating an example of a four-transistor pixel circuit in an organic EL panel. FIG. 16B is a timing diagram illustrating an example of display control timing of a four-transistor pixel circuit.

Explanation of symbols

10, 100 liquid crystal device, 20, 120 LCD panel, 22 _nm TFT,
24 _nm liquid crystal capacitance, 26 _nm pixel electrode, 28 _nm counter electrode,
30, 130 signal driver, 50, 150 scan driver,
60, 160 LCD controller, 80, 180 power supply circuit,
200, 210 _{interface, 300 1 ~300 P, 410 1} ~410 Q I / O circuit,
302 _{1 to} 302 _P level conversion circuit (L / S), 310 _{1 to} 310 _P input terminals,
320 _{1 to} 320 _P output terminal, 400 _{1 to} 400 _Q input / output pad,
412 _j LV-LV buffer circuit, 414 _j LV-LV output buffer circuit,
416 _j LV-LV input buffer circuit, 418 _j LV-HV buffer circuit,
420 _j LV-HV output buffer circuit, 422 _j HV-LV input buffer circuit,
424 _j selector circuit, 426 _j G / A circuit, 430 selector line,
440 _j control circuit,
_{500 j, 504 j, 524 j} , 540 j, 544 j, 548 j, 552 j, 556 j, 560 j, 570 j inverter _{circuit, 502 j, 526 j, 542} j, 572 j EXOR circuit,
506 _j , 520 _j , 550 _j , 558 _j LS, 508 _j , 522 _j transfer circuit 528 _j , 532 _j , 564 _j , 576 _j n-type transistor,
530 _j , 562 _j , 574 _j p-type transistor, 546 _j NAND circuit,
554 _j NOR circuit

Claims (5)

A line driving circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other,
An input terminal to which a signal to be supplied to a second line driving circuit for driving the second line is input from a display controller that controls the display of the electro-optical device;
A level conversion circuit that shifts a signal input to the input terminal to a given voltage;
An output terminal for outputting the signal shifted to the given voltage to the second line driving circuit;
A line driving circuit comprising: A line driving circuit for driving a first line of an electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other,
An input terminal to which a signal to be supplied to the power supply circuit is input from a display controller that controls the display of the electro-optical device;
A level conversion circuit that shifts a signal input to the input terminal to a given voltage;
An output terminal for outputting the signal shifted to the given voltage to the power supply circuit;
A line driving circuit comprising: In claim 1 or 2,
The line driving circuit according to claim 1, wherein the first line is a signal line to which a voltage based on image data is supplied. Pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A line driving circuit according to any one of claims 1 to 3,
A second line driving circuit for driving the second line;
An electro-optical device comprising: An electro-optical device having pixels specified by a plurality of first lines and a plurality of second lines intersecting each other;
A line driving circuit according to any one of claims 1 to 3,
A second line driving circuit for driving the second line;
A display device comprising:

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