KR20080057460A - Data driver of fpd and driving method of the same - Google Patents

Abstract

A data driver of a flat panel display device and a driving method thereof are provided to reduce current loss by maintaining a first source voltage of a first node constant. A data driver of a flat panel display device includes a display panel, a shift register for outputting a sampling pulse, first and second latches, and a DAC(Digital to Analog Converter). The first latch includes a level shifter(201), a sampling unit(203), a first switching unit(204), an inverter(207), and a second switching unit(208). The level shifter adjusts a data signal, sampled at the first latch, to a voltage of a specific driving level by synchronizing with the sampling pulse. The sampling unit inverts and samples the data signal. The first switching unit determines output timing of the data signal by synchronizing with the sampling pulse and the inverted sampling pulse. The inverter re-inverts the sampled data signal. The second switching unit determines output timing of the sampled data signal by synchronizing with an enable signal.

Description

Data driver of flat panel display and its driving method {Data driver of FPD and driving method of the same}

1 is a block diagram schematically illustrating a structure of a general liquid crystal display device.

2 is a block diagram schematically illustrating a configuration of a liquid crystal display device using a general polysilicon substrate.

3 is an equivalent circuit diagram showing a part of a data driver.

4 is a block diagram schematically illustrating a data driver of a flat panel display device according to an exemplary embodiment of the present invention.

5A is a block diagram schematically illustrating a structure of a first latch of a data driver in a flat panel display according to an exemplary embodiment of the present invention.

5B is an equivalent circuit diagram of FIG. 5A.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driver of a flat panel display device and a driving method thereof. More particularly, the present invention relates to a data driver of a flat panel display device which reduces power consumption of a data driver mounted on a display panel and reduces an area occupied by a circuit. It relates to a driving method.

Recently, the flat panel display device is becoming thinner and larger in size as its industrial use is greatly increased. Plasma display panel (PDP), liquid crystal display (LCD), etc. I am in the limelight.

Plasma display devices generate light with plasma characteristics according to voltages applied to phosphors interposed between partition walls and glass substrates. On the other hand, the liquid crystal display is a device that displays the light generated by the backlight unit by controlling the amount of light through the shutter function of the liquid crystal and belongs to the light receiving display device. Plasma display displays have a problem in expressing natural images because gradation is expressed due to digital data voltages. However, liquid crystal displays display natural images in comparison with plasma display displays because analog voltage is applied to both ends of the liquid crystal. Can be.

In addition, the above-mentioned liquid crystal display device has low power consumption, and can be thinned and implemented on a large screen, and thus has been spotlighted as a next-generation high-end display device having high added value as a display device such as a notebook computer or a large screen TV.

In the following description, it will be described as an example of a liquid crystal display device which is in the spotlight in recent years among flat panel display devices.

FIG. 1 is a block diagram schematically illustrating a structure of a general liquid crystal display device, which corresponds to a liquid crystal panel 10 displaying an image and a gate / data corresponding to a control signal and a data signal supplied from an external system (not shown). A timing controller 20 generates a control signal and rearranges the data signal, and gates and data drivers 30 and 50 driving the liquid crystal panel 10.

In the liquid crystal panel 10, a plurality of gate lines GL and data lines DL are arranged to intersect in a matrix form, and the intersection points are defined as pixel regions, and one end of the pixel region is a liquid crystal capacitor LC. It includes a thin film transistor (T) connected to.

The timing controller 20 receives a plurality of control signals and data signals from an external system (not shown), generates a gate control signal corresponding thereto, and supplies the same to the gate driver 30.

In addition, data control signals are generated in response to the control signals, the data signals are rearranged in a form that the data driver 50 can process, and the data signals are supplied to the data driver 50.

 The gate driver 30 sequentially supplies gate driving signals to the liquid crystal panel 10 by the horizontal lines through the gate line GL in response to the gate control signal, thereby causing a pixel on the liquid crystal panel 10 to be removed. Make sure that the horizontal lines are selected.

Whenever the gate line GL is sequentially selected, the data driver 50 corresponds to the data control signal and the rearranged data signal, and outputs an image signal containing image information through the data line DL. To 10).

Accordingly, in the liquid crystal panel 10, the thin film transistor T provided in response to the scan signal is turned on, and the data signal is supplied to the pixel electrode connected thereto. Accordingly, the light transmittance of the liquid crystal layer is controlled by an electric field formed between the pixel electrode and the common electrode.

Hydrogenated amorphous silicon (a-Si: H; hereinafter, amorphous silicon) is mainly used for the semiconductor layer of the thin film transistor T in the liquid crystal display device having such a configuration. This is because it is possible to use a low-cost insulating substrate because deposition is possible at a lower substrate temperature of 350 ° C or lower.

However, the above-mentioned amorphous silicon has a problem in that its characteristics are deteriorated by light irradiation, and it is difficult to use in a driving circuit due to the electrical characteristics of the TFT (low field effect mobility: 0.1 to 1.0 cm 2 / V · s) and a decrease in reliability. .

Therefore, the amorphous silicon thin film transistor substrate connects the insulated substrate and the printed circuit board (PCB) by using a tape carrier package (TCP) driving IC (Intergrated Circuit), which consumes a large part of the cost for the driving IC and the actual equipment. do.

In addition, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate line and the data line of the thin film transistor substrate with the TCP becomes short, which makes TCP bonding itself difficult.

Accordingly, a method of using polysilicon (P-si; Polycrystalline-Silicon, hereinafter polysilicon) as a semiconductor layer of a TFT has been proposed. Since polysilicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. If the driving circuit is directly made of polysilicon on a substrate, the driving IC cost can be reduced and the mounting is simplified. As a result, the entire system can be mounted in a panel (System On Panel, hereinafter referred to as SOP method).

FIG. 2 is a block diagram schematically illustrating a configuration of a liquid crystal display using a general polysilicon substrate, and includes a liquid crystal panel 10 in which gates and data drivers 30 and 50 are mounted. ) Is a display area 12 in which two substrates are bonded to each other, a thin film transistor T is formed to display an image, and a non-display area 14 in which the gate and data drivers 30 and 50 and signal wiring are formed. Separated by.

More specifically, the display area 12 is formed by crossing a plurality of gate lines GL and data lines DL in a matrix form, and a point where the gate lines GL and data lines DL intersect. The thin film transistor T is provided.

The gate driver 30 and the data driver 50 receive a scan signal and a data signal from the outside to control the thin film transistor T of the display area 12 through the gate line GL and the data line DL. By changing the light transmittance of the liquid crystal.

In addition, although not shown, a timing controller (not shown) and a power supply unit are mounted on a separate PCB substrate and connected to the liquid crystal panel 10 and a driver mounted thereon, and a backlight unit (not shown) is also provided on the liquid crystal panel 10. Is provided on the back side.

Although not shown, the above-described data driver includes a plurality of shift registers, latches, and output buffers.

FIG. 3 is an equivalent circuit diagram showing a part of the data driver, in which the first and second latches and the output buffer are shown.

Referring to the drawings, a conventional data driver receives a sampling pulse SP from a shift register (not shown), and a static memory for sampling and temporarily storing a data signal DATA. A first latch 54 having an SRAM structure, an output buffer 56 for stably outputting the sampling data signal of the first latch 54 to the second latch 58, and the sampling data signal temporarily A second latch 58 is included to store and output simultaneously to all data lines (not shown).

Here, the reason why the first latch 52 is implemented in the SRAM structure is that a stable driving characteristic is required, and in particular, a refresh for maintaining the data signal during temporary storage is not required.

However, the SRAM structure has a disadvantage in that the circuit area, in particular, the vertical area is large in implementing a circuit, which causes the data driver to occupy a large area on the liquid crystal panel in a limited space.

The present invention has been made to solve the above problems, the object of the present invention is to provide a data driver and a driving method thereof of a flat panel display device by reducing the circuit area and power consumption by changing the structure of the data driver. have.

In order to realize the above technical problem, a data driver of a flat panel display device according to an embodiment of the present invention includes a display panel, a shift register mounted on one end of the display panel and sequentially outputting sampling pulses, and a data signal. A data driver of a flat panel display device comprising a first latch for sampling, a second latch for temporarily storing the data signal, and a DAC for converting the data signal into an analog type video signal, wherein the first latch comprises: A level shifter unit for adjusting the data signal to a voltage of a specific driving level in synchronization with the sampling pulse; A sampling unit for inverting and sampling the data signal; A first switching unit configured to determine an output timing of the data signal in synchronization with the sampling pulse and the inverting sampling pulse; An inverter for reversing the sampled data signal; And a second switching unit configured to determine an output timing of the sampled data signal in synchronization with an enable signal.

The level shifter may include: a first transistor having a gate electrode connected to a second power supply voltage terminal, and a source electrode connected to a first power supply voltage terminal; And a second transistor connected to an input terminal of the sampling pulse, a source electrode connected to a data signal terminal, and a drain electrode interposed between an N1 node and a drain electrode of the first transistor. do.

The sampling unit includes: a third transistor having a gate electrode connected to the N1 node, and a source electrode connected to the first power supply voltage terminal; And a fourth transistor having a gate electrode connected to the N1 node, a source electrode connected to the second power supply voltage terminal, and a drain electrode interposed between the N2 node and the drain electrode of the third transistor. It is done.

The first switching unit includes: a fifth transistor having a gate electrode connected to an inverting sampling pulse input terminal and a source electrode connected to the N2 node (N2); A gate electrode is connected to the sampling pulse input terminal, and a source electrode includes a sixth transistor connected to the N2 node (N2).

The inverter is characterized in that the input terminal is connected to the drain electrode of the fifth and sixth transistor.

The second switching device may include a seventh transistor having a gate electrode connected to an enable signal input terminal, a source electrode connected to an output terminal of the inverter, and a drain electrode connected to the second latch.

According to an aspect of the present invention, there is provided a method of driving a flat panel display data driver, the method including: level shifting the data signal in synchronization with the sampling pulse; Inverting and sampling the data signal that is level shifted; Re-inverting the sampled inverted data signal in synchronization with the sampling pulse and the inverted sampling pulse; And outputting the sampled data signal to the second latch in synchronization with an enable signal.

Level shifting the data signal in synchronization with the sampling pulse may include outputting a first power supply voltage when the sampling pulse is not input; And level shifting the data signal when the sampling pulse is input.

Hereinafter, a data driver and a driving method thereof of a flat panel display device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram schematically illustrating a data driver of a flat panel display device according to an exemplary embodiment of the present invention.

As shown, the data driver of the flat panel display according to the embodiment of the present invention includes a plurality of shift registers 152 that sequentially generate sampling pulses SP, and are input according to the sampling pulses SP. A plurality of first latches 154 for sampling the data signal DATA, a second latch 158 for temporarily storing and simultaneously outputting the outputs of the plurality of first latches 154, and the digital form And a data analog converter (DAC) 159 for converting the sampling data signal of the digital signal into an analog form and outputting the sample data signal to the data line DL.

Referring to the drawings, the operation of the data driver 154 of the flat panel display device according to the present invention will be described. The sampling of the shift register 152 from the first latch 154 by the digital data signal DATA input from the outside is described. Sampling is performed in synchronization with the pulse SP, and is temporarily stored until all data signals DATA of one horizontal line are sampled.

Thereafter, the sampled data signal DATA is input to the second latch 158 at one time by the enable signal OE. The sampled data signal DATA input to the second latch 158 is in a digital form, which is input to the DAC 159 and converted into an analog image signal, which is displayed through each data line DL. Supplied to a panel (not shown).

5A is a block diagram schematically illustrating a structure of a first latch of a data driver in a flat panel display according to an exemplary embodiment of the present invention, and FIG. 5B is an equivalent circuit diagram of FIG. 5A.

Hereinafter, a first latch of a data driver according to an embodiment of the present invention will be described with reference to FIGS. 5A and 5B.

As illustrated, the first latch 154 includes a level shifter 201, a sampling unit 103, first and second switching units 204 and 208, and an inverter unit 207.

The level shifter 201 adjusts an input data signal to a specific level. The level shifter 201 may be provided at an input terminal or an output terminal of a circuit, but in general, configuring a level shifter at an input terminal of a circuit reduces the area of a circuit. Since it is possible to do this, it is preferable to provide in the input terminal of the 1st latch 154.

The level shifter 201 adjusts the data signal to a specific level in response to the sampling pulse SP of the shift register 152 of FIG.

The sampling unit 203 samples the data signal input to the level shifter unit 201 in an inverted form.

The first switching unit 204 is a circuit dependent on the type of the level shifter 201 and may be omitted, and adjusts the output timing of the sampled data signal.

The inverter 207 inverts the sampled data signal of the inverted form again.

The second switching unit 208 outputs the sampled signal to the second latch 158 in synchronization with the enable signal.

With this structure, the area occupied by the data driver can be reduced through the first latch replacing the existing SRAM structure.

Hereinafter, the structure of the first latch will be described in detail with reference to the equivalent circuit diagram of the first latch.

The first latch 154 includes a plurality of transistors T1 to T7 and one inverter I1.

The first, third, and fifth transistors T1, T3, and T5 of the plurality of transistors T1 to T7 are P-channel metal oxide semiconductors (PMOS), and second, fourth, sixth, The seventh transistors T2, T4, T6, and T7 are implemented with N-channel metal oxide semiconductors (NMOS).

More specifically, in the first transistor T1, a gate electrode is connected to the second power supply voltage GND terminal, a source electrode is connected to the first power supply voltage VDD terminal, and a drain electrode is connected to the N1 node N1. Connected.

In the second transistor T2, the gate electrode is connected to the output terminal of the shift register 152 of FIG. 4 to receive the sampling pulse SP, the source electrode is connected to the data signal DATA terminal, and the drain electrode is the N1 node. Is connected to (N1).

As described above, when the level shifter is provided at the input terminal of the circuit, this structure compensates for the large current consumption.

More specifically, the general level shifter turns on the gate electrodes of the PMOS and NMOS transistors in which the drain electrodes are connected to the same node at the same time, thereby turning on one source electrode selected from the PMOS and NMOS transistors. In the structure of level shifting the input signal, when the signal is not applied to the gate electrode, since the same node is in a floating state, there is a consumption of current consumption during turn-on / off.

In order to improve this, in the embodiment of the present invention, when the data signal is not applied by connecting the gate electrode of the second transistor T2, which is the PMOS transistor, to the second power supply voltage GND, the N1 node N1 Since the first power supply voltage VDD is always maintained, the consumption of current consumption is eliminated.

In the third and fourth transistors T3 and T4, the gate electrode is connected to the N1 node N1, the source electrode is connected to the first and second power supply voltages VDD and GND, respectively, and the drain electrode is It is connected to N2 node (N2).

In the fifth and sixth transistors T5 and T6, a gate electrode is connected to the sampling pulse SP terminal and an inverted sampling pulse SPB terminal, and a source electrode is connected to the N2 node N2, and a drain electrode. Is connected to the input terminal of the inverter I1.

Here, the fifth and sixth transistors T5 and T6 are elements provided to complement the first transistor T1.

More specifically, since the first transistor T1 is always turned on, this is a state in which a high level signal is input from a data sampling point of view, which is actually sampled. Since it is not a data signal, the fifth and sixth transistors T5 and T6 are controlled by the sampling pulses SP and the inverting sampling pulses SPB so that a data signal having a high level is actually input. Only the signal output structure.

The inverter I1 has an output terminal connected to the source electrode of the seventh transistor T7.

In the seventh transistor T7, the gate electrode is connected to the enable signal OE terminal, and the drain electrode is connected to the input terminal of the second latch 158 of FIG. 4.

Hereinafter, an operation of the data driver first latch in the flat panel display according to the exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

As shown, the first transistor T1 is always in a turn-on state because the conductivity type is P-type. In addition, when the sampling pulse SP is input to the gate electrode of the second transistor T2 from the shift register 152 of FIG. 4 and turned on, the voltage of the N1 node N1 becomes third. The voltage (VDD-DATA) is in a state.

Subsequently, the voltage of the N1 node N1 is applied to the gate electrodes of the third and fourth transistors T3 and T4, thereby inverting the voltage of the N1 node N1, and in this case, the fifth and sixth transistors T5, Since T6 is turned on in synchronization with the sampling pulse SP and the inverting sampling pulse SPB, T6 is again inverted through the next inverter I1 and output.

Thereafter, according to the enable signal OE, the output voltage is input to the second latch 158 of FIG. 4.

The liquid crystal display data driver according to the exemplary embodiment of the present invention performs the same operation as the conventional SRAM structure, and has a small area occupied by a circuit and low current consumption.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

The data driver of the flat panel display device according to the present invention replaces the first latch of the SRAM structure with a circuit of another structure that performs the same operation, and is easily mounted in a limited display panel. There is an effect of improving the waste of current consumption.

Claims (8)

A display panel, a shift register mounted on one end of the display panel and sequentially outputting a sampling pulse, a first latch for sampling the data signal, a second latch for temporarily storing the data signal, and the data signal A data driver of a flat panel display device including a DAC for converting an analog image signal, The first latch may include: a level shifter unit configured to adjust the data signal to a voltage of a specific driving level in synchronization with the sampling pulse; A sampling unit for inverting and sampling the data signal; A first switching unit configured to determine an output timing of the data signal in synchronization with the sampling pulse and the inverting sampling pulse; An inverter for reversing the sampled data signal; A second switching unit configured to determine an output timing of the sampled data signal in synchronization with an enable signal; Data driver of a flat panel display device comprising a. The method of claim 1, The level shifter may include: a first transistor having a gate electrode connected to a second power supply voltage terminal, and a source electrode connected to a first power supply voltage terminal; A second transistor having a gate electrode connected to an input terminal of the sampling pulse, a source electrode connected to a data signal terminal, a drain electrode interposed between the N1 node, and a drain electrode of the first transistor; Data driver of a flat panel display device comprising a. The method of claim 2, The sampling unit includes: a third transistor having a gate electrode connected to the N1 node, and a source electrode connected to the first power supply voltage terminal; A fourth transistor having a gate electrode connected to the N1 node, a source electrode connected to the second power supply voltage terminal, a drain electrode interposed between the N2 node, and a drain electrode of the third transistor; Data driver of a flat panel display device comprising a. The method of claim 3, wherein The first switching unit includes: a fifth transistor having a gate electrode connected to an inverting sampling pulse input terminal and a source electrode connected to the N2 node (N2); A sixth transistor having a gate electrode connected to the sampling pulse input terminal and a source electrode connected to the N 2 node N 2; Data driver of a flat panel display device comprising a. The method of claim 4, wherein The inverter, And an input terminal of the input terminal is connected to drain electrodes of the fifth and sixth transistors. The method of claim 5, wherein The second switching device may include: a seventh transistor having a gate electrode connected to an enable signal input terminal, a source electrode connected to an output terminal of the inverter, and a drain electrode connected to the second latch; Data driver of a flat panel display device comprising a. In the driving method of a flat panel display data driver according to claim 1, Level shifting the data signal in synchronization with the sampling pulse; Inverting and sampling the data shifted level signal; Re-inverting the sampled inverted data signal in synchronization with the sampling pulse and the inverted sampling pulse; Outputting the sampled data signal to the second latch in synchronization with an enable signal; A method of driving a flat panel display data driver comprising a. The method of claim 7, wherein Level shifting the data signal in synchronization with the sampling pulse, Outputting a first power supply voltage when the sampling pulse is not input; Level shifting the data signal when the sampling pulse is input; A method of driving a flat panel display data driver comprising a.

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