KR20090131844A - Gate driving unit for liquid crystal display device - Google Patents

Abstract

PURPOSE: A gate driver for a liquid crystal display device is provided to reduce power consumption by driving only enable register selected when driving a partial mode of a liquid crystal display device. CONSTITUTION: A shift register is subordinately connected and outputs an output signal successively. One of a first clock signal and a first clock bar signal is inputted to the shift register. A plurality of enable registers are connected to the plurality of shift registers one-to-one and output the output signal according to the enable signal input. One of a second clock signal and a second clock bar signal is inputted to the plurality of enable registers. A partial controller(20) outputs the enable signal and select the enable register into which the enable signal, the second clock signal, and the second clock bar signal are inputted.

Description

Gate driving unit for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver for a liquid crystal display device, and more particularly, to a gate driver for a liquid crystal display device capable of reducing power consumption in partial mode driving in which only a part of an image is displayed on a display panel.

Among the display devices, in particular, liquid crystal displays have advantages of small size, thinness, and low power consumption, and are used as notebook computers, office automation devices, and audio / video devices. In particular, an active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switch element is suitable for displaying a dynamic image.

FIG. 1 is a block diagram illustrating a general liquid crystal display device 100. For the convenience of description, only the liquid crystal display panel 110, the plurality of source drivers SD1 to SD4, and the plurality of gate drivers GD1 to GD4. Shown.

The liquid crystal display panel 110 has a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn intersecting with each other, and a thin film transistor TFT and a liquid crystal capacitor Clc in the crossing region. And a storage capacitor Cst are defined as pixels P1 and P2.

The pixels are formed in a matrix form in each region where the plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn cross each other, and are arranged in a matrix form, and image data is written to the plurality of pixels to display an image. This area is called an active area (A / A).

The plurality of source drivers SD1 to SD4 output the image data D to the plurality of data lines DL1 to Dlm and provide the image data D to the liquid crystal display panel 110, thereby providing the plurality of gate drivers GD1 to SD4. GD4 sequentially outputs the gate driving signal Vg to each gate line GL1 to GLn to control switching of the thin film transistor TFT configured in each pixel so that the image data is written to the pixel to display an image. do.

Of course, the general liquid crystal display device provides image data and a plurality of control signals to the plurality of source driving units SD1 to SD4 in addition to the above-described configuration, and also provides the gate driving signals to the plurality of gate driving units GD1 to GD4. A timing controller for providing a plurality of control signals including a gate output enable (GOE) signal for indicating the output of Vg), a backlight unit for supplying light to the liquid crystal display panel 110, and an operating voltage of each component It further includes a power supply for providing.

Among these configurations, the gate drivers GD1 to GD4 have a partial mode such that only a part of the screen is displayed in a standby time other than the time when the actual image is displayed in order to reduce power consumption in a battery-powered electronic device such as a mobile phone. (Partial mode) It supports driving.

FIG. 2 is a block diagram of a gate driver for explaining partial mode driving according to the prior art, in which a clock signal CLK and a clock bar signal CLKB, which is an antiphase signal of the clock signal CLK, are cross-input and a start signal. First to fifth shift registers S / R1 to S / R5 that are first driven by Vst and sequentially output scan signals Vg1 to Vg5, and also the clock signal CLK and the clock bar. A first signal crossing the signal CLKB and receiving the output signals of the first to fifth shift registers S / R1 to S / R5 as start signals and finally outputting the scan signals Vg1 to Vg5. It consists of the enable register to the fifth enable register (ES / R1 to ES / R5). The clock signal CLK and the clock bar signal CLKB may be further divided into a plurality of signals, respectively, and generally use two to four clock signals and clock bar signals.

Of course, the shift registers S / R1 to S / R5 and the enable registers E-S / R1 to E-S / R5 have no limit in the number of configurations, and only five registers are illustrated in FIG. 2 as an example.

In this case, each of the first enable register to the fifth enable register ES / R1 to ES / R5 operates only when an enable signal Ven is applied from a partial controller: 10. 10) supplies the enable signal Ven only to the selected enable register when the partial mode is driven.

However, in the gate in panel (GIP) method in which the gate driver having the above-described configuration is mounted on the liquid crystal display panel, the shift registers S / R1 to S / R5 and the enable register ES / R1 are used. To thin film transistors formed at the output terminals of ES / R5) are configured to be different from each other.

That is, in each case of the first shift register to the fifth shift registers S / R1 to S / R5, the input terminal of the first enable register to the fifth enable register ES / R1 to ES / R5 (that is, the first shift register S / R1 to S / R5). The thin film transistor configured at the stud signal input stage ST has its output load, while each of the first to fifth enable registers ES / R1 to ES / R5 is a gate line and The entire liquid crystal display panel connected thereto has the output load.

Therefore, when each of the shift registers S / R1 to S / R5 and enable registers ES / R1 to ES / R5 is configured using an amorphous silicon thin film transistor having low charge mobility, the output load is different. Therefore, the size of the thin film transistors formed at the output terminals of the shift registers S / R1 to S / R5 and the enable registers ES / R1 to ES / R5 is several to several tens of times. / R5) The thin film transistor of the output stage should be large, which means that the parasitic capacitance of the thin film transistor is also increased proportionally.

Therefore, the power consumption of the enable registers E-S / R1 to E-S / R5 constituting a much larger thin film transistor is much higher than that of the shift registers S / R1 to S / R5.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the power consumption in the enable registers ES / R1 to ES / R5 requiring high power consumption, thereby enabling long-term operation of the gate for a liquid crystal display device. The purpose is to provide a drive.

In order to achieve the above object, the present invention comprises: a plurality of shift registers which are cascade-connected to sequentially output output signals, and one of the first clock signal and the first clock bar signal is input; A plurality of enable registers connected one-to-one to each of the plurality of shift registers, outputting the output signal according to an enable signal input, and receiving one of a second clock signal and a second clock bar signal; And a partial controller configured to output the enable signal and to select an enable register to which the enable signal, the second clock signal, and the second clock bar signal are input, from among the plurality of enable registers. Propose a gate driver.

In the gate driver of the liquid crystal display device, the shift register and the enable register may be identical to each other.

In the gate driver of the liquid crystal display device, the partial controller generates and outputs the second clock signal and the second clock bar signal.

In the gate driver of the liquid crystal display device, the partial controller generates and outputs the first clock signal and the first clock bar signal.

In the gate driver for the liquid crystal display device, an output signal output from the n th shift register is an n-1 th shift register, an n + 1 th shift register, an n th enable register and an n-2 th enable register. Characterized in that provided.

In the gate driver of the liquid crystal display device, the plurality of shift registers and the plurality of enable registers are configured on the same transparent substrate.

According to the present invention, the power consumption is greatly reduced by driving only the enable register selected in the partial mode driving of the liquid crystal display device, thereby driving the liquid crystal display device and the electronic device employing the same for a longer time. To help.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a gate driver for a liquid crystal display device according to an embodiment of the present invention, in which a first clock signal 1CLK and a first clock bar signal 1CLKB are cross-input and are started by a start signal Vst. First to fifth shift registers S / R1 to S / R5 that are initially driven to sequentially output scan signals Vg1 to Vg5, and second clock signal 2CLK and second clock bar signal 2CLKB. ) Is cross-input, the first enable register receiving the output signals of the first to fifth shift registers S / R1 to S / R5 as a start signal and finally outputting the scan signals Vg1 to Vg5. And fourth to fourth enable registers ES / R1 to ES / R4.

The clock bar signals 1CLKB and 2CLKB are anti-phase signals of the clock signals 1CLK and 2CLK, respectively, and each of the clock signal and the clock bar signal may be further divided into a plurality of signals. Four clock signals and corresponding clock bar signals are used.

In addition, the shift registers S / R1 to S / R5 and the enable registers ES / R1 to ES / R4 are substantially the same circuit, and the number of configurations thereof is not limited. The 5- and 4-stage shift registers and enable registers are exemplified.

In the connection between each register, the output signal (that is, Vg (n)) output from any n th shift register is provided as the start signal of the n-1 th shift register and the reset signal of the n + 1 th shift register. In addition, the start signal of the n-th enable register is provided and the reset signal of the n-2th enable register is provided.

Each of the first enable register to the fourth enable register ES / R1 to ES / R4 operates only when an enable signal Ven is applied from a partial controller 20. ) Supplies the enable signal Ven only to the selected enable register when the partial mode is driven.

Further, in the present invention, the first clock signal 1CLK and the second clock signal 2CLK may be the same or different signals, and accordingly, the first clock bar signal 1CLKB and the second clock bar signal ( 2CLKB) may also be the same or different signals, and different output sources of the first clock signal groups 1CLK and 1CLKB and the second clock signal groups 2CLK and 2CLKB are configured. That is, the outputs of the first clock signal groups 1CLK and 1CLKB and the second clock signal groups 2CLK and 2CLKB are controlled separately.

Accordingly, the first clock signal group 1CLK and 1CLKB and the second clock signal group 2CLK and 2CLKB may be configured to separate circuits, or when configured in the same circuit unit, the output terminals may be provided separately. Naturally, for example, a separate circuit may be configured to separately output the first clock signal group generation unit (not shown) and the second clock signal group generation unit (not shown) in the partial controller 20. Do.

Thus, the purpose of differently configuring the output source of the first clock signal group (1CLK, 1CLKB) and the second clock signal group (2CLK, 2CLKB) is to output the output signal of the second clock signal group (2CLK, 2CLKB). This is to provide only to the selected enable register, such as the enable signal Ven. That is, in order to reduce power consumption by driving only the selected enable registers without driving the entire enable registers ES / R1 to ES / R4, which are higher in power consumption than the shift registers S / R1 to S / R5. to be.

The shift registers S / R1 to S / R5 and the enable registers ES / R1 to ES / R4 may be driven separately according to the characteristics of the gate driver for the liquid crystal display device according to the present invention. Even when the first clock signal group 1CLK and 1CLKB are selected and provided to each of the shift registers S / R1 to S / R5 in the partial display mode driving that displays only a part of the screen, the enable register ES / R1 to ES / R4 provide signals of the enable signal Ven and the second clock signal groups 2CLK and 2CLKB only to the enable register selected according to the partial mode. Of course, the control for providing the selection may be provided by the partial controller 20.

Therefore, in the partial mode operation, only the enable register selected without driving the entire enable register (ES / R1 to ES / R4), which has a relatively high power consumption compared to the shift registers S / R1 to S / R5. By driving, the power consumption is greatly reduced.

1 is a block diagram illustrating a general liquid crystal display device 100.

2 is a block diagram illustrating a gate driver for explaining partial mode driving according to the related art.

3 is a block diagram showing the configuration of a gate driver for a liquid crystal display device according to the present invention;

<Brief description of the main parts of the drawing>

20: partial controller

S / R: Shift Register E-S / R: Enable Register

Claims (6)

A plurality of shift registers which are cascade-connected to sequentially output the output signals and to which one of the first clock signal and the first clock bar signal is input; A plurality of enable registers connected one-to-one to each of the plurality of shift registers, outputting the output signal according to an enable signal input, and receiving one of a second clock signal and a second clock bar signal; A partial controller configured to output the enable signal and to select an enable register to which the enable signal, the second clock signal, and the second clock bar signal are input among the plurality of enable registers; Gate driver for liquid crystal display device comprising a The method according to claim 1, And the shift register and the enable register are identical to each other. The method according to claim 1, The partial controller generates and outputs the second clock signal and the second clock bar signal. The method according to claim 3, The partial controller generates and outputs the first clock signal and the first clock bar signal. The method according to claim 1, And an output signal output from the n th shift register is provided to an n-1 th shift register, an n + 1 th shift register, an n th enable register, and an n-2 th enable register. Gate driver The method according to claim 1, The plurality of shift registers and the plurality of enable registers are formed on the same transparent substrate, the gate driver of the liquid crystal display device

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