JP4840211B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  When an electronic device such as a mobile phone is exposed to electrostatic discharge from a charged operator, a transistor of an integrated circuit device built in the electronic device may be electrostatically damaged. In order to prevent such electrostatic breakdown, the integrated circuit device is provided with a protection element for electrostatic breakdown.

On the other hand, the electrostatic discharge from the operator does not cause the electrostatic breakdown of the transistor, but a malfunction such as an abnormal display state of the display panel of the electronic device may occur. A test called an ESD immunity test (ElectroStatic Discharge immunity test) may be performed in order to inspect such malfunction caused by electrostatic discharge.
The ESD immunity test is a test for an electronic device that is exposed to electrostatic discharge from a charged operator directly or through a close object.

In recent years, as the manufacturing process of integrated circuit devices has become finer, the ESD immunity has become a problem of insufficient withstand voltage, and an integrated circuit device that does not malfunction even when an electronic device is exposed to electrostatic discharge. Offer is desired.
JP 2003-234647 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide an integrated circuit device capable of effectively preventing malfunction caused by electrostatic discharge or the like and an electronic apparatus including the integrated circuit device. Is to provide.

  The present invention provides an I / O circuit for buffering and outputting an input signal from a pad when an enable signal is at a second voltage level, and a circuit block to which an output signal from the I / O circuit is input And a first period in which the enable signal is at a first voltage level and a second period including a period in which the enable signal transitions from the first voltage level to the second voltage level. An output signal whose voltage level is set by the power source is output to the circuit block, and in the third period in which the enable signal becomes the second voltage level after the second period, the I The present invention relates to an integrated circuit device including a malfunction prevention circuit that outputs an output signal corresponding to an output signal from the / O circuit to the circuit block.

  In the present invention, the output signal from the I / O circuit is input to the circuit block via the malfunction prevention circuit. In this case, an output signal whose voltage level is set by the first power supply is input to the circuit block in the first and second periods, and an output corresponding to the output signal from the I / O circuit is input in the third period. A signal is input to the circuit block. Accordingly, even when noise is applied to the power source due to electrostatic discharge or the like, the voltage level of the output signal of the malfunction prevention circuit is maintained at the voltage level of the first power source, so that the integrated circuit device or the like is incorporated. Malfunctions of electronic devices can be prevented.

  In the present invention, the malfunction prevention circuit receives the enable signal and outputs a signal obtained by performing at least one of signal delay processing and filter processing on the enable signal as a second enable signal; The voltage level of the first power supply is input to the first input, the output signal from the I / O circuit is input to the second input, and the first, A selector that selects any one of the second inputs and outputs an output signal may be included.

  According to this configuration, in the second period including the transition period of the enable signal, the first input of the selector is selected, and the output signal whose voltage level is set by the first power supply is input to the circuit block. It becomes like this.

  In the present invention, the first power source may be a power source different from the power source supplied to the I / O circuit.

  In this way, even when noise or the like is applied to the power supply supplied to the I / O circuit, an output signal whose voltage level is set by the stable first power supply is input to the circuit block. .

  According to the present invention, when the enable signal is at the second voltage level, the first to Jth I-th buffers that buffer and output the first to J-th input signals from the first to Jth pads. / O circuit and in the first and second periods, the first to J-th output signals set to the voltage level by the first power supply are output to the circuit block, and in the third period, The first to Jth malfunction prevention circuits for outputting the first to Jth output signals corresponding to the output signals from the first to Jth I / O circuits to the circuit block may be included.

  In this way, it is possible to prevent a situation in which an erroneous signal is input to the circuit block due to noise such as electrostatic discharge for all of the first to Jth input signals.

  In the present invention, when each command for the integrated circuit device is assigned to each combination of signal levels of the first to Jth input signals from the first to Jth pads, the first The J-th malfunction prevention circuit outputs first to J-th output signals whose signal level combinations are not assigned to the command to the circuit block in the first and second periods. You may make it do.

  In this way, in the first and second periods, the first to Jth output signals of a combination to which no command is assigned are input to the circuit block, so that the command is erroneously written. The frequency can be reduced.

  The present invention also provides a Kth circuit block that outputs an output signal when the enable signal is at the second voltage level, and an Lth circuit block that receives an output signal from the Kth circuit block. In a first period in which the enable signal is at a first voltage level and a second period in which the enable signal transitions from the first voltage level to the second voltage level, An output signal whose voltage level is set by a power supply is output to the Lth circuit block, and is a period following the second period, and in a third period in which the enable signal is at the second voltage level, The present invention relates to an integrated circuit device including a malfunction prevention circuit that outputs an output signal corresponding to an output signal from the Kth circuit block to the Lth circuit block.

  In the present invention, the output signal from the Kth circuit block is input to the Lth circuit block via the malfunction prevention circuit. In this case, in the first and second periods, an output signal whose voltage level is set by the first power supply is input to the Lth circuit block, and in the third period, an output signal from the Kth circuit block. Is output to the Lth circuit block. Accordingly, even when noise is applied to the power source due to electrostatic discharge or the like, the voltage level of the output signal of the malfunction prevention circuit is maintained at the voltage level of the first power source, so that the integrated circuit device or the like is incorporated. Malfunctions of electronic devices can be prevented.

  In the present invention, the Kth circuit block may be a logic circuit block, and the Lth circuit block may be a power supply circuit block that is controlled by the logic circuit block to generate a power supply voltage.

  In this way, it is possible to prevent a situation in which the power supply circuit block generates an incorrect power supply voltage.

  In the present invention, the Kth circuit block is a logic circuit block, and the Lth circuit block is a gradation voltage generation circuit block that is controlled by the logic circuit block to generate a gradation voltage. Also good.

  In this way, it is possible to prevent a situation in which the gradation voltage generation circuit block generates an erroneous gradation voltage and the display characteristics deteriorate.

  In the present invention, the malfunction prevention circuit receives the enable signal and outputs a signal obtained by performing at least one of signal delay processing and filter processing on the enable signal as a second enable signal; The voltage level of the first power supply is input to the first input, the output signal from the Kth circuit block is input to the second input, and the first input is based on the second enable signal. And a selector that selects any one of the second inputs and outputs an output signal.

  According to this configuration, in the second period including the transition period of the enable signal, the first input of the selector is selected, and the output signal whose voltage level is set by the first power supply is input to the Lth circuit block. Will come to be.

  In the present invention, the K-th circuit block outputs an address signal, a data signal, and the enable signal to the L-th circuit block, and the malfunction prevention circuit performs the operation in the first and second periods. An address signal whose voltage level is set by a first power supply is output to the Lth circuit block. In the third period, an address signal corresponding to the address signal from the Kth circuit block is output to the Lth circuit block. It may be output to the circuit block.

  In this way, it is possible to prevent a situation in which a malfunction occurs due to an incorrect address signal setting.

  In the present invention, the malfunction prevention circuit may use an address signal that is not assigned in the normal operation mode as an address signal whose voltage level is set by the first power source in the first and second periods. It may be outputted to the L circuit block.

  In this way, the frequency of erroneous writing can be reduced.

  In the present invention, the K-th circuit block outputs an address signal, a data signal, and the enable signal to the L-th circuit block, and the malfunction prevention circuit performs the operation in the first and second periods. A data signal whose voltage level is set by a first power supply is output to the Lth circuit block, and in the third period, a data signal corresponding to the data signal from the Kth circuit block is output to the Lth circuit block. It may be output to the circuit block.

  In this way, it is possible to prevent a situation in which erroneous data signal data is transferred to the Lth circuit block and malfunction occurs.

  In the present invention, the direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is the first direction, and the second side is the long side of the integrated circuit device. When the direction toward the fourth side is the second direction, it includes first to Nth circuit blocks arranged along the first direction, and the first to Nth circuit blocks are , Including the Kth circuit block and the Lth circuit block (1 ≦ K <L ≦ N), and another circuit block is disposed between the Kth circuit block and the Lth circuit block. You may make it do.

  In the present invention, since the first to Nth circuit blocks are arranged along the first direction, a slim and elongated integrated circuit device can be provided. In the present invention, even when another circuit block is arranged between the Kth and Lth circuit blocks and the Kth and Lth circuit blocks are spaced apart, the malfunction prevention circuit prevents malfunction. Is done. Accordingly, it is possible to realize both a slim and long integrated circuit device and prevention of malfunction.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. ESD Immunity FIG. 1A conceptually shows an ESD immunity test for a display module 6 (electronic device in a broad sense) in which a display panel 8 and an integrated circuit device 10 (display driver) are incorporated. Various signals are input to the integrated circuit device 10 that drives the display panel 8 and power is supplied to the integrated circuit device 10 so as to be in an operating state. In this state, static electricity is applied to the display module 6 by the static electricity applying device 4. Specifically, an operation of applying a positive electrostatic test voltage (XkV) and then removing the charge is repeated a plurality of times (for example, 10 times). Next, the operation of applying a negative electrostatic test voltage (-XkV) and then removing the charge is repeated a plurality of times (for example, 10 times). When the test by these operations is cleared, the test voltage (XkV) is increased by, for example, 1 kV step, and the same test is performed.

  When an electrostatic test voltage is applied as shown in FIG. 1A, induced charges generated on the glass substrate of the display panel 8 and the liquid crystal capacitor CL are discharged to the GND side as shown in FIG. 1B. Specifically, the induced charges are discharged from the data line, the scanning line, and the counter electrode to the GND side via the integrated circuit device 10. As a result, the integrated circuit device 10 malfunctions and the display state of the display panel 8 becomes abnormal.

  For example, in FIG. 1C, the I / O (Input-Output) circuit 20 buffers the data signal D (input signal in a broad sense) from the pad 18 when the enable signal is at the H (High) level. To the internal circuit block 50. During the ESD immunity test, the voltage level of the data signal D is fixed at, for example, the H level. When an electrostatic test voltage is applied in this state, noise is applied to the power supply VDDI of the I / O circuit 20 as shown in FIG. As a result, although the enable signal is not H level (active), the H level of the data signal D passes through the circuit AND1 of the I / O circuit 20, and an incorrect data signal is input to the circuit block 50. . For example, if a software reset command is assigned to a combination of signal levels of the data signals D7 to D0 (for example, 00000001 = 01h), the software reset command is erroneously written. As a result, the integrated circuit device 10 is reset, and an abnormal state occurs such that no image is displayed on the display panel 8. For example, when a charged operator touches the screen of a mobile phone, an abnormal state occurs in which nothing is displayed on the display panel due to ESD. In order to recover from this abnormal state, it is necessary to re-input a power-on command or the like and execute a normal startup sequence, which hinders convenience.

2. Malfunction Prevention Circuit FIG. 2A shows a configuration example of an integrated circuit device of this embodiment that can solve the above problems. As shown in FIG. 2A, the integrated circuit device includes an I / O circuit 20, a malfunction prevention circuit 30, and a circuit block 50.

  Here, the I / O (Input-output) circuit 20 has a data signal D from the pad 18 (electrode) when the enable signal ENB (input control signal) is at the H level (second voltage level in a broad sense). Buffer the (input signal) and output the output signal QI. The I / O circuit 20 (I / O cell) may include at least an input buffer circuit, may be an input-only I / O circuit, or may be an input / output I / O circuit. Good.

  The circuit block 50 is an internal circuit of the integrated circuit device and receives an output signal QI (QP) from the I / O circuit 20. Examples of the circuit block 50 include a logic circuit block configured by an automatic wiring method such as G / A (gate array).

  The malfunction prevention circuit 30 is a circuit that prevents malfunction due to external noise such as static electricity. Specifically, as shown in FIG. 2B, the malfunction prevention circuit 30 has a power supply VDDC (in a broad sense) in a period T1 in which the enable signal is at an L (Low) level (a first voltage level in a broad sense). An output signal QP whose voltage level is set by the first power source is output to the circuit block 50. In addition, in the period T2 (period following T1) including the transition period in which the enable signal ENB transitions from the L level (first voltage level) to the H level (second voltage level), the voltage level is set by the power supply VDDC. The output signal QP is output to the circuit block 50. For example, the H level output signal QP which is the voltage level of the power supply VDDC is output to the circuit block 50. The period T2 is, for example, a period from when the signal ENB changes from L level to H level until a given time (delay time by the delay element) elapses. 2A and 2B, the malfunction prevention circuit 30 outputs the H level output signal QP in the periods T1 and T2. However, the L level output signal QP may be output.

  On the other hand, the malfunction prevention circuit 30 outputs the output signal QP corresponding to the output signal QI from the I / O circuit 20 to the circuit block 50 in the period T3 in which the enable signal ENB is at the H level following the period T2. To do. For example, when the signal QI is at the L level, the L level signal QP is output, and when the signal QI is at the H level, the H level signal QP is output. Note that the malfunction prevention circuit 30 may output an inverted signal of the voltage level of the signal QI as the signal QP. In this case, the I / O circuit 20 may output an inverted signal of the signal D. The malfunction prevention circuit 30 may be a circuit included in the I / O circuit 20 or the circuit block 50. The enable signal ENB may be a negative logic signal.

  If such a malfunction prevention circuit 30 is provided, the voltage level of the output signal QP of the malfunction prevention circuit 30 is the voltage of the power supply VDDC even when noise is applied to the power supply VDDI as shown in FIG. The level is maintained (H level). That is, as shown in FIG. 2C, even when the relative voltage level of the signal ENB changes transiently, the malfunction prevention circuit 30 causes the influence of the transient voltage level change to the circuit block 50. It will not be transmitted. Accordingly, it is possible to prevent a situation in which a command / parameter such as a software reset command is erroneously written due to noise such as an external surge. As a result, an integrated circuit device and an electronic device with high ESD immunity can be provided.

  In FIG. 2A, the power supply VDDC supplied to the malfunction prevention circuit 30 is different from the power supply VDDI supplied to the I / O circuit 20. Therefore, even when noise is applied to the power supply VDDI due to ESD as shown in FIG. 1D, the signal QP can be set to a stable voltage level of the power supply VDDC, and the malfunction can be prevented more reliably. In particular, in FIG. 2A, the power supply VDDC is the power supply for the circuit block 50. The circuit block 50 includes a large number of transistors, and the source capacitance of these transistors is parasitic on the power supply VDDC. Therefore, noise applied to the power supply VDDC when ESD is applied is reduced compared to the power supply VDDI, and the signal QP can be set to a more stable voltage level. It is possible to supply the same power as the power supplied to the I / O circuit 20 to the malfunction prevention circuit 30.

3. Detailed Configuration FIG. 3A shows a detailed configuration example of the I / O circuits 20 and 22 and the malfunction prevention circuit 30. Note that the configurations of the I / O circuit and the malfunction prevention circuit are not limited to those in FIG. 3A, and various modifications such as omitting some of the components in FIG. 3A and adding other components. Implementation is possible.

  Each of the I / O circuits 20 and 22 includes buffer circuits BUF1 and BU2 that function as output buffers. Circuits AND1 and AND2 functioning as input buffers are also included. These I / O circuits 20 and 22 are I / O circuits for both input and output. However, the I / O circuits 20 and 22 may not be provided with the circuits BUF1 and BUF2.

  4A and 4B show signal waveform examples of the host (MPU) interface. A host device (external device) such as an MPU, a baseband engine, or an image processor uses a write signal XWR ("X" means negative logic) as shown in FIG. 8-bit signal) is input to the integrated circuit device (display driver). That is, the command A is written using the signal D by setting the signal A0, which is a command / parameter identification signal, to L level and the write signal XWR to L level. Next, the parameter (data) of the command is written using the signal D by setting the signal A0 to the H level and the write signal XWR to the L level. Note that commands and parameters are written to the registers (registers and bus holders included in the circuit block 50) included in the integrated circuit device at the rising edge of the write signal XWR. A read operation from the integrated circuit device is performed using a read signal XRD as shown in FIG.

  The I / O circuit 22 buffers the write signal XWR and outputs it. The input control circuit 24 generates the enable signal ENB based on the signal XWRI from the I / O circuit 22. The enable signal ENB is a signal for controlling the input of the I / O circuit 20, and the input of the I / O circuit 20 is enabled when the signal ENB is at the H level (active).

  The circuit AND1 of the I / O circuit 20 buffers the data signal D from the pad 18 and outputs it as the output signal QI when the signal ENB is at the H level. In this case, the output of the circuit BUF1 is set to a high impedance state.

  The malfunction prevention circuit 30 includes a signal processing circuit 32 and a selector 34. The signal processing circuit 32 receives the enable signal ENB and outputs a signal obtained by subjecting the signal ENB to signal delay processing and filter processing as the second enable signal ENB2. 3B and 3C show an example of the signal ENB2 output from the signal processing circuit 32. FIG. In FIG. 3B, signal delay processing is performed only on the rising edge of the signal ENB to generate the signal ENB2. In FIG. 3C, signal delay processing is performed on both rising and falling edges of the signal ENB to generate the signal ENB2. The signal processing circuit 32 may perform only one of the signal delay processing and the filter processing, or may perform both.

  The selector 34 receives the voltage level of the power supply VDDC at its first input, and receives the output signal QI from the I / O circuit 20 at its second input. Based on the enable signal ENB2, either the first input or the second input is selected and the output signal QP is output. For example, in FIG. 3B, the signal ENB2 is at the L level (first voltage level) in the periods T1 and T2, and the first input of the selector 34 is selected. Therefore, the selector 34 outputs the output signal QP set to the voltage level of the power supply VDDC.

  On the other hand, in the period T3, the signal ENB2 is at the H level (second voltage level), and the second input of the selector 34 is selected. Therefore, the selector 34 outputs the signal QI from the I / O circuit 20 as the signal QP. In this way, it is possible to prevent a malfunction caused by an erroneous signal input to the circuit block 50 due to an external surge or the like.

  FIG. 5A shows a configuration example of the signal processing circuit 32. The signal processing circuit 32 includes inverter circuits INV1 to INVM and a circuit AND3 that constitute a delay circuit. The output of the circuit INVM is input to the first input of the circuit AND3, and the signal ENB is output to the second input. By adopting the configuration of FIG. 5A, a signal ENB2 as shown in FIG. 3B can be generated. In the signal ENB2 in FIG. 3B, the rising edge is delayed by several ns (for example, 2 ns), while the falling edge is hardly delayed. Therefore, when writing to the register of the circuit block 50 at the rising edge of the signal XWR (falling edge of ENB) as shown in FIG. 4A, the adverse effect of the write hold time and setup time on the AC characteristics is adversely affected. Can be minimized. The signal processing circuit 32 may be configured as shown in FIG. In this case, the signal ENB2 shown in FIG. 3C is generated. The signal processing circuit 32 may be a signal delay circuit (signal delay & filter circuit) as shown in FIGS. 5A and 5B, or may be a filter circuit realized by a resistance element or a capacitor. .

  FIG. 5C shows a configuration example of the selector 34. The selector 34 in FIG. 5C includes a transfer transistor TT1 constituted by transistors TR1 and TR2, and a transfer transistor TT2 constituted by transistors TR3 and TR4. When the signal ENB2 is at L level, TT1 is turned on, and when it is at H level, TT2 is turned on. The selector 34 may be configured as shown in FIG. The selector 34 in FIG. 5D includes circuits AND4 and AND5 and a circuit OR1.

4). The command assignment malfunction prevention circuit 30 may be provided only for some bits of the data signal or may be provided for all bits. For example, in FIG. 6A, the integrated circuit device includes I / O circuits 20-7 to 20-0 (first to Jth I / O circuits in a broad sense) and malfunction prevention circuits 30-7 to 30-0. (First to Jth malfunction prevention circuits in a broad sense). The I / O circuits 20-7 to 20-0 buffer and output the data signals D7 to D0 from the pads 18-7 to 18-0 when the enable signal ENB is at the H level. In addition, the malfunction prevention circuits 30-7 to 30-0 receive the output signals QP7 to QP0 (first to Jth output signals in a broad sense) that are set to voltage levels by the power supply VDDC during the periods T1 and T2, respectively. Output to. On the other hand, in the period T3, output signals QP7 to QP0 corresponding to the output signals QI7 to QI0 from the I / O circuits 20-7 to 20-0 are output to the circuit block 50.

  In FIG. 6A, malfunction prevention circuits 30-7 to 30-0 are provided for all bits of the data signals D7 to D0. Therefore, it is possible to prevent a situation in which erroneous signals due to ESD external noise are input to the circuit block 50 for all of the data signals D7 to D0.

  In FIG. 4A, when the signal A0 is at the L level, a command is input by the data signals D7 to D0. That is, as shown in FIG. 6B, for each combination of the signal levels of the signals D7 to D0 (first to Jth input signals from the first to Jth pads), each command ( Operation instruction command) is assigned. For example, when the signals D7 to D0 are (00h), the command CMD0 is input. When the signals D7 to D0 are 01h, the command CMD1 is input. "H" means hex display. When the signal A0 is at the H level, command parameters are input by the signals D7 to D0.

  In FIG. 6B, CMD0 is a software reset command. Therefore, if the malfunction prevention circuit is not provided, there is a possibility that the software reset command is erroneously written when ESD is applied. In this regard, in the present embodiment, since the malfunction prevention circuits 30-7 to 30-0 are provided, the signals QP7 to QP0 are fixed at the H level when ESD is applied, and erroneous writing of the software reset command can be prevented.

  In the periods T1 and T2, it is desirable that the malfunction prevention circuits 30-7 to 30-0 output the output signals QP7 to QP0 to the circuit block 50 with combinations of signal levels that are not assigned to commands. For example, in FIG. 6B, no command is assigned to (FFh). Therefore, it is desirable that the malfunction prevention circuits 30-7 to 30-0 output signals QP7 to QP0 that satisfy (11111111) = (FFh) in the periods T1 and T2. In this way, the frequency with which the software reset command is erroneously written can be further reduced.

  Further, the voltage levels of the data signals D7 to D0 may all be set to the H level during the ESD immunity test or during standby in normal operation. In this case, the malfunction prevention circuits 30-7 to 30-0 may set all the voltage levels of the signals QP7 to QP0 to H level in the periods T1 and T2 and output the signals QP7 to QP0 of (FFh). desirable. Conversely, when the voltage levels of the signals D7 to D0 are all set to the L level during the ESD immunity test, all the voltage levels of the signals QP7 to QP0 are set to the L level in the periods T1 and T2. Is desirable.

5). Malfunction prevention circuit between circuit blocks A malfunction prevention circuit can also be provided between circuit blocks. For example, in FIG. 7A, the integrated circuit device includes a circuit block 60 (Kth circuit block) that outputs a valid output signal QI when the enable signal ENB is at H level (second voltage level); A circuit block 90 (Lth circuit block) to which an output signal from the circuit block 60 is input and a malfunction prevention circuit 70 are included. Note that the malfunction prevention circuit 70 may be included in the circuit blocks 60 and 90.

  As shown in FIG. 7B, the malfunction prevention circuit 70 includes a period T2 including a period T1 in which the signal ENB is at the L level (first voltage level) and a period in which the signal ENB transitions from the L level to the H level. Then, an output signal QP whose voltage level is set by the power supply VDDC is output to the circuit block 90. On the other hand, the output signal QP corresponding to the output signal QI from the circuit block 60 is output to the circuit block 90 in the period T3 in which the signal ENB is at the H level following the period T2.

  In this way, the voltage level of the output signal QP of the malfunction prevention circuit 70 is maintained at the voltage level of the power supply VDDC even when noise is applied to the power supply when ESD or the like is applied. Accordingly, it is possible to prevent a situation where a command is erroneously written due to noise such as an external surge, and to improve the ESD immunity withstand voltage.

  For example, the circuit block 60 in FIG. 7A is a logic circuit block (G / A), and the circuit block 90 is a power supply circuit block that is controlled by the logic circuit block and generates power. Alternatively, the circuit block 90 is a gradation voltage generation circuit block that generates gradation voltages under the control of the logic circuit block. Voltage adjustment data and gradation adjustment data are communicated between the logic circuit block, the power supply circuit block, and the gradation voltage generation circuit block. Therefore, when noise is added to the communication signal due to ESD or the like, erroneous voltage adjustment data and gradation adjustment data are written in the power supply circuit block and the gradation voltage generation circuit block, resulting in malfunction. In particular, if the distance between the logic circuit block, the power supply circuit block, and the grayscale voltage generation circuit block is long, noise is easily applied to the communication signal, and malfunction is likely to occur. In this regard, if a malfunction prevention circuit as shown in FIG. 7A is provided, such malfunction can be prevented and the withstand voltage of ESD immunity can be improved.

  FIG. 8A shows detailed examples of the circuit blocks 60 and 90 and the malfunction prevention circuit 70. The circuit block 60 outputs address signals A3 to A0, data signals D7 to D0, and an enable signal ENB to the circuit block 90. A latch signal LAT is also output. Specifically, when the signal ENB is at L level (first voltage level), the circuit block 60 outputs an address signal (Mth address signal) of (Fh) and invalid data signals D7 to D0. Output. On the other hand, when the signal ENB is at the H level (second voltage level), valid data signals D7 to D0 are output.

  Then, as shown in FIG. 8B, the malfunction prevention circuit 70 outputs address signals PA3 to PA0 whose voltage levels are set by the power supply VDDC to the circuit block 90 in the periods T1 and T2. Specifically, an address signal in which the combination of the signal levels of the signals PA3 to PA0 is (1111) = (Fh) is output. On the other hand, the malfunction prevention circuit 70 outputs the address signals PA3 to PA0 corresponding to the address signals A3 to A0 from the circuit block 60 to the circuit block 90 in the period T3. Specifically, the signals A3 to A0 are buffered and output to the circuit block 90 as signals PA3 to PA0.

  In FIG. 8A, a circuit block 90 includes a register portion 92 having a plurality of registers R0 to RI. In the register unit 92, the adjustment data (voltage adjustment data, gradation adjustment data) set by the data signals D7 to D0 is written into the registers specified by the register addresses of the address signals A3 to A0. For example, in FIG. 8C, registers R0, R1, R2,... Are mapped to register addresses (0h), (1h), (2h),. Then, adjustment data DARO, DAR1, DAR2 set by data signals D7 to D0 for registers R0, R1, R2,... Specified by register addresses (0h), (1h), (2h). ... is written. When the circuit block 90 is a power supply circuit block, the adjustment data DARO, DAR1, and DAR2 are voltage adjustment (voltage setting) data of a plurality of power supplies VDDH, VDDL, and VCOMH generated by the power supply circuit block.

  Thus, when communication is performed between the circuit blocks 60 and 90 using the address signals A3 to A0 and the data signals D7 to D0, incorrect adjustment data is written to the registers R0 to RI due to noise caused by ESD. There is a risk of being. For example, when the signal ENB is at the L level, the signals D7 to D0 are invalid data signals. However, if the voltage level of the signal ENB changes transiently due to noise caused by ESD, the adjustment data set by this invalid data signal may be written to the registers R0 to RI.

  In this regard, in FIG. 8A, a malfunction prevention circuit 70 is provided for the address signals A3 to A0. Therefore, the malfunction prevention circuit 70 prevents the influence of the transient voltage level change from being transmitted to the circuit block 90. Accordingly, it is possible to prevent the adjustment data from being erroneously written due to ESD noise and to improve the ESD immunity withstand voltage.

  As shown in FIG. 8B, the malfunction prevention circuit 70 uses the register address (Fh) not assigned in the normal operation mode as an address signal whose voltage level is set by the power supply VDDC in the periods T1 and T2. Address signals PA7 to PA0 are output to the circuit block 90. For example, in FIG. 8C, no register is mapped to the address signal (Fh). The malfunction prevention circuit 70 outputs address signals PA3 to PA0 that satisfy (1111) = (Fh) in the periods T1 and T2. That is, all the bits of the signals PA3 to PA0 are set to the H level that is the voltage level of the power supply VDDC. In this way, the frequency with which the adjustment data is erroneously written can be further reduced.

  Note that the malfunction prevention circuit 70 in FIG. 8A can include the signal processing circuit 32 and the selector 34 similar to those in FIG. Further, the malfunction prevention circuit 70 may be provided for all the bits of the address signals A3 to A0, or may be provided for only a part of the bits. Alternatively, a malfunction prevention circuit 72 may be provided for the data signals D7 to D0 as shown in FIG. In this case, the malfunction prevention circuit 72 outputs the data signals PD7 to PD0 whose voltage levels are set by the power supply VDDC to the circuit block 90 in the periods T1 and T2, and the data signal D7 from the circuit block 60 in the period T3. Data signals PD7 to PD0 corresponding to .about.D0 are output to the circuit block 90. Alternatively, as shown in FIG. 9B, malfunction prevention circuits 70 and 72 may be provided for both the address signals A3 to A0 and the data signals D7 to D0.

6). FIG. 10 shows a detailed circuit configuration example when the integrated circuit device of this embodiment is a display driver. The display panel 512 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel 512 can be constituted by an active matrix type panel using switching elements such as TFT and TFD. Note that the display panel 512 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel (such as an organic EL panel).

  A memory 520 (RAM) stores image data. The memory cell array 522 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The memory 520 includes a row address decoder 524 (MPU / LCD row address decoder), a column address decoder 526 (MPU column address decoder), and a write / read circuit 528 (MPU write / read circuit).

  The logic circuit 540 generates a display control signal for controlling display timing and data processing timing. The logic circuit 540 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 542 generates various control signals and controls the entire apparatus. The display timing control circuit 544 generates a display timing control signal and controls reading of image data from the memory 520 to the display panel 512 side. The host (MPU) interface circuit 546 implements a host interface that generates an internal pulse for each access from the host and accesses the memory 520. The RGB interface circuit 548 realizes an RGB interface that writes moving image RGB data to the memory 520 using a dot clock.

  A host (MPU) interface as shown in FIGS. 4A and 4B is realized by the host interface circuit 546 of FIG.

  The data driver 550 is a circuit that generates a data signal for driving the data lines of the display panel 512. Specifically, the data driver 550 receives gradation data that is image data from the memory 520 and receives a plurality of (for example, 64 levels) gradation voltages (reference voltages) from the gradation voltage generation circuit 610. Then, a voltage corresponding to the gradation data is selected from the plurality of gradation voltages and is output to each data line of the display panel 512 as a data signal (data voltage).

  The scan driver 570 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output to each scanning line of the display panel 512 as a scanning signal (scanning voltage). To do. The scan driver 570 includes a scan address generation circuit and an address decoder. The scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 590 is a circuit that generates various power supply voltages, and FIG. The booster circuit 592 is a circuit that generates a boosted voltage by boosting an input power supply voltage and an internal power supply voltage by using a boosting capacitor and a boosting transistor, and includes a primary to quaternary booster circuit and the like. be able to. The booster circuit 592 can generate a high voltage used by the scan driver 570 and the gradation voltage generation circuit 610. The regulator circuit 594 adjusts the level of the boosted voltage generated by the booster circuit 592. A VCOM generation circuit 596 generates and outputs a VCOM voltage supplied to the counter electrode of the display panel. The control circuit 598 controls the power supply circuit 590 and includes an adjustment register 599 in which power supply voltage adjustment data is set.

  A grayscale voltage generation circuit (γ correction circuit) 610 is a circuit that generates a grayscale voltage, and FIG. The selection voltage generation circuit 612 (voltage dividing circuit) generates selection voltages VS0 to VS255 (R selection voltages in a broad sense) based on the high-voltage power supply voltages VDDH and VSSH generated by the power supply circuit 590. Output. Specifically, the selection voltage generation circuit 612 includes a ladder resistor circuit having a plurality of resistor elements connected in series. Then, voltages obtained by dividing VDDH and VSSH by the ladder resistor circuit are output as selection voltages VS0 to VS255. Based on the gradation characteristic adjustment data set in the adjustment register 616 by the logic circuit 540, the gradation voltage selection circuit 614 has 64 (for example, 64 selection voltages VS0 to VS255 in the case of 64 gradations). In a broad sense, S voltages (R> S) are selected and output as gradation voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel.

7). Elongated Integrated Circuit Device FIG. 12 shows an arrangement example of the integrated circuit device 10. The integrated circuit device 10 includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F region 12 (first I / O region) is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. The input-side I / F area 14 (second I / O area) is arranged on the D4 direction side of the circuit blocks CB1 to CBN, for example, without passing through other circuit blocks. That is, at least in the portion where the data driver block exists, there is only one circuit block (data driver block) in the direction D2. When the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, etc., it may be configured such that at least one of the I / F regions 12 and 14 is not provided.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and includes various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, it includes an output transistor for outputting a data signal to the data line and a scanning signal to the scanning line. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like are included.

  Note that an output-side or input-side I / F area along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to. More specifically, the circuit blocks CB1 to CBN can include at least a data driver block and a logic circuit block, and can further include a grayscale voltage generation circuit block. In the case of a built-in memory type, a memory block can be further included.

  FIG. 13 shows a detailed example of the planar layout of the integrated circuit device 10. In FIG. 13, first to Nth circuit blocks CB1 to CBN include first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense; I is an integer of 2 or more). . The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  The layout arrangement of the integrated circuit device 10 of the present embodiment is not limited to FIG. For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. In addition, a configuration in which a memory block, a scan driver block, a power supply circuit block, a gradation voltage generation circuit block, or the like is not provided may be employed. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  FIG. 14A shows an example of a cross-sectional view of the integrated circuit device 10 along the direction D2. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. The widths W1, WB, and W2 are the widths (maximum widths) of the transistor formation regions (bulk region and active region) in the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14, respectively. Yes, it does not include the bump formation area. W is the width of the integrated circuit device 10 in the direction D2.

  In the present embodiment, as shown in FIG. 14A, in the direction D2, no other circuit block is interposed between the circuit blocks CB1 to CBN and the output side and input side I / F regions 12 and 14. . Therefore, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2. Alternatively, since W1 + W2 <WB holds, W <2 × WB can be set.

  On the other hand, in the arrangement method of FIG. 14B, two or more circuit blocks are arranged along the direction D2. Specifically, the data driver block and the memory block are arranged along the direction D2.

  For example, in FIG. 14B, image data from the host side is written into the memory block. The data driver block converts the digital image data written in the memory block into an analog data voltage, and drives the data lines of the display panel. Accordingly, the signal flow of the image data is in the direction D2. For this reason, in FIG. 14B, the memory block and the data driver block are arranged along the direction D2 in accordance with the flow of this signal.

  However, the arrangement method of FIG. 14B has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, if a fine process is employed and the integrated circuit device is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced, and mounting becomes difficult due to the narrow pitch.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the arrangement method of FIG. 14B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match in a certain product, these pitches do not match if the configuration of the memory or data driver changes. . If the pitches do not match, it becomes necessary to form a useless wiring region for absorbing the pitch mismatch between the circuit blocks. As a result, the width of the integrated circuit device in the direction D2 is increased, the chip area is increased, and the cost is increased. On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost.

  On the other hand, in the arrangement methods shown in FIGS. 12 and 13, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. In FIG. 14A, a transistor (circuit element) can be arranged under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, the width W in the D2 direction can be narrowed while maintaining the length of the integrated circuit device 10 in the D1 direction, and a slim elongated chip can be realized.

  In addition, the circuit blocks CB1 to CBN are arranged along the direction D1 in the arrangement methods shown in FIGS. 12 and 13, so that it is possible to easily cope with a product specification change or the like. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, in FIG. 13, even when the number of pixels and the number of gradations of the display panel increase or decrease, it is possible to cope with only by increasing or decreasing the number of memory blocks or data driver blocks or the number of times image data is read out in one horizontal scanning period. it can. FIG. 13 shows an example for an amorphous TFT panel with a built-in memory. However, when developing a product for a low-temperature polysilicon TFT panel with a built-in memory, the scan driver block is simply removed from the circuit blocks CB1 to CBN. That's it. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, the influence of the circuit block on other circuit blocks can be minimized, so that the design efficiency can be improved.

  12 and 13, the width (height) of each circuit block CB1 to CBN in the direction D2 can be unified to the width (height) of the data driver block and the memory block, for example. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, in FIG. 13, even when the configuration of the gradation voltage generation circuit block or the power supply circuit block is changed and the number of transistors is increased or decreased, the length of the gradation voltage generation circuit block or the power supply circuit block in the D1 direction is increased or decreased. It can respond by doing.

8). Arrangement of Logic Circuit Blocks and Power Supply Circuit Blocks In this embodiment, as shown in FIG. 15, the circuit blocks CB1 to CBN are logic circuit blocks LB for setting power supply voltage adjustment data (Kth circuit block in a broad sense). And a power supply circuit block PB (Lth circuit block in a broad sense, 1 ≦ K <L ≦ N) that generates a power supply voltage based on the set adjustment data. Further, it includes data driver blocks DB1 to DB4 (at least one data driver block in a broad sense) for driving the data lines. In FIG. 15, another circuit block is arranged between the logic circuit block LB and the power supply circuit block PB. Specifically, data driver blocks DB1 to DB4, which are other circuit blocks, are arranged between LB and PB.

  According to the arrangement of FIG. 15, the logic circuit block LB and the power supply circuit block PB having a relatively large circuit area are arranged on both sides of the data driver blocks DB1 to DB4. Therefore, the logic circuit pad, the input transistor formed under the pad, and the like can be arranged using the empty space (space shown by C1) on the D4 direction side of the logic circuit block LB. Further, by using the empty space (space indicated by C2) on the D4 direction side of the power supply circuit block PB, it becomes possible to arrange boosting transistors and the like of the power supply circuit having a large transistor size.

  Further, according to the arrangement shown in FIG. 15, the data driver blocks DB1 to DB4 can be concentrated and arranged near the center of the integrated circuit device. Therefore, the output lines of the data signals from DB1 to DB4 are connected to the output side I / F. In the area 12, wiring can be performed efficiently and simply. Therefore, the wiring efficiency and the placement efficiency in the output I / F region 12 and the input I / F region 14 can be improved, the width W in the D2 direction of the integrated circuit device can be reduced, and a slim elongated integrated circuit device can be obtained. realizable.

  By the way, when the logic circuit block LB and the power supply circuit block PB are arranged as shown in FIG. 15, the distance between LB and PB is increased. In particular, when the arrangement methods shown in FIGS. 12 and 13 are employed, the length LD in the long side direction (D1 direction) of the integrated circuit device is 15 mm <LD <27 mm, which makes the chip very slim and elongated. Therefore, the distance between the logic circuit block LB and the power supply circuit block PB is very large.

  When the distance between the logic circuit block LB and the power supply circuit block PB is increased as described above, the length of the signal line of the power supply voltage adjustment data connecting these blocks also increases. Therefore, there is a high possibility that erroneous adjustment data due to noise such as ESD is written to the register of the power supply circuit block PB.

  In this regard, in the present embodiment, a malfunction prevention circuit 70 is provided between the logic circuit block LB that is the circuit block 60 and the power supply circuit block PB that is the circuit block 90 as shown in FIG. Therefore, even when the logic circuit block LB and the power supply circuit block PB are arranged at a distance as shown in FIG. 15, erroneous writing of adjustment data due to noise such as ESD can be prevented. Then, by arranging the logic circuit block LB and the power supply circuit block PB at a distance as shown in FIG. 15, the wiring efficiency and the placement efficiency in the output side I / F region 12 and the input side I / F region 14 can be improved. The width W in the direction D2 of the integrated circuit device can be reduced. Therefore, it is possible to achieve both a slim and long integrated circuit device and an ESD immunity withstand voltage improvement.

9. Electronic Device FIGS. 16A and 16B show examples of an electronic device (electro-optical device) including the integrated circuit device 10 of the present embodiment. Note that the electronic apparatus may include components (for example, a camera, an operation unit, a power supply, or the like) other than those illustrated in FIGS. The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  In FIGS. 16A and 16B, the host device 410 is, for example, an MPU, a baseband engine, or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, the image processing controller 420 in FIG. 16B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 16A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 16B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (data signal, L level, H level, etc.) described at least once together with different terms (input signal, first voltage level, second voltage level, etc.) having a broader meaning or the same meaning ) May be replaced by the different terms anywhere in the specification or drawings. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

1A to 1D are explanatory diagrams of ESD immunity. 2A, 2B, and 2C are a configuration example and an explanatory diagram of the integrated circuit device of the present embodiment. 3A, 3B, and 3C are detailed configuration examples and explanatory diagrams of an integrated circuit device. 4A and 4B show signal waveform examples of the host (MPU) interface. 5A to 5D are configuration examples of a signal processing circuit and a selector. 6A and 6B are a configuration example of an integrated circuit device and explanatory diagrams of commands. 7A and 7B are explanatory diagrams of a method of providing a malfunction prevention circuit between circuit blocks. 8A, 8B, and 8C are also explanatory diagrams of a method of providing a malfunction prevention circuit between circuit blocks. 9A and 9B are explanatory diagrams of a method of providing a malfunction prevention circuit for a data signal. 6 is a circuit configuration example of a display driver which is an integrated circuit device. 11A and 11B are configuration examples of a power supply circuit and a gradation voltage generation circuit. An example of arrangement of an integrated circuit device. 3 shows a detailed arrangement example of an integrated circuit device. 14A and 14B are examples of cross-sectional views of an integrated circuit device. Explanatory drawing of the arrangement method of a logic circuit block and a power supply circuit block. 16A and 16B are configuration examples of electronic devices.

Explanation of symbols

4 electrostatic application device, 6 display module, 8 display panel, 10 integrated circuit device,
18, 18-7 to 18-0 pad, 20, 20-7 to 20-0, 22 I / O circuit,
24 input control circuit 30, 30-7 to 30-0 malfunction prevention circuit, 50 circuit block,
60 circuit block (Kth circuit block), 70, 72 malfunction prevention circuit,
90 circuit block (Lth circuit block), 92 register unit

Claims (9)

A Kth circuit block for outputting an output signal when the enable signal is at the second voltage level;
An Lth circuit block to which an output signal from the Kth circuit block is input;
In a first period in which the enable signal is at a first voltage level and a second period in which the enable signal transitions from the first voltage level to the second voltage level, a first power supply To output an output signal whose voltage level is set to the L-th circuit block, and in a third period after the second period in which the enable signal is at the second voltage level, A malfunction prevention circuit for outputting an output signal corresponding to an output signal from the Kth circuit block to the Lth circuit block;
An integrated circuit device comprising: In claim 1,
The Kth circuit block is a logic circuit block;
The integrated circuit device, wherein the Lth circuit block is a power supply circuit block that is controlled by the logic circuit block to generate a power supply voltage. In claim 1,
The Kth circuit block is a logic circuit block;
The integrated circuit device, wherein the Lth circuit block is a gradation voltage generation circuit block that is controlled by the logic circuit block to generate a gradation voltage. In any one of Claims 1 thru | or 3,
The malfunction prevention circuit is
A signal processing circuit that receives the enable signal and outputs a signal obtained by performing at least one of a signal delay process and a filter process on the enable signal as a second enable signal;
The voltage level of the first power supply is input to the first input, the output signal from the Kth circuit block is input to the second input, and the first input is based on the second enable signal. And an selector that selects any one of the second inputs and outputs an output signal. In any one of Claims 1 thru | or 4,
The Kth circuit block is:
An address signal, a data signal, and the enable signal are output to the Lth circuit block;
The malfunction prevention circuit is
In the first and second periods, an address signal whose voltage level is set by the first power supply is output to the Lth circuit block, and in the third period, the address signal from the Kth circuit block is output. An integrated circuit device that outputs an address signal corresponding to an address signal to the L-th circuit block. In claim 5,
The malfunction prevention circuit is
In the first and second periods, an address signal not assigned in the normal operation mode is output to the Lth circuit block as an address signal whose voltage level is set by the first power supply. Integrated circuit device. In any one of Claims 1 thru | or 6.
The Kth circuit block is:
An address signal, a data signal, and the enable signal are output to the Lth circuit block;
The malfunction prevention circuit is
In the first and second periods, a data signal whose voltage level is set by the first power supply is output to the Lth circuit block, and in the third period, the data signal from the Kth circuit block is output. An integrated circuit device, wherein a data signal corresponding to a data signal is output to the Lth circuit block. In any one of Claims 1 thru | or 7,
The direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is defined as the first direction, and the second side, which is the long side of the integrated circuit device, is directed to the fourth side facing the first side. Including the first to Nth circuit blocks arranged along the first direction when the direction toward the second direction is the second direction,
The first to Nth circuit blocks are:
Including the Kth circuit block and the Lth circuit block (1 ≦ K <L ≦ N);
An integrated circuit device, wherein another circuit block is arranged between the Kth circuit block and the Lth circuit block. An integrated circuit device according to any one of claims 1 to 8,
A display panel driven by the integrated circuit device;
An electronic device comprising:

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