JP4356836B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit capable of initializing an output voltage to a desired level when power is turned on.

  FIG. 4 shows a conventional level shift circuit (see, for example, Patent Document 1). In FIG. 4, PMOS transistors P1 and P2 and NMOS transistors N1 and N2 constitute a latch circuit 1 and operate at a high power supply voltage VDDH. The voltage of the input terminal IN is applied to the gate (first input terminal: IN1) of the transistor N1 of the latch circuit 1, and the input to the gate (second input terminal: IN2) of the transistor N2 via the inverter INV1. The voltage at the terminal IN is applied with the level inverted. The inverter INV1 operates with a low power supply voltage VDDL (<VDDH). The input voltage of the input terminal IN of this level shift circuit is 0 to VDDL, and the output voltage of the output terminal OUT is 0 to VDDH.

  Here, when the input terminal IN = 0V, the transistor N1 is cut off and the transistor N2 is turned on. When the transistor N2 is turned on, the voltage at the output terminal OUT is lowered, the transistor P1 is turned on, the level of the node A1 having the opposite logic to that of the output terminal OUT is increased to the high power supply voltage VDDH, and the transistor P2 is cut off. Eventually, the transistor N2 becomes conductive and the transistor P2 is cut off, and the voltage of the output terminal OUT becomes 0V.

  On the other hand, when the input terminal IN = VDDL, the transistor N1 is turned on and N2 is turned off. When the transistor N1 is turned on, the voltage at the node A1 is lowered, the transistor P2 is turned on, the level of the output terminal OUT rises to the high power supply voltage VDDH, and the transistor P1 is cut off. Eventually, the transistor P2 becomes conductive and the transistor N2 is cut off, and the voltage of the output terminal OUT becomes the high power supply voltage VDDH.

As described above, in the conventional level shift circuit, the voltage of 0V to VDDL inputted to the input terminal IN is level-converted to the voltage of 0V to VDDH and outputted to the output terminal OUT without passing through current.
JP 11-027137 A

  However, in this conventional level shift circuit, when the high power supply voltage VDDH is turned on earlier than the low power supply voltage VDDL, both the input terminals IN1 and IN2 of the latch circuit 1 become 0V. There is a problem that both the transistors N1 and N2 are cut off and the voltage at the output terminal OUT becomes unstable.

  An object of the present invention is to provide a level shift circuit in which the logic of the output terminal OUT is determined even when both input terminals IN1 and IN2 of the latch circuit 1 become 0V when VDDL = 0V. That is.

A level shift circuit according to a first aspect of the present invention includes a latch circuit having a first input terminal, a second input terminal, and an output terminal and operating at a high power supply voltage, and an input side connected to the first input terminal. A first inverter connected to an output side of the second input terminal and operating at a low power supply voltage, and a signal input to the first input terminal is changed from a level of the low power supply voltage to a level of the high power supply voltage. In the level shift circuit that shifts to the output signal and outputs from the output terminal, the input side is connected to the first input terminal, and the second inverter that operates at the high power supply voltage is connected between the output terminal and the ground. electrodeposition of the output signal of the second inverter is provided and switch means for cutting off when conducting at a high level of low level, the second inverter, and the inverter, the high supply voltage The characterized by having a voltage shifting means for applying to at least the said inverter main body is lowered to a voltage of the low supply voltage.

A level shift circuit according to a second aspect of the present invention has a first input terminal, a second input terminal, an output terminal, and a node that generates a logic voltage opposite to the logic of the output terminal, and operates at a high power supply voltage. A latch circuit; and a first inverter connected to the first input terminal and connected to the second input terminal and connected to the output side and operating at a low power supply voltage, and inputs to the first input terminal. In a level shift circuit that shifts a signal from the low power supply voltage level to the high power supply voltage level and outputs the signal from the output terminal, an input side is connected to the second input terminal and operates at the high power supply voltage. a second inverter, the node and is connected between the ground output signal of the second inverter is provided and switch means for cutting off when conducting at a high level of low level, the second i Converter is characterized by having an inverter main body, and a voltage shift means for applying to said inverter main body lowers the voltage of said high power supply voltage to a voltage of at least the low power supply voltage.

  According to the level shift circuit of the present invention, even when the low power supply voltage VDDL is turned on later than the high power supply voltage VDDH, the voltage level of the output terminal can be initialized to 0V or VDDH. The logic is not output to the subsequent logic circuit.

  FIG. 1 is a circuit diagram showing a principle configuration of a level shift circuit of the present invention. In FIG. 1, PMOS transistors P1, P2 and NMOS transistors N1, N2 constitute a latch circuit 1 and operate at a high power supply voltage VDDH. The voltage of the input terminal IN is applied to the gate (first input terminal: IN1) of the transistor N1 of the latch circuit 1, and the gate (second input terminal: IN2) of the transistor N2 is input via the inverter INV1. The voltage at the terminal IN is applied with the level inverted. The inverter INV1 operates with a low power supply voltage VDDL (<VDDH). Furthermore, an NMOS transistor N3 (switch means) is connected between the output terminal OUT and GND, and the voltage of the input terminal IN is applied to the gate of the NMOS transistor N3 through the inverter INV2 with the level inverted. The inverter INV2 operates with the high power supply voltage VDDH, but is an inverter having a structure in which no through current flows even when the input voltage level is the low power supply voltage VDDL.

  As described above, when the high power supply voltage VDDH is turned on earlier than the low power supply voltage VDDL and VDDL = 0V, the input terminal IN is 0V and the high power supply voltage VDDH of the inverter INV2 rises earlier. Therefore, the node A3 becomes high level, the transistor N3 becomes conductive, and the voltage of the output terminal OUT is determined to be 0V.

  The normal level shift operation is exactly the same as that described with reference to FIG. During this normal operation, the transistor N3 is turned on / off by the output of the inverter INV2, but is turned on when the output terminal OUT controlled by the latch circuit 1 including the transistors P1, P2, N1, and N2 is 0V. Since the power supply voltage VDDH is cut off, the level shift operation is not affected.

  FIG. 2 shows a level shift circuit of a modification of FIG. In the level shift circuit of FIG. 2, the NMOS transistor N4 (switch means) is connected between the nodes A1 and GND, the inverter INV3 is connected to the node A2 on the input side, and the node A4 on the output side is connected to the node N4. It differs from the level shift circuit of FIG. 1 in that it is connected to the gate.

  In the level shift circuit of FIG. 2, the power supply voltage VDDH is turned on earlier than the low power supply voltage VDDL. When VDDL = 0V, the voltage at the node A2 is 0V, so the transistor N2 is cut off. Further, the high power supply voltage VDDH of the inverter INV3 rises early, the transistor N4 becomes conductive, the node A1 becomes 0V, the transistor P2 becomes conductive, and the voltage of the output terminal OUT is determined to be the high power supply voltage VDDH.

  In normal operation, the transistor N4 is cut off when the output terminal OUT controlled by the latch circuit 1 including the transistors N1, N2, P1, and P2 is 0V, and is turned on when VDDH, so that the level shift operation is affected. Will not affect.

  FIG. 3 is a circuit diagram showing a specific example of the level shift circuit according to the first embodiment of the present invention, in which the inverter INV2 of the level shift circuit shown in FIG. 1 is embodied. Here, the inverter INV2 is composed of a CMOS inverter body composed of a PMOS transistor P3 and an NMOS transistor N5, and three NMOS transistors N6, N7, and N8 that are diode-connected between the inverter body and a terminal of the high power supply voltage VDDH. Voltage shift means. In the inverter INV2, the potential of the source point (node A5) of the transistor P3 is shifted from the high power supply voltage VDDH to the low power supply voltage VDDL or lower by three diodes. If the voltage shift amount is insufficient with three diodes, the number of diode-connected transistors may be increased.

  In this way, by setting the voltage at the node A5 to be equal to or lower than the low power supply voltage VDDL, which is the high level of the input voltage, the transistor P3 is turned on when the input voltage becomes the low power supply voltage VDDL. There is no conduction, and no through current flows.

  In such a structure, since the output impedance becomes large, the operation speed of the inverter INV2 may decrease and the output voltage may not reach the level of the low power supply voltage VDDL. However, the inverter INV2 only determines the initial value. There is no problem.

  Note that the inverter INV3 of the level shift circuit shown in FIG. 2 operates in the same manner if it has the same structure as the inverter INV2 shown in FIG.

It is a circuit diagram of a level shift circuit for explaining the principle of the present invention. It is a circuit diagram of the level shift circuit of a modification. FIG. 2 is a circuit diagram of a specific example of the level shift circuit of FIG. 1. It is a circuit diagram of a conventional level shift circuit.

Explanation of symbols

1: latch circuit P1-P3: PMOS transistor, N1-N8: NMOS transistor, INV1-INV3: inverter, IN: input terminal, IN1: first input terminal, IN2: second input terminal, OUT: output terminal

Claims (2)

A latch circuit having a first input terminal, a second input terminal and an output terminal and operating at a high power supply voltage; and an input side connected to the first input terminal and an output side connected to the second input terminal; A first inverter that operates with a power supply voltage, and a signal input to the first input terminal is shifted from the low power supply voltage level to the high power supply voltage level signal and output from the output terminal. In the level shift circuit,
A second inverter connected to the first input terminal and operating at the high power supply voltage, and connected between the output terminal and the ground and conductive when the output signal of the second inverter is at a high level. provided a switch means for cutting off time,
The second inverter includes an inverter body and voltage shift means for reducing the voltage of the high power supply voltage to at least the voltage of the low power supply voltage and applying the voltage to the inverter body . A latch circuit having a first input terminal, a second input terminal, an output terminal, and a node for generating a logic voltage opposite to the logic of the output terminal and operating at a high power supply voltage, and an input to the first input terminal And a first inverter connected to the second input terminal and operating at a low power supply voltage, and a signal input to the first input terminal is transferred from the level of the low power supply voltage to the high power supply. In a level shift circuit that shifts to a voltage level signal and outputs from the output terminal,
A second inverter connected to the second input terminal on the input side and operating at the high power supply voltage; connected between the node and ground; and conductive when the output signal of the second inverter is at a high level; A switch means for blocking ,
The second inverter includes an inverter body and voltage shift means for reducing the voltage of the high power supply voltage to at least the voltage of the low power supply voltage and applying the voltage to the inverter body .

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