JP3538558B2 - Analog switch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an analog switch circuit.

[0002]

2. Description of the Related Art A conventional analog switch circuit has a configuration as shown in FIG. P-channel type MOS
The transistor P41 and the N-channel MOS transistor N41 have their sources and drains commonly connected in parallel. An enable signal EN generated by a control circuit (not shown) is inverted by the inverter IN31 and input to the gate of the transistor N41, and further inverted by the inverter IN32 and input to the gate of the transistor P41 to control respective operations. You. When an enable signal EN at the same high level as the power supply voltage VDD is input, both the transistors N41 and P41 are turned on, the source and the drain are electrically connected, and the input terminal and the output terminal are electrically connected.

Here, two transistors N41 and P41 having different conductivity types are used because of the N-channel type M transistor.
When a switch is configured using only OS transistors,
This is because when the input voltage is high, the on-resistance of the switch increases due to the substrate bias effect.

FIG. 8 shows a sectional structure of an element on a semiconductor substrate of the switch circuit. A P-type well 102 and an N-type well 103 are formed on the surface of a P-type semiconductor substrate 101. As an N-channel MOS transistor N41, N-type impurity diffusion layers 104 and 105 corresponding to source and drain regions are formed on the surface of a P-type well 102. Similarly, as a P-channel MOS transistor P41, an N-type well is formed. Source on the surface of 103,
P-type impurity diffusion layers 106 and 1 corresponding to drain regions
07 is formed.

A P ⁺ -type impurity diffusion layer 108 is formed in the P-type well 102 and is grounded.
N ⁺ -type impurity diffusion layer 109 is formed on
DD is applied. N-type impurity diffusion layer 104 and P-type impurity diffusion layer 107 are connected to an input terminal, and N-type impurity diffusion layer 105 and P-type impurity diffusion layer 106 are connected to an output terminal. As described above, the enable signal E is applied to the gate G1 of the N-channel MOS transistor.
N is input, and the enable signal / EN is input to the gate G2 of the P-channel MOS transistor.

[0006]

However, the conventional switch circuit has the following problems. When a signal having a voltage higher than the power supply voltage VDD is input to the input terminal, P
The channel type MOS transistor is forced to conduct. For example, a power supply voltage VDD of 3 V is supplied, a 3 V enable signal / EN is input to its gate to turn off the P-channel MOS transistor, and a voltage of 3 V is applied to the P-type impurity diffusion layer 106. Suppose you have In this state, when an input signal voltage of, for example, 5 V is applied to the P-type impurity diffusion layer 107 of the input terminal, conduction is forced between the diffusion layers 106 and 107.

Further, as described above, the N-type well 103
To the P-type semiconductor substrate 1
01 is grounded. In this state, the P-type impurity diffusion layer 1
When a voltage of 5 V is applied to 07, a diode D1 biased in the forward direction from diffusion layer 107 toward N ⁺ diffusion layer 109 is formed, and a current flows. As a result, a current flows from the input terminal to the power supply voltage VDD terminal.

In order to avoid such a problem, it is conceivable that a resistor is inserted before the analog switch including the transistors P41 and N41 and the input signal voltage is forcibly reduced and input to the switch. However, since the resistance value of the integrated circuit is fixed, the range in which the voltage can be reduced is limited. Therefore, there is no effect when a high voltage exceeding this range is input.
Further, if a resistor is inserted on the input side of the switch, there is a problem that the waveform of the input signal changes due to the resistance and the parasitic capacitance, which adversely affects the characteristics.

As described above, when a voltage higher than the power supply voltage is input to the conventional analog switch circuit, a transistor to be turned off is turned on and malfunctions, or a current flows from the diffusion layer to the power supply voltage terminal, causing waste. However, there is a problem that current is consumed.

In view of the above circumstances, the present invention provides an analog switch circuit which does not hinder the switching operation even when a voltage higher than the power supply voltage is input, and which can prevent wasteful current consumption. The purpose is to:

[0011]

An analog switch circuit according to the present invention is provided with an input signal and a first power supply voltage, and when the voltage of the input signal is lower than the first power supply voltage, the first power supply voltage. Gate voltage control for generating and outputting a second power supply voltage having the same voltage as the input signal voltage and having the same voltage as the input signal voltage when the voltage of the input signal exceeds the first power supply voltage A level shifter that is supplied with the second power supply voltage, shifts the level of the applied first enable signal in accordance with the second power supply voltage, and outputs the level shifter as a second enable signal; And an analog switch for controlling a switching operation by receiving an enable signal and outputting the input signal when the switch is closed.

Here, the analog switch is connected to the second switch.
And a P-channel MOS transistor whose operation is controlled based on an enable signal of
It is desirable that the second power supply voltage be applied to the N-type well in which the S transistor is formed.

The gate voltage control circuit may include a first P-channel MOS transistor having a drain supplied with the first power supply voltage and a gate supplied with the input signal, and a drain supplied with the input signal. And the second P-channel type MO whose gate receives the first power supply voltage.
And an S transistor, wherein the second power supply voltage is output from the sources of the first and second P-channel MOS transistors.

Further, the first and second P-channel type M
It is preferable that the OS transistor be a transistor having a low threshold voltage.

Further, the level shifter has third and fourth P-channel MOS transistors each having a source to which the second power supply voltage is input, a gate and a drain cross-coupled, and the first enable. A first inverter that receives and inverts and outputs a first inversion enable signal; a second inverter that receives and inverts the first inversion enable and outputs the first enable signal; A first N-channel MOS transistor having a drain connected to the drain of the third P-channel MOS transistor, a gate receiving the inverted first enable signal, a source grounded, and a drain connected to the fourth P-channel MOS transistor; The first enable signal is input to the gate of the P-channel MOS transistor of A second N-channel MOS transistor whose ground is grounded, and which operates by being supplied with the second power supply voltage; an input side is connected to a drain of the fourth P-channel type MOS transistor; And a third inverter that outputs a second enable signal.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the analog switch circuit according to the first embodiment of the present invention comprises an analog switch 11, a level shifter 12, and a gate voltage control circuit 1.
3 is provided. The gate voltage control circuit 13 operates by being supplied with the power supply voltage VDD, receives the input signal, generates the power supply voltage VWELL, and outputs it to the level shifter 12 and the analog switch 11. As shown in FIG. 3, the power supply voltage VWELL has the same voltage as the power supply voltage VDD when the voltage of the input signal is equal to or lower than the power supply voltage VDD, and has the same voltage as the input voltage when the input voltage exceeds the power supply voltage VDD. With voltage.

The level shifter 12 operates by being supplied with the power supply voltage VWELL, and receives an enable signal EN. Then, the high level of the enable signal EN is changed to the power supply voltage VWELL.
And outputs it to the analog switch 11 as the enable signal EN1. Analog switch 11
Is applied to an N-type well in which a P-channel MOS transistor is formed, and is supplied with a level-shifted enable signal EN1 to control a switching operation to output an input signal.

FIG. 2 shows an example of a specific circuit configuration of the gate voltage control circuit 13. The source of the P-channel MOS transistor P11 is connected to the power supply voltage VDD terminal, the gate is connected to the input terminal, and the source is connected to the output terminal. Further, a P-channel MOS transistor P
Twelve sources are connected to the input terminal, the gate is connected to the power supply voltage VDD terminal, and the source is connected to the output terminal.

When a signal having a voltage lower than the power supply voltage VDD is input to the input terminal, the transistor P11 whose gate is input with this signal voltage turns on, and the power supply voltage V
The transistor P12 whose DD is input to the gate is turned off. Thus, when a voltage exceeding the power supply voltage VDD is input to the input terminal from which the power supply voltage VDD is output from the output terminal via the source of the transistor P11, the transistor P11 whose gate is supplied with this signal voltage is turned off. Then, the transistor P12 whose power supply voltage VDD lower than the signal voltage is input to the gate is turned off. Therefore, the same voltage as the input signal is output as the power supply voltage VWELL from the output terminal via the source of the transistor P12.

In FIG. 9, when the input signal voltage approaches the internal power supply voltage 3 [V] of the gate voltage control circuit,
The diode characteristic appears in the range of the threshold voltage of the P-channel MOS transistor constituting the gate voltage control circuit centering on the internal power supply voltage, and the output voltage decreases. Therefore, as shown in FIG. 10, by forming the gate voltage control circuit with a P-channel MOS transistor having a low threshold voltage, the range in which the diode characteristics appear in the output voltage characteristics is narrowed, and the ideal characteristics of the gate voltage control circuit are reduced. You can get closer.

FIG. 6A shows a relationship between an analog input signal swinging in the range of 0 to VWELL and a power supply voltage VDD lower than VWELL. When such an input signal is applied to the gate voltage control circuit 13, a power supply voltage VWELL that varies in the range from the voltage VDD to the voltage VWELL as shown in FIG. 6B is generated.

The power supply voltage VWELL having such characteristics
And an analog switch 11 using a level-converted enable signal EN1 having the same potential when it is at a high level.
, The gate voltage of the P-channel MOS transistor constituting the analog switch 11 is always controlled to be equal to or higher than the input signal voltage. Thus, the above-described conventional problem that the P-channel MOS transistor is forcibly turned on when it should be turned off is avoided, and malfunction of the analog switch 11 is prevented.

Further, an N-type well 103 in which a P-channel MOS transistor of the analog switch 11 is formed.
Is applied with the power supply voltage VWELL. As a result, by using the highest voltage VWELL in the circuit, P
P-type impurity region 107 of channel type MOS transistor
And the N-type well 103 can be reverse biased. Therefore, it is possible to prevent a useless current from flowing from the P-type impurity region 107 to the N-type well 103, the N ⁺ -type impurity region 109, and the power supply voltage VDD terminal by forming the diode D1.

FIG. 4 shows an example of a specific circuit configuration of the level shifter 12. P-channel type MOS transistor P
The sources of 21 and P22 are both connected to the power supply voltage VWELL terminal, and the gate and drain are connected in a cross-coupled manner. The drain of the N-channel MOS transistor N21 is connected to the node ND1 to which the drain of the transistor P21 is connected, the drain of the N-channel MOS transistor N22 is connected to the node ND22 to which the drain of the transistor P22 is connected, and the transistor N2
The sources of 1 and N22 are both grounded. further,
The enable signal / EN inverted by the inverter IN11 is input to the gate of the transistor N21, and the inverters IN11 and I11 are input to the gate of the transistor N22.
The enable signal EN inverted twice by N12 is input.

The input terminal of the inverter IN13 is connected to a node ND2 to which the drain of the transistor P22 and the drain of the transistor N22 are connected.
The output terminal of N13 is connected to the output terminal of level shifter 12. This inverter IN13 has a power supply voltage VWE
It operates with LL supplied. Inverters IN11 and IN
12 operate by being supplied with the power supply voltage VDD.

With respect to the operation of the level shifter 12, the power supply voltage VWELL is 5V and the enable signal EN is 0 or 3V.
An example will be described. When a 3V enable signal EN is input to the input terminal, 0V inverted by the inverter IN11 is applied to the gate of the transistor N21 to turn off, and 3V inverted by the inverters IN11 and IN12 is applied to the gate of the transistor N22. Turn on.

When the transistor N21 is turned off and the transistor N22 is turned on, the potential of the node ND1 rises relatively and the potential of the node ND2 falls. This allows
The transistor P21 turns on and the transistor P22 turns off. In this state, the potential of the node ND2 becomes 0 V, and the potential of the inverter IN13 to which this potential is input is supplied from the inverter IN13 to the enable signal E having a voltage equal to the power supply voltage VWELL.
N1 is output.

When a 0 V enable signal EN is input to the input terminal, the 3 V inverted by the inverter IN11 is output.
Is applied to the gate of the transistor N21 to turn on, and 0 V inverted by the inverters IN11 and IN12 is applied to the gate of the transistor N22 to turn off.

Since the transistor N21 is turned on and the transistor N22 is turned off, the potential of the node ND1 falls and the potential of the node ND2 rises. Then, the transistor P21 turns off and the transistor P22 turns on. As a result, the potential of the node ND2 becomes approximately 5 V, and the inverter IN13 receiving this potential outputs the enable signal EN1 of 0 V.

As described above, when the enable signal EN having 0 or the power supply voltage VDD is input to the level shifter 12, the power supply voltage VDD at the high level is changed to the power supply voltage VWELL.
Is output as the enable signal EN1.

The gate voltage control circuit 13 shown in FIG. 2, the level shifter 12 shown in FIG.
Channel MOS transistor and N channel MOS
Analog switch 11 with one transistor at a time
FIG. 5 shows the inverters IN21 and IN22. Here, the enable signal EN1 output from the level shifter 12 can be directly input to the gates of the transistors P31 and N33 of the analog switch 11. However, the inverters IN21 and IN22 can be used as buffers as shown, and the analog switch 1 can be connected via the inverters IN21 and IN22.
1 is controlled by giving an enable signal EN. In this case, the level shifter 12 outputs the enable signal EN1 having 0 to the power supply voltage VWELL, but the signal EN having the same voltage range is output from the inverter IN21 or IN2.
2 must be output. Therefore, the inverter IN
The power supply voltage VWELL is supplied to 21 and IN22.

As described above, the input signal is supplied to the gate voltage control circuit 13 to which the power supply voltage VDD is supplied.
Are generated, and the level shifter 12, the inverters IN21 and IN2
2. The power is supplied to the N-type well in which the transistor P33 of the analog switch 11 is formed. 0 for level shifter 12
To an enable signal EN1 having a voltage of 0 to power supply voltage VWELL, and output as an enable signal EN1 having a voltage of 0 to power supply voltage VWELL.
Alternatively, the signal is inverted by IN22 and applied to the gates of the transistors P31 and N31 of the analog switch 11 to control the switching operation. Transistors P31 and N
When both 31 are turned on, the input terminal and the output terminal become conductive, and when both the transistors P31 and N31 are turned off, the input terminal and the output terminal become non-conductive.

The above-described embodiment is an example, and does not limit the present invention. For example, the specific circuit configuration may be different from that shown in FIG. 5, and various modifications are possible as needed. Also, as an example of the voltage value,
Although the power supply voltage VDD was 3 V and the power supply voltage VWELL was 5 V,
The value can be set to another value as long as the relationship of VDD> VWELL is satisfied.

[0035]

As described above, when the analog switch circuit of the present invention receives a signal having a voltage higher than the first power supply voltage, the analog switch circuit has the second potential having the same potential as the signal voltage.
By controlling the operation of the analog switch by generating the power supply voltage, it is possible to prevent a phenomenon that the transistor constituting the analog switch is forcibly turned on when it should be turned off and malfunctions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an analog switch circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a gate voltage control circuit in the analog switch circuit.

FIG. 3 shows a power supply voltage VWE generated by the gate voltage control circuit.
4 is a graph showing characteristics of LL.

FIG. 4 is a circuit diagram showing a configuration of a level shifter in the analog switch circuit.

FIG. 5 is a circuit diagram showing an example of the configuration of the analog switch circuit.

FIG. 6 is a time chart showing a relationship between an analog signal, a power supply voltage VDD, and a power supply voltage VWELL input to the gate voltage control circuit of the analog switch circuit.

FIG. 7 is a circuit diagram showing a configuration of a conventional analog switch circuit.

FIG. 8 is a longitudinal sectional view showing a sectional structure of a P-channel type MOS transistor and an N-channel type MOS transistor in a semiconductor substrate in the analog switch circuit.

FIG. 9 is a graph showing input / output characteristics of a gate voltage control circuit configured using a normal P-channel MOS transistor.

FIG. 10 is a graph showing input / output characteristics of a gate voltage control circuit formed using a P-channel MOS transistor having a low threshold voltage.

[Explanation of symbols]

Reference Signs List 11 analog switch 12 level shifter 13 gate voltage control circuit 101 P-type semiconductor substrate 102 P-type well 103 N-type well 104, 105 N-type impurity diffusion layer 106, 107 P-type impurity diffusion layer 108 P ⁺ -type impurity diffusion layer 109 N ⁺ -type Impurity diffusion layers G1, G2 Gate D1 Diodes P11, P12, P21, P22 P-channel MOS
Transistors N21, N22 N-channel MOS transistors EN, EN1 Enable signal VDD, VWELL Power supply voltage ND1, ND2 Nodes IN11, IN12, IN13 Enable

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-252241 (JP, A) JP-A-63-86615 (JP, A) JP-A-6-169247 (JP, A) JP-A-3- 52010 (JP, A) JP-A-6-283675 (JP, A) JP-A-2000-244298 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00

Claims (5)

(57) [Claims] An input signal and a first power supply voltage;
When the voltage of the input signal is equal to or lower than the first power supply voltage, it has the same voltage as the first power supply voltage, and when the voltage of the input signal exceeds the first power supply voltage, A gate voltage control circuit that generates and outputs a second power supply voltage having the same voltage as the voltage, and a second power supply voltage supplied thereto, and a supplied first enable signal according to the second power supply voltage A level shifter that level-shifts and outputs as a second enable signal; an analog switch that receives the second enable signal, controls a switching operation, and outputs the input signal given when the switch is closed; An analog switch circuit comprising: 2. The P-channel type M analog switch, the operation of which is controlled based on the second enable signal.
2. The analog switch circuit according to claim 1, further comprising an OS transistor, wherein the second power supply voltage is applied to an N-type well in which the P-channel MOS transistor is formed. 3. A gate voltage control circuit comprising: a first P-channel MOS transistor having a drain supplied with the first power supply voltage and a gate supplied with the input signal; and a drain supplied with the input signal. And the first
And a second P-channel MOS transistor to which the power supply voltage is input, and wherein the second power supply voltage is output from the sources of the first and second P-channel MOS transistors. Item 3. An analog switch circuit according to item 1 or 2. 4. The third and fourth P-channel type M level shifters each having a source to which the second power supply voltage is input and a gate and a drain cross-coupled.
An OS transistor; a first inverter that receives and inverts the first enable and outputs a first inversion enable signal; and an inverter that receives and inverts the first inversion enable and outputs the first enable signal. A first N-channel type having a drain connected to the drain of the third P-channel type MOS transistor, a gate receiving the inverted first enable signal, and a source grounded. A second N-channel MOS transistor having a drain connected to a drain of the fourth P-channel MOS transistor, a gate receiving the first enable signal, and a source grounded; 2 operates by being supplied with the power supply voltage of
4. The analog according to claim 1, further comprising: a third inverter having an input connected to a drain of the channel type MOS transistor and outputting the second enable signal from an output. Switch circuit. 5. The analog circuit according to claim 1, wherein said gate voltage control circuit uses a transistor having a low threshold voltage as said first and second P-channel MOS transistors. Switch circuit.