JP2003229748A - Analog switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely suppress flowing of an excessive current in an element from an input side in an analog switching circuit. <P>SOLUTION: A well potential NW of a PMOS P1 of the analog switch 10 is controlled by a well potential control circuit 30. The circuit 30 is provided with a PMOS P2 and an NMOS N2, wherein mutual gates and mutual drains are connected, and a well potential NW is supplied form the drains. The P2 receives an input AIN of the analog switch by its source, a source and a gate of the N2 are connected, and the source receives a power source potential VDD of the analog switching circuit. When the power source VDD is off, the well potential NW is supplied from the input AIN, and potential difference is not caused between the input AIN and the well. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a technique relating to an analog switch circuit used in an LSI.

[0002]

2. Description of the Related Art Recently, in LSI technology, a so-called system-on-chip technology has become mainstream in which all elements are integrated into one chip. Also, analog circuits tend to be incorporated in LSIs, and it is no exaggeration to say that analog switches are now included in any LSI.

FIG. 11 is a schematic diagram showing an example of the configuration of an analog switch. MOs with different polarities connected in parallel
The gate potentials of the S transistors P1 and N1 are the potentials PG and N.
It is controlled by G and is in the ON state,
The analog signal input from the input side AIN is the output side AO
Transmitted to the UT.

[0004]

In recent mobile devices such as mobile phones, low power consumption has become an important need. In the future, when further power consumption reduction is required, multiple LSIs on the system or LSI
There is a possibility that some of the functional blocks inside will be cut off. An analog switch is indispensable to realize such a function.

However, in the conventional analog switch,
Current flows through the parasitic diode due to the potential difference,
There is a problem that unnecessary power consumption, malfunction, or element destruction may occur.

For example, in the configuration of FIG. 11, the input AIN
When a voltage higher than the power supply voltage is applied to the
When a voltage is applied to the input AIN while the power source of I is off, a large current CR is applied to the input AIN via the parasitic diode PD formed between the input AIN and the substrate (well) of the PMOS P1. Might flow from the power supply to the power supply VDD. This current CR causes destruction of elements, malfunction of the system, and unnecessary power consumption.

Due to such a problem, in the past, the analog switch was constructed as a separate component, or the power supply to some functional blocks was cut off.

In view of the above problems, it is an object of the present invention to reliably prevent an excessive current from flowing from the input side into the element in an analog switch circuit.

[0009]

In order to solve the above-mentioned problems, the solving means taken by the invention of claim 1 is, as an analog switch circuit, a first P-type transistor and a first P-type transistor connected in parallel. An analog switch having an N-type transistor, a gate control circuit that controls ON / OFF of the analog switch according to a control signal, and a well that controls the well potential of the first P-type transistor using the input of the analog switch. And a potential control circuit.

According to the invention of claim 1, the well potential of the first P-type transistor of the analog switch is controlled by the well potential control circuit using the input of the analog switch. Therefore, the analog switch input and the first
It is possible to control so that no potential difference is generated between the well of the P-type transistor and the well. Therefore, it is possible to prevent an excessive current from flowing from the input side.

Further, in the invention of claim 2, the well potential control circuit in the analog switch circuit of claim 1 includes a second P-type transistor and a second N-type transistor whose gates and drains are connected to each other. A well potential of the first P-type transistor is supplied from its drain, the second P-type transistor receives the input potential of the analog switch at its source, and the second N-type transistor is The source and the gate are connected to each other, and the source receives the power supply potential of the analog switch circuit.

According to the invention of claim 3, said claim 1
The well potential control circuit in the analog switch circuit includes a second N-type transistor and a second P-type transistor whose gates are connected to each other and drains are connected to each other, and the well potential control circuit supplies the well potential of the first P-type transistor from its drain. The second N-type transistor has a source and a gate connected to each other, the source receives the input potential of the analog switch, and the second P-type transistor has the source connected to the analog switch. It shall receive the power supply potential of the circuit.

According to the invention of claim 2 or 3,
When the power supply of the analog switch circuit is OFF, the well potential of the first P-type transistor is supplied from the input of the analog switch via the second P-type transistor or the second N-type transistor. Therefore, it is possible to control so that no potential difference is generated between the input of the analog switch and the well of the first P-type transistor.

In the invention of claim 4, the invention according to claim 1
The gate control circuit in the analog switch circuit of (1) has a first inverter that receives the control signal as an input and the well potential as a power supply potential, a second inverter that receives the output of the first inverter, and the analog circuit. A third inverter that receives the power supply potential of the switch circuit and uses the well potential as the power supply potential, and a second P-source that receives the power supply potential of the analog switch circuit and a gate that receives the output of the third inverter. Type transistor and a source, the source of which is connected to the drain of the second P-type transistor, the gate of which receives the output of the second inverter and the drain of which is connected to the output line of the first inverter. A P-type transistor, and a gate of the first P-type transistor from the output line of the first inverter. It is assumed that the supply bets potential.

According to the invention of claim 5, said claim 1
A gate control circuit in the analog switch circuit, wherein a first NAND gate having the control signal and the stop signal as an input and having the well potential as a power supply potential;
An inverter that receives the output of the first NAND gate, a second NAND gate that receives the power supply potential of the analog switch circuit and the stop signal and receives the well potential as the power supply potential, and a source of the analog switch circuit. A second P-type transistor that receives a power supply potential and a gate that receives the output of the second NAND gate, a source connected to the drain of the second P-type transistor, and a gate that receives the output of the inverter A drain is provided with a third P-type transistor connected to the output line of the first NAND gate, and the gate potential of the first P-type transistor is supplied from the output line of the first NAND gate.

According to the invention of claim 6, the invention according to claim 1
The gate control circuit in the analog switch circuit of (1) receives the control signal as an input, a level shifter having the well potential as a power supply potential, a first inverter having an output of the level shifter as an input, and a power supply potential of the analog switch circuit. A second inverter that receives the power supply potential of the analog switch circuit at its source and has its second gate at its gate
Second P-type transistor for receiving the output of the inverter, a source connected to the drain of the second P-type transistor, a gate for receiving the output of the first inverter, and a drain for the output line of the level shifter. And a third P-type transistor connected to the level shifter for supplying the gate potential of the first P-type transistor from the output line of the level shifter, wherein the level shifter has an intermediate potential when the control signal is at an intermediate potential. , The intermediate potential is raised to the well potential and output.

According to the invention of claim 7, said claim 1
The gate control circuit in the analog switch circuit of, a level shifter having the control signal and the stop signal as an input and having the well potential as a power supply potential, an inverter having an output of the level shifter as an input, and a power supply potential of the analog switch circuit. A NAND gate having the stop signal as an input and having the well potential as a power source potential, a second P-type transistor having a source receiving the power source potential of the analog switch circuit and having a gate receiving an output of the NAND gate, and a source having the second A second P-type transistor connected to the drain of the second P-type transistor, the gate of which receives the output of the inverter and the drain of which is connected to the output line of the level shifter; First P-type transistor It is intended to supply a gate potential,
The level shifter raises the intermediate potential to the well potential and outputs the intermediate potential when the control signal has an intermediate potential, and fixes the output when the stop signal has a negative logic level. I shall.

According to the invention of claim 8, said claim 1
The analog switch in the analog switch circuit of
A second P-type transistor connected in series with the first P-type transistor is provided.

According to a ninth aspect of the present invention, there is provided a means for solving an analog switch circuit, comprising an analog switch having a first P-type transistor and a first N-type transistor connected in parallel and a control signal. A gate control circuit for ON / OFF controlling the analog switch, wherein the gate control circuit receives the control signal as an input, and uses a well potential of the first P-type transistor as a power supply potential; A second inverter having an output of the first inverter as an input, a third inverter having a power supply potential of the analog switch circuit as an input and having the well potential as a power supply potential, and a power supply potential of the analog switch circuit as a source. A second P-type transistor for receiving the output of the third inverter at its gate Source connected to the drain of said second P-type transistor, and the drain with receiving the output of said second inverter gate the first
And a third P-type transistor connected to the output line of the first inverter, and the gate potential of the first P-type transistor is supplied from the output line of the first inverter.

According to a tenth aspect of the present invention, there is provided a solution according to an analog switch circuit having an analog switch having a first P-type transistor and a first N-type transistor connected in parallel, and a control signal. And a gate control circuit for controlling the on / off of the analog switch, wherein the gate control circuit receives the control signal and the stop signal as input and uses the well potential of the first P-type transistor as a power supply potential. An inverter that receives the output of the first NAND gate, a second NAND gate that receives the power supply potential of the analog switch circuit and the stop signal as input, and the well potential is the power supply potential, and the source of the analog switch. The second NAND is applied to the gate while receiving the power supply potential of the circuit. A second P-type transistor for receiving the output of the inverter, a source connected to the drain of the second P-type transistor, a gate for receiving the output of the inverter, and a drain for the output of the first NAND gate. A third P-type transistor connected to the first line, and a third P-type transistor connected to the line from the output line of the first NAND gate to the first P-type transistor.
The gate potential of the type transistor is supplied.

According to the eleventh aspect of the present invention, there is provided a solution according to an analog switch circuit, which has an analog switch having a first P-type transistor and a first N-type transistor connected in parallel and a control signal. And a gate control circuit for ON / OFF controlling the analog switch. The gate control circuit receives the control signal as an input, a level shifter having a well potential of the first P-type transistor as a power supply potential, and an output of the level shifter. , A second inverter having the power supply potential of the analog switch circuit as an input and having the well potential as a power supply potential, the source receives the power supply potential of the analog switch circuit, and the gate has A second P-type transistor for receiving the output of the second inverter, and a saw A third P-type transistor having a gate connected to the drain of the second P-type transistor, a gate receiving the output of the first inverter, and a drain connected to the output line of the level shifter, The gate potential of the first P-type transistor is supplied from the output line of the level shifter, and the level shifter raises and outputs the intermediate potential to the well potential when the control signal is the intermediate potential. It is a thing.

According to a twelfth aspect of the present invention, there is provided a means for solving an analog switch circuit, comprising an analog switch having a first P-type transistor and a first N-type transistor connected in parallel and a control signal. And a gate control circuit for controlling on / off of the analog switch, wherein the gate control circuit receives the control signal and the stop signal as an input, and a level shifter for setting a well potential of the first P-type transistor as a power supply potential, and An inverter having the output of the level shifter as an input, a NAND gate having the power supply potential of the analog switch circuit and the stop signal as an input and having the well potential as the power supply potential, and a source receiving the power supply potential of the analog switch circuit and a gate. Second receiving the output of the NAND gate And P-type transistor, a source connected to the drain of said second P-type transistor, and, along with receiving the output of the inverter gate,
A third drain whose drain is connected to the output line of the level shifter.
And a gate potential of the first P-type transistor from the output line of the level shifter, and the level shifter outputs the intermediate potential when the control signal is the intermediate potential. The level is raised to the well potential and output, and
The output is fixed when the stop signal has a negative logic level.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the following description, the PchMOS transistor is abbreviated as "PMOS" and the NchMOS transistor is abbreviated as "NMOS". Further, for example, the PMOS P1 may be simply referred to as “P1”. Further, the HIGH level of the voltage level is "" H "", and the low level is "" L "".
Each is abbreviated.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of an analog switch circuit according to a first embodiment of the present invention. In FIG. 1, 10 is the first connected in parallel
Has a PMOS P1 as a P-type transistor and an NMOS N1 as a first N-type transistor,
, An analog switch that inputs AOUT and outputs AOUT, 20
Is an analog switch 1 according to the control signal CNT.
Reference numeral 30 denotes a gate control circuit that controls 0 to turn on and off, and 30 denotes a well potential control circuit that controls the well potential NW of the PMOS P1 of the analog switch 10 using the input AIN of the analog switch 10. The NMO of the analog switch 10
The well of SN1 is connected to ground.

The gate control circuit 20 is an inverter INV.
Input control signal CN having 1 and INV2
Depending on the potential of T, P1 and N1 of the analog switch 10
Control the gate potentials PG and NG of.

The well potential control circuit 30 has a PMOS P2 as a second P-type transistor and a NMOS N2 as a second N-type transistor whose gates and drains are connected to each other. The well potential NW of the PMOS P1 is supplied. The analog switch 1 is at the source of the PMOSP2
While the input potential AIN of 0 is received, the source and the gate of the NMOS N2 are connected, and the source receives the power supply potential VDD of the analog switch circuit.

The operation of the analog switch circuit of FIG. 1 will be described.

When "H" is input as the control signal CNT, the analog switch 10 is turned on, and the analog signal input AIN is transmitted as the output AOUT. At this time, the well potential NW of P1 in the well potential control circuit 30 is such that P2 is OFF and N2 is ON.
Since it is in the state, it is supplied from the power supply VDD.

On the other hand, when "L" is input as the control signal CNT, the analog switch 10 is OF
F In this case, in the normal state, that is, when the power source of the analog switch circuit itself is ON and the input AIN is equal to or lower than the power source potential VDD, P2 in the well potential control circuit 30 is OFF state and N2.
Is in the ON state, the well potential NW of P1 is the power source V
Given by DD. On the other hand, in the standby state, that is, when the power supply VDD is OFF, or even when the power supply VDD is ON, the input AIN is at the power supply potential VDD.
Well potential control circuit 30, P2
Turns on and N2 turns off, so the well potential NW of P1 is given from the input AIN.

As described above, according to this embodiment, the well potential NW of P1 becomes a diode N2 in a normal state.
Is raised to the power supply potential VDD via P2, and is raised to the input potential AIN via P2 in the standby state. Therefore, it is possible to prevent a leak current from flowing from the input AIN to the power supply VDD via the parasitic diode PD formed between the source of P1 and the well.

(Second Embodiment) FIG. 2 is a circuit diagram showing a configuration of an analog switch circuit according to a second embodiment of the present invention. 2, constituent elements common to FIG. 1 are assigned the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted here.

In FIG. 2, the PMO of the analog switch 10 is
The well potential NW of SP1 is controlled by a well potential control circuit 30A having an NMOS N3 as a second N-type transistor and a PMOS P3 as a second P-type transistor. Gates and drains of the NMOS N3 and the PMOS P3 are connected to each other, and the well potential NW of P1 is supplied from the drain. NMO
The source and gate of SN3 are connected, and the source receives the input potential AIN of the analog switch 10, while the PMOS P3 receives the power supply potential VDD of the analog switch circuit at the source.

The operation of the analog switch circuit of FIG. 2 will be described.

When "H" is input as the control signal CNT, the analog switch 10 is turned on and the input A
IN is transmitted as the output AOUT. At this time, P1
When the input AIN is "H", the well potential NW is given from the input AIN because N3 is ON and P3 is OFF in the well potential control circuit 30A, while the input AIN is "L". Is supplied from the power supply VDD because N3 is in the OFF state and P3 is in the ON state in the well potential control circuit 30A.

On the other hand, when "L" is input as the control signal CNT, the analog switch 10 is OF
F In this case, in the normal state, the well potential NW of P1 is P3 when the input AIN is "H" and N3 is in the ON state in the well potential control circuit 30A.
Since 3 is in the OFF state, it is supplied from the input AIN, while when the input AIN is "L", N3 is in the OFF state and P3 is in the ON state in the well potential control circuit 30A, so that it is supplied from the power supply VDD. On the contrary,
In the standby state, N3 is on and P3 is off in the well potential control circuit 30A, so the well potential NW of P1 is given from the input AIN.

As described above, according to this embodiment, in the normal state, the well potential NW of P1 is up to the input potential AIN when the input AIN is "H", and when the input AIN is "L", the power source potential VW.
It is pulled up to DD, and in the standby state, it is pulled up to the input potential AIN. Therefore, it is possible to prevent a leak current from flowing from the input AIN to the power supply VDD via the parasitic diode PD formed between the source of P1 and the well.

In the first embodiment, when the input AIN is "L", the well potential NW is a potential dropped from the power supply potential VDD by the threshold voltage of N2, but in the present embodiment, it is in the normal state. When input AIN is “L”, P3 is O
Since the well potential NW of P1 is applied from the power supply VDD in the N state, the well potential NW does not drop from the power supply potential VDD by the threshold voltage.

Since the circuit of FIG. 2 has the parasitic diode PD at P1, even if N3 is omitted in the well potential control circuit 30A, it operates as an analog switch circuit in the same manner as this embodiment.

(Third Embodiment) FIG. 3 is a circuit diagram showing a configuration of an analog switch circuit according to a third embodiment of the present invention. 3, constituent elements common to FIG. 1 are assigned the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted here. In FIG. 3, a well potential control circuit 30B that controls the well potential NW of P1 is configured by combining the well potential control circuit 30 according to the first embodiment and the well potential control circuit 30A according to the second embodiment. ing.

The operation of the analog switch circuit of FIG. 3 will be described.

When "H" is input as the control signal CNT, the analog switch 10 is turned on and input A
IN is transmitted as the output AOUT. At this time, P1
When the input AIN is “H”, the well potential NW is given from the input AIN and the power supply VDD while N3 and N2 are in the ON state and P2 and P3 are in the OFF state in the well potential control circuit 30B. When AIN is "L", P3 and N2 in the well potential control circuit 30B
Is on and P2 and N3 are off, so that power is supplied from the power supply VDD.

On the other hand, when "L" is input as the control signal CNT, the analog switch 10 turns off.
F In this case, in the normal state, when the input AIN is “H”, the well potential NW of P1 is the input AIN because N3 and N2 are in the ON state and P2 and P3 are in the OFF state in the well potential control circuit 30B. And power V
On the other hand, when the input AIN is “L” while being given from DD, P3 and N2 are O in the well potential control circuit 30B.
Since it is in the N state and P2 and N3 are in the OFF state, the power source V
Given by DD. On the other hand, in the standby state, the well potential control circuit 30B has N3, P2
Is ON and P3 and N2 are OFF,
The well potential NW of P1 is given from the input AIN.

As described above, also in this embodiment, as in the first or second embodiment, the leak current is supplied from the input AIN via the parasitic diode PD formed between the source of P1 and the well. It can be prevented from flowing into VDD.

Also in the present embodiment, similarly to the second embodiment, when the input AIN is "L" in the normal state, P3 is turned on and the well potential NW of the power supply VDD to P1.
Is given, the well potential NW does not drop from the power supply potential VDD by the threshold voltage. Further, when the input AIN is “H” in the normal state, the well potential NW is
Since it is given from both DD and input AIN, more stable operation can be performed.

Since the circuit of FIG. 3 also has the parasitic diode PD in P1, even if N3 is omitted in the well potential control circuit 30B, it operates as an analog switch circuit in the same manner as this embodiment.

(Fourth Embodiment) If the output side of the analog switch is not Hi-Z (high impedance), there is a possibility that a leak current may flow out from the output end. For example, a circuit composed of a resistor connected in series between the power supply VDD and the ground as shown in FIG. 4A or another analog switch as shown in FIG. 4B is connected to the output AOUT of the analog switch. If the analog switch is turned off,
If the state does not occur, a leak current will flow out from the output AOUT.

Therefore, in order to avoid such a problem, when the analog switch is OFF, the OF is surely performed.
The gate potential of the transistor must be controlled so that the F state is reached.

Therefore, in this embodiment, the gate potentials PG and NG of the analog switch are used by using the well potential NW of P1.
Shall be controlled. However, when the configuration shown in the first embodiment is used as the well potential control circuit, the well potential NW drops from the power supply potential VDD by the threshold voltage in the normal state, so that the well potential NW is kept as it is as the gate potential PG.
When used as, the extra current flows from the input AIN to the output AOUT even though the analog switch is OFF, and power is wasted. Therefore, it is necessary to consider this point in the gate control of the analog switch.

FIG. 5 is a circuit diagram showing the configuration of the analog switch circuit according to the fourth embodiment of the present invention. 5, constituent elements common to FIG. 1 are assigned the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted here. In the configuration of FIG. 5, the well potential NW of P1 is controlled by the well potential control circuit 30 according to the first embodiment, so P
The well potential NW is input to the first gate after raising the well potential NW by the threshold voltage.

The gate control circuit 40 is composed of a PMOS P4 and an NMOS N4, and has a control signal C
A first inverter 41 having NT as an input and a well potential NW of P1 as a power supply potential, and PMOS P5 and NMO
A second inverter 42 configured by SN5 and having the output of the first inverter 41 as an input; a third inverter 43 having the power supply potential VDD of the analog switch circuit as an input and having a well potential NW as a power supply potential; It has a PMOS P7 as a second P-type transistor and a PMOS P8 as a third P-type transistor connected in series between VDD and the output line of the first inverter 41. The output of the second inverter 42 is given to the gate of the PMOS P8, and the output of the third inverter 43 is PM.
It is given to the gate of OSP7.

All the PMOS wells except P5 are connected to the well potential NW. The substrate of P5 is connected to the power supply VDD.

The operation of the analog switch circuit of FIG. 5 will be described.

In the normal state, the control signal CN
When T is "H", the analog switch 10 is turned on and the input AIN is transmitted as the output AOUT. In this case, since the first inverter 41 outputs the ground potential, the gate potential PG is applied to P1 of the analog switch 10.
Is given as "L". The output of the first inverter 41, that is, "L", is input to the second inverter 42, so that the output thereof becomes "H". Further, the third inverter 43 outputs the ground potential. Therefore, the PMOS
P7 is turned on because "L" is input to the gate, while PMOS P8 is turned off because "H" is input to the gate.

On the other hand, in the normal state, when the control signal CNT is "L", N1 of the analog switch 10 is
Is directly supplied with “L” as the gate potential NG, and N1
Turns off. The first inverter 41 also outputs the well potential NW. The output of the second inverter 42 becomes "L" because the input is the well potential NW. Also, the third
The inverter 43 of outputs the ground potential. For this reason, both PMOS P7 and P8 are turned on.
The gate potential PG of P1 of the analog switch 10 becomes equal to the power supply potential VDD.

On the other hand, in the standby state,
The control signal CNT is “L”, the well potential NW output from the first inverter 41 is input to the second inverter 42, and the output becomes “L”. on the other hand,
The third inverter 43 outputs the well potential NW. Therefore, the PMOSP8 is turned on, while the PMOSP8 is turned on.
P7 is turned off. Therefore, the well potential NW is applied to P1 as the gate potential PG.

As described above, according to this embodiment, when the control signal CNT is "L" in the normal state, the well potential NW is the power supply potential VDD when the input AIN is "L".
However, by feeding back the second inverter 42, the gate potential PG of P1 can be raised by the threshold voltage to the same potential as the power supply potential VDD.
As a result, P1 can be reliably turned off.
Further, when AIN is "H" in the normal state or in the standby state, the well potential NW does not drop by the threshold voltage, so P1 is surely turned off.

Therefore, even if the circuit as shown in FIG. 4 is connected to the output AOUT, an extra leak current does not flow from the input AIN to the output AOUT. Of course, the well potential control circuit 30 can prevent a leak current from flowing from the input AIN to the power supply VDD via the parasitic diode. Instead of the well potential control circuit 30, the well potential control circuit according to the second or third embodiment or a circuit having another configuration may be provided.

(Fifth Embodiment) FIG. 6 is a circuit diagram showing a configuration of an analog switch circuit according to a fifth embodiment of the present invention. 6, constituent elements common to FIG. 5 are denoted by the same reference numerals as those in FIG. 5, and detailed description thereof will be omitted here. In FIG. 6, the gate and the source are connected to the power supply VDD, the drain is connected to the input line of the control signal CNT, and the gate and the source are the power supply V.
A PMOS P10 connected to DD and having a drain connected to the output line of the second inverter 42 is added to the configuration of FIG.

When actually configuring the analog switch circuit, the control signal CNT is input to the first inverter 41 via one or two inverters. At this time, in the circuit as shown in FIG. 5, the potential of the control signal CNT may rise due to the parasitic capacitance even when the power supply voltage VDD is 0 V in standby. Even in this case, since the PMOS has a parasitic diode, the potential of the control signal CNT does not exceed the built-in voltage of the parasitic diode. However, since the built-in voltage of the parasitic diode is not controlled in the manufacturing process, the potential of the control signal CNT becomes indefinite (~ 0.
V), a through current may flow in the first inverter 41. In addition, the power source V is also supplied to the second inverter 42.
A through current flows from DD to the ground. Furthermore, P1 and N1 of the analog switch 10 are turned on, and a current flows from the input AIN to the output AOUT.

Therefore, when the power supply potential VDD is 0V,
It is necessary to set the potential of the control signal CNT to approximately 0V. From such a point of view, the circuit of FIG. 6 is devised so that control management in manufacturing can be easily performed.

In the circuit of FIG. 6, in the standby state, when the power supply voltage VDD is 0V, the control signal C
The potential of NT and the gate potential of PMOS P8 can be brought close to 0V or can be controlled. Therefore, the analog switch 10 can be surely turned off, a through current to the first inverter 41 can be prevented by turning off N4, and the second inverter can be turned off by turning off P5. A through current to 42 can also be prevented. Further, when the power supply voltage VDD is “H”, no influence is exerted, and the circuit operation in the normal state is the same as that of the fourth embodiment.

(Sixth Embodiment) In the above fifth embodiment, by inserting the PMOSs P9 and P10,
The potential of the control signal CNT was positively brought close to 0V. However, in the circuit of FIG. 6, when the power supply potential VDD becomes the intermediate potential, for example, VDD × 0.5 or VDD × 0.3, the control signal CNT itself becomes the intermediate potential and P
Since the MOSP2, P4 to P8 and the NMOS N2 and N4 to N6 are all turned on, the input AIN to the output AOU
Through current flows from T, the input AIN to the ground, and from the power supply VDD to the ground.

Therefore, in the present embodiment, when there is room for receiving a control signal such as a standby signal on the system, the signal is used as a stop signal STOP, and any through current path from the input AIN or the power supply VDD to the ground is Try to cut it.

FIG. 7 is a circuit diagram showing the configuration of the analog switch circuit according to the sixth embodiment of the present invention. 7, constituent elements common to FIG. 5 are assigned the same reference numerals as those in FIG. 5, and detailed description thereof will be omitted here.

The gate control circuit 50 shown in FIG.
For the gate potential control circuit 40 shown in FIG.
1, P12 and NMOS N7, N8 are added. P11 is provided in parallel with PMOS P4, and N
7 is provided in series with the NMOS N4. Also P12
Is provided in parallel with PMOS P6, and N8 is NMO.
It is provided in series with SN6. And P11, P12
And a stop signal STO is applied to each gate of N7 and N8.
P is given.

P4, P11, N4 and N7 form a first NAND gate 51 which receives the control signal CNT and the stop signal STOP and uses the well potential NW as the power source potential. The gate potential PG of P1 is supplied from the output line of the first NAND gate 51. Also P
6, P12, N6 and N8 form a second NAND gate 53 which receives the power supply potential VDD of the analog switch circuit and the stop signal STOP and uses the well potential NW as the power supply potential. The output signal is input to the gate of P7.

Further, the well potential NW is applied to the source of P5.
And the gate signal NG of N1 is supplied from the inverter 52. The well potential NW is supplied to all the PMOS substrates.

The operation of the analog switch circuit of FIG. 7 will be described.

When the stop signal STOP is "H", the same operation as in the fourth embodiment is performed in the normal state and the standby state. Therefore, when the power supply voltage VDD does not become 0V in the standby state, the first NAND gate 5
1, input to the inverter 52, the second NAND gate 53
A through current flows from IN or the power supply VDD. Also,
A through current also flows when the power supply potential VDD is an intermediate potential.

On the other hand, when the stop signal STOP is "L", N7 is turned off and P11 is turned on in the first NAND gate 51, so that the well potential NW is always maintained.
Is output and P1 is a well potential N as a gate potential PG.
Receive W. Further, since the inverter 52 receives the output of the first NAND gate 51, that is, the well potential NW, it always outputs the ground potential. Therefore, N1 receives the ground potential as the gate potential NG and is always in the OFF state. In addition, N8 is also OF in the second NAND gate 53.
It becomes the F state. In this state, the well potential NW is always equal to or higher than the input AIN, so that P1 is also in the OFF state and the analog switch 10 is surely turned OFF. That is, even if any potential including the intermediate potential is input as the control signal CNT, the analog switch 10 is always in the OFF state, and the through current does not flow in any transistor.

Therefore, when a control signal such as a standby signal can be secured on the system, the stop signal S
By inputting "L" as TOP, a through current does not flow in any transistor even when the power supply potential VDD and the control signal CNT are at an intermediate potential. That is, by using the stop signal STOP,
A stable analog switch with no leakage current can be realized.

Instead of the well potential control circuit 30, a well potential control circuit according to the second or third embodiment or a circuit having another structure may be provided.

(Seventh Embodiment) In the above-described sixth embodiment, when the stop signal STOP is "H", the through current as described above flows. If a control signal such as a standby signal cannot be secured on the system, this through current must be suppressed by some means without using the stop signal STOP. Therefore, in the present embodiment, the through current is prevented from flowing in the standby state when the power supply voltage VDD is not 0 V or when the control signal CNT is the intermediate potential.

FIG. 8 is a circuit diagram showing the configuration of the analog switch circuit according to the seventh embodiment of the present invention. 8, constituent elements common to FIG. 5 are assigned the same reference numerals as those in FIG. 5, and detailed description thereof will be omitted here.

In the gate control circuit 60 shown in FIG.
For the gate potential control circuit 40 shown in FIG.
3 and NMOSs N9, N10 and N11 are added. P13 and N9 are connected in series and are provided in parallel with P4 and N4. And both gates are P
Connected to the gate of 1 and the ends connected to each other are P
4 gates. Further, N10 and N11 are connected in series and connected to the input line of the control signal CNT and P4.
, The well potential NW is applied to the gate of N10 and the power supply potential VDD is applied to the gate of N11.
Are given respectively.

P4, P13, N4, N9, N10, N1
1 constitutes a level shifter 61 which receives the control signal CNT as an input and uses the well potential NW as a power source potential. When the control signal CNT has the intermediate potential, the level shifter 61 raises the intermediate potential to the well potential NW and outputs it.

The source of P5 is given the well potential NW as in the sixth embodiment. A first inverter 62 is formed by P5 and N5. further,
A resistor R1 is inserted between P6 and N6,
6, and the resistor R1 form a second inverter 63.

The operation of the analog switch circuit of FIG. 8 will be described.

In the normal state, the control signal CNT
Is "H", N4 is ON in the level shifter 61
On the other hand, N9 turns off and P13
Is turned on, the gate potential of P4 becomes a potential corresponding to the well potential NW, that is, "H", and P4 is turned off. Therefore, the gate potential PG of P1 becomes the ground potential, and P1 is turned on. Further, since the output of the level shifter 61, that is, the gate potential PG is the ground potential, the output of the first inverter 62 becomes a potential corresponding to the well potential NW, that is, "H". As a result, the gate potential NG of N1 becomes the well potential NW, so that N1 becomes O
It becomes N state. Further, P8 is turned off because "H" is input to the gate. On the other hand, since the output of the second inverter 63 is at the ground potential, P7 is given "L" to the gate and turned on. At this time, the analog switch 10 is ON
Because of the state, a current flows from the input AIN to the output AOUT, but no through current flows in other transistors.

On the other hand, in the normal state, when the control signal CNT is "L", the level shifter 61 outputs N4.
Turns off, and N10 and N11 turn on, so P4 turns on because "L" is input to the gate. Therefore, P
The gate potential PG of 1 becomes the well potential NW, that is, "H", and P1 is turned off. N9 is turned on, P13 is turned off, and the output of the first inverter 62 becomes the ground potential. Therefore, the gate potential NG of N1 becomes the ground potential, so that N1 is turned off. Also, P8 is turned on. On the other hand, since the output of the second inverter 63 is at the ground potential, P7 is given "L" to the gate and turned on. P
Since 7, P8 are turned on, the power supply potential VDD is fed back to the gate potential PG of P1, and P1 is surely turned off. At this time, a through current does not flow from the input AIN to the output AOUT, or from the input AIN or the power supply VDD to the ground.

In the standby mode, the control signal C
NT and the power supply potential VDD become 0V, and in the level shifter 61, N4 is turned off, N11 is turned off, and N9.
Turns on, P13 turns off, the gate potential of P4 becomes the ground potential, P4 turns on, the gate potential PG of P1 becomes the well potential NW given from the input AIN, and P1
Is turned off. The output of the first inverter 62 becomes the ground potential, and N1 is turned off because the gate potential NG becomes the ground potential. Also, P8 is turned on. on the other hand,
The output of the second inverter 63 becomes the well potential NW,
P7 is turned off. Therefore, the shoot-through current is the input AIN
From the output AOUT to the input AIN or the power supply V
It doesn't flow from DD to the ground.

Control signal CNT and power supply potential V
When both DD are at the intermediate potential, N10, N11, N4 and P4 are turned on and P13 is turned on in the level shifter 61.
Finally, the gate potential of P4 becomes the well potential NW and P4 is turned off. Therefore, the gate potential PG becomes 0V and P1 is turned on. The output of the first inverter 62 becomes a potential corresponding to the well potential NW, and the gate potential NG of N1 becomes equal to the well potential NW and the N1 is turned on. P8 turns off. However, the second inverter 6
In 3, N6 and P6 are turned on, the gate potential of P7 becomes an intermediate potential, and P7 is turned on.

In this case, in the second inverter 63, P6
A through current flows from VDD and AIN to the ground through N6 and N6. The resistor R1 is inserted between P6 and N6 in order to suppress this through current. Resistance R1
It is possible to control the peak value of the through current by changing the resistance value of. No through current flows through the other transistors. At this time, since the analog switch 10 is ON, the input AIN changes to the output AOUT.
An electric current flows through.

As described above, according to the present embodiment, the through current only flows through the second inverter 63 when the control signal CNT and the power supply potential VDD are at the intermediate potential, and in the other cases, the through current flows. No current flows.
Therefore, it is possible to realize a stable analog switch in terms of leakage current without using the stop signal as shown in the sixth embodiment.

Instead of the well potential control circuit 30, a well potential control circuit according to the second or third embodiment or a circuit having another structure may be provided.

(Eighth Embodiment) FIG. 9 is a circuit diagram showing a configuration of an analog switch circuit according to an eighth embodiment of the present invention. In the configuration of FIG. 9, the gate control circuit 70 is configured by combining the gate control circuit 50 according to the sixth embodiment shown in FIG. 7 and the gate control circuit 60 according to the seventh embodiment shown in FIG. There is. 71 is a stop signal ST
A level shifter configured to receive OP, 72 is an inverter, and 73 is a NAND gate in which a resistor R1 is inserted. Further, a well potential control circuit 30B according to the third embodiment shown in FIG. 3 is provided.

The level shifter 71 is configured by combining the NAND gate 51 shown in FIG. 7 and the level shifter 61 shown in FIG. 8, and is provided between the gate of P4 and the drain of N9, and has a stop signal STOP at its gate.
An NMOS N12 for receiving the signal is added. When the stop signal STOP is 0V and the control signal CNT and the power supply potential VDD are intermediate potentials, the gate potential PG of P1 becomes the well potential NW given from the input AIN, so that N9 turns on and the CNT terminal outputs N9. An electric current flows through it to the ground. N12 is inserted to cut this current path.

When the stop signal STOP is "H",
The same operation as in the seventh embodiment described above is performed. When the control signal CNT and the power supply potential VDD are intermediate potentials,
A through current flows through the NAND gate 73, and the peak value of the current can be controlled by the resistor R1. On the other hand, when the stop signal STOP is "L", the control signal CN
P1 in the level shifter 71 regardless of the potential of T
1 is ON and N7 is OFF, so the gate potential PG of P1
Becomes a potential corresponding to the well potential NW. The states of the inverter 72, the NAND gate 73, P7, and P8 are the sixth.
The same as in the embodiment.

As described above, according to the present embodiment, when the stop signal STOP is 0 V, the through current or the output AOU from the input AIN is output in all cases including the power supply potential VDD and the control signal CNT being the intermediate potential.
No current flows to T. Also, the stop signal S
When TOP is “H”, when the control signal CNT and the power supply potential VDD are intermediate potentials, the NAND gate 7
Only a through current flows from VDD and AIN to the ground via the line 3. Therefore, it is possible to realize an extremely stable analog switch in terms of leakage current.

(Ninth Embodiment) FIG. 10 shows a ninth embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of an analog switch circuit according to the exemplary embodiment. In the configuration of FIG. 10, the analog switch 10
A includes a PMOSP1 ′ as a second P-type transistor connected in series with the PMOSP1.
A well potential control circuit 30a for controlling the well potential of the MOSP1 'is provided. A1 and A2 are P1,
It is a gate control circuit that controls the gate potential of P1 ′ by using each well potential.

Output AOUT side is power supply VDD and input A
When the voltage becomes higher than IN, that is, when the circuit as shown in FIG. 4 is connected to the output AOUT and the power supply is a power supply different from the power supply VDD of the analog switch circuit, the input AIN and A current may flow between the output AOUT and the output AOUT. The present embodiment is made to prevent this current.

That is, by connecting the two PMOSs P1 and P1 'in series in the analog switch 10A, it is possible to prevent current from flowing from either side of the input AIN and the output AOUT of the analog switch 10A.

In FIG. 10, the well potential control circuit has the configuration shown in the first embodiment, but the second or third well potential control circuit is shown.
The circuit shown in the embodiment may be used. Further, as the gate control circuits A1 and A2, any circuit of the fourth to eighth embodiments may be used.

[0095]

As described above, according to the present invention, when a voltage higher than the power source voltage is applied to the input side or the power source is turned off.
Even if voltage is applied to the input side in the state, PM
It is possible to prevent a leakage current flowing through the OS parasitic diode. Moreover, a stable analog switch circuit can be realized from the viewpoint of leakage current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an analog switch circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an analog switch circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an analog switch circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration example of a circuit connected to an output side of an analog switch.

FIG. 5 is a circuit diagram showing a configuration of an analog switch circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of an analog switch circuit according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of an analog switch circuit according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an analog switch circuit according to a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of an analog switch circuit according to an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of an analog switch circuit according to a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating a problem of a conventional analog switch circuit.

[Explanation of symbols]

10, 10A Analog switch 20, 40, 40A, 50, 60, 70 Gate control circuit 30, 30a, 30A, 30B Well potential control circuit 41 First inverter 42 Second inverter 43 Third inverter 51 First NAND gate 52 inverter 53 second NAND gate 61 level shifter 62 first inverter 63 second inverter 71 level shifter 72 inverter 73 NAND gate P1 PMOS (first P-type transistor) N1 NMOS (first N-type transistor) P2 PMOS (second) P-type transistor) N2 NMOS (second N-type transistor) P3 PMOS (second P-type transistor) N3 NMOS (second N-type transistor) P7 PMOS (second P-type transistor) P8 PMOS (third) P-type transistor P1 'PMOS (second P-type transistor) AIN gate potential NW PMOSP1 power PG PMOSP1 input VDD analog switch circuit of the analog switch well potential CNT control signal STOP STOP signal

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F038 BG06 BG10 DF01 DF17 EZ20                 5J055 AX28 BX17 CX24 CX27 DX22                       DX65 DX73 EX07 EY21 EY29                       EZ00 EZ07 EZ12 EZ20 EZ25                       FX37 GX01 GX02

Claims (12)

[Claims] 1. An analog switch having a first P-type transistor and a first N-type transistor connected in parallel, a gate control circuit for ON / OFF controlling the analog switch according to a control signal, and the first switch. And a well potential control circuit for controlling the well potential of the P-type transistor using the input of the analog switch. 2. The well potential control circuit according to claim 1, wherein the second P having the gates connected to each other and the drains connected to each other is connected to each other.
Type transistor and a second N-type transistor,
The drain supplies the well potential of the first P-type transistor, the second P-type transistor receives the input potential of the analog switch at the source, and the second N-type transistor is the source. An analog switch circuit in which a gate and a gate are connected to each other and a source receives a power supply potential of the analog switch circuit. 3. The second well N according to claim 1, wherein the well potential control circuit is configured such that:
Type transistor and a second P-type transistor,
The drain supplies the well potential of the first P-type transistor, the second N-type transistor has a source and a gate connected to each other, and the source receives the input potential of the analog switch. In the analog switch circuit, the second P-type transistor receives the power supply potential of the analog switch circuit at its source. 4. The gate control circuit according to claim 1, wherein the gate control circuit receives the control signal as an input, and a first inverter that receives the well potential as a power supply potential, and a second inverter that receives an output of the first inverter as an input. Inverter, and a third inverter that receives the power supply potential of the analog switch circuit as an input and uses the well potential as the power supply potential, a source that receives the power supply potential of the analog switch circuit, and a gate of the third inverter. A second P-type transistor receiving an output, a source connected to the drain of the second P-type transistor, a gate receiving the output of the second inverter, and a drain having an output of the first inverter. A third P-type transistor connected to a line, the output line of the first inverter from the first P-type Analog switch circuit which is characterized in that supplies a gate potential of the transistor. 5. The gate control circuit according to claim 1, wherein the control signal and the stop signal are input.
A first NAND gate having the well potential as a power supply potential, an inverter having an output of the first NAND gate as an input, a power supply potential of the analog switch circuit and the stop signal as inputs, and the well potential as a power supply potential A second NAND gate, a second P-type transistor whose source receives the power supply potential of the analog switch circuit and a gate which receives the output of the second NAND gate, and a source whose drain is the drain of the second P-type transistor. A third P-type transistor having a gate connected to the output line of the first NAND gate and a gate connected to the output line of the first NAND gate, and a drain connected to the output line of the first NAND gate. An analog circuit, which supplies the gate potential of the first P-type transistor. Gusuitchi circuit. 6. The gate control circuit according to claim 1, wherein the gate control circuit receives the control signal as an input, a level shifter having the well potential as a power supply potential, a first inverter having an output of the level shifter as an input, and the analog circuit. A second inverter that receives the power supply potential of the switch circuit and uses the well potential as the power supply potential, and a second inverter that receives the power supply potential of the analog switch circuit at its source and receives the output of the second inverter at its gate. A P-type transistor and a third P-type transistor whose source is connected to the drain of the second P-type transistor and whose gate receives the output of the first inverter and whose drain is connected to the output line of the level shifter. A transistor of the first P-type transistor from the output line of the level shifter. Is intended to supply a preparative potential, said level shifter, the control when the signal is an intermediate potential, the analog switch circuit and outputting an intermediate potential level up to the well potential. 7. The level control circuit according to claim 1, wherein the gate control circuit receives the control signal and the stop signal as input, and the level shifter receives the well potential as a power supply potential, and an inverter receives the output of the level shifter as input. A NAND gate that receives the power supply potential of the analog switch circuit and the stop signal as input and uses the well potential as the power supply potential, and a second P that receives the power supply potential of the analog switch circuit at its source and the output of the NAND gate at its gate Type transistor and a third P-type transistor whose source is connected to the drain of the second P-type transistor and whose gate receives the output of the inverter and whose drain is connected to the output line of the level shifter. From the output line of the level shifter, the first The level shifter supplies a gate potential of a P-type transistor, and when the control signal is an intermediate potential, the level shifter raises the intermediate potential to the well potential and outputs the well potential, and the stop signal. An analog switch circuit characterized in that the output is fixed when is a negative logic level. 8. The analog switch circuit according to claim 1, wherein the analog switch includes a second P-type transistor connected in series with the first P-type transistor. 9. An analog switch having a first P-type transistor and a first N-type transistor connected in parallel, and a gate control circuit for controlling ON / OFF of the analog switch according to a control signal, A gate control circuit, a first inverter having the control signal as an input and having a well potential of the first P-type transistor as a power supply potential; and a second inverter having an output of the first inverter as an input, A third inverter having a power supply potential of the analog switch circuit as an input and having the well potential as a power supply potential; a third inverter having a source receiving the power supply potential of the analog switch circuit and a gate receiving an output of the third inverter; A second P-type transistor and a source connected to the drain of the second P-type transistor, And a third P-type transistor having a gate receiving the output of the second inverter and a drain connected to the output line of the first inverter, the output line of the first inverter from the output line of the first inverter. An analog switch circuit for supplying the gate potential of a first P-type transistor. 10. An analog switch having a first P-type transistor and a first N-type transistor connected in parallel, and a gate control circuit for controlling ON / OFF of the analog switch according to a control signal, The gate control circuit receives the control signal and the stop signal as input,
A first NAND gate having a well potential of the first P-type transistor as a power supply potential; an inverter having an output of the first NAND gate as an input; and a power supply potential of the analog switch circuit and the stop signal as inputs, A second NAND gate having the well potential as a power source potential, a second P-type transistor having a source receiving the power source potential of the analog switch circuit and a gate receiving an output of the second NAND gate, and a source being the first A second P-type transistor connected to the drain of the second P-type transistor, the gate of which receives the output of the inverter, and the drain of which is connected to the output line of the first NAND gate; The gate potential of the first P-type transistor is supplied from the output line of the NAND gate of Analog switch circuit according to claim Rukoto. 11. An analog switch having a first P-type transistor and a first N-type transistor connected in parallel, and a gate control circuit for controlling ON / OFF of the analog switch according to a control signal, A gate control circuit receives the control signal as an input, a level shifter having a well potential of the first P-type transistor as a power supply potential, a first inverter having an output of the level shifter as an input, and a power supply of the analog switch circuit. A second inverter having a potential as an input and having the well potential as a power source potential; and a second P-type transistor having a source receiving the power source potential of the analog switch circuit and a gate receiving an output of the second inverter. , The source is connected to the drain of the second P-type transistor, and A third P-type transistor whose drain receives the output of the first inverter and is connected to the output line of the level shifter, and the output line of the level shifter connects the first P-type transistor An analog switch circuit for supplying a gate potential, wherein the level shifter raises and outputs the intermediate potential to the well potential when the control signal is at the intermediate potential. 12. An analog switch having a first P-type transistor and a first N-type transistor connected in parallel, and a gate control circuit for ON / OFF controlling the analog switch according to a control signal, The gate control circuit receives the control signal and the stop signal as an input, a level shifter having a well potential of the first P-type transistor as a power supply potential, an inverter having an output of the level shifter as an input, and an analog switch circuit. A NAND gate having a power supply potential and the stop signal as an input and having the well potential as a power supply potential; and a second P-type transistor having a source receiving the power supply potential of the analog switch circuit and a gate receiving the output of the NAND gate, The source is the second P-type transistor A third P-type transistor connected to the drain and having the gate receiving the output of the inverter and having the drain connected to the output line of the level shifter; The level shifter supplies the gate potential of a well-type transistor, and when the control signal is an intermediate potential, the level shifter raises the intermediate potential to the well potential and outputs the well potential, and the stop signal is An analog switch circuit characterized in that it fixes the output when it is at a negative logic level.