JP4354126B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
  The present invention relates to a semiconductor integrated circuit device provided with a plurality of wiring layers.In placeThe present invention relates to a semiconductor integrated circuit device using standard cells.
[0002]
[Prior art]
As a method for designing a large-scale LSI, a design method called a standard cell method is used. This standard cell methodA circuit called a cellAre prepared, and these are combined to constitute an LSI.
[0003]
The layout and wiring process using the standard cell method is automatic placement and routing using software.Is possible to do.
[0004]
FIG. 1 shows an example of a conventional floor plan using standard cells. FIG. 1 is a plan view of a semiconductor integrated circuit device using standard cells. This semiconductor integrated circuit device includes a standard cell region 11 and two macro cells 12 in a chip 1.
[0005]
In the conventional floor plan method,
(1) Arrange standard cells and macro cells.
(2) Wire the power supply metal.
(3) Wire the signal line.
Is performed in three steps. Performing such a method with a tool is called automatic placement and routing.
[0006]
In FIG.Area 11 where standard cells are placedIs shown. The power supply wirings 21 and 22 are wired so as to surround the standard cell region 11 and the macro cell region 12. In the figure, reference numeral 21 denotes a power supply (Power) wiring, and reference numeral 22 denotes a grounding (Ground) wiring.
[0007]
FIG. 4 shows the basic structure of a standard cell (function). FIG. 4 is a pattern diagram of the standard cell 3 constituting the inverter shown in the circuit diagram of FIG. The standard cell 3 includes input / output terminals 3a and 3b, and a power source 21 and a ground 22 metal. The metal of the power source (Power) 21 and the ground (Ground) 22 is composed of a first layer metal (metal 1). Hereinafter, simply referring to the power supply (PG) includes these two wirings, the power supply (P) 21 and the ground (G) 22.
[0008]
As shown in FIG. 4, the standard cell 3 has power (PG) wiring made of metal near the lower layer. The case where such a standard cell 3 is used and the metal near the upper layer is used for the main power (PG) wiring of the chip will be described. FIG. 2 is a plan view of a semiconductor integrated circuit device showing an example in which an upper layer metal is used as a power supply (PG) wiring, and FIG. 3 is an enlarged view of a portion A in FIG.
[0009]
As shown in FIG. 2, when the metal near the upper layer is used for the main power (PG) wirings 21 and 22 of the chip.Standard cell area 11The connection of the metal layer occurs at the connection with the power supply wiring inside. As shown in the enlarged view of FIG.Standard cell area 11In order to connect the power supply wirings 21 ′, 22 ′ and the main power supply (PG) wirings 21, 22, the metal layer is changed through the via hole.
[0010]
On the other hand, since the signal wiring mainly uses the lower to middle metal layers, the power wiring that is wired before the signal wiring is an obstacle to the signal wiring. For this reason, the upper layer metal cannot be used as the power supply wiring, or even if it is used, sufficient consideration is required.
[0011]
[Problems to be solved by the invention]
As described above, using the upper metal layer as the power supply wiring has a problem that it takes a lot of time and labor during floor planning, such as editing a macro block and estimating the wiring route, and there is also a risk of an erroneous estimation. .
[0012]
In addition, with the progress of high integration by a fine process, a voltage drop in which supply of power supply voltage is insufficient has become a problem. Since the voltage drop largely depends on the resistance of the power supply wiring, it will continue to be a serious problem.
[0013]
Furthermore, although the wiring width of the power supply wiring greatly affects the high integration of the semiconductor integrated circuit, it is necessary to optimally set the wiring width of the power supply wiring in order to prevent a voltage drop. Accurate analysis is required to optimally set the wiring width of the power supply wiring, but as the use of multilayer metal for higher integration of semiconductor devices is progressing, the optimal wiring width of the power supply wiring is determined. It has become difficult to do.
[0014]
On the other hand, if there is a problem with the power analysis, power wiring can only be done before cell placement, so it will have to be redone from the floor plan, or a major correction will be required, so the final analysis will If there is a defect, the work period will be very long. Further, in order to avoid such a long construction period, excessive power supply wiring is performed in the floor plan so as not to cause a problem, and there is a high possibility of causing an increase in chip size.
[0015]
Various proposals have been made regarding power supply wiring. For example, Japanese Patent Laid-Open No. 05-047930 proposes a semiconductor device in which the standard cell is reduced to stabilize the power supply. This device does not have a power supply (PG) in a standard cell, and is connected to a power supply line (Rail) provided outside the cell after the cell is arranged.
[0016]
Since this apparatus does not have a power supply (PG) in the standard cell, it cannot be applied to a configuration having a power supply Rail inside the cell. Further, since the power supply (PG) is wired, the degree of freedom in layout is reduced.
[0017]
  Japanese Patent Application Laid-Open No. 05-047931 discloses a semiconductor device configured such that the power supply wiring becomes thicker toward the outside of the layout where the standard cell arrangement is sparse. However, this semiconductor device is not configured to use the upper layer metal as the power supply wiring. Also, since the place where the power supply is thickened is outside the layout, there is sufficient voltageDescentIt cannot be a countermeasure.
[0018]
The present invention has been made to solve the above-described conventional problems, and in a multi-metal process, an upper layer metal is less likely to interfere with signal wiring, and can be used as a power supply line. The object is to provide a circuit.
[0019]
[Means for Solving the Problems]
  The present invention relates to a semiconductor integrated circuit device formed by a multi-layer process using automatic placement and routing using standard cells.With the top metalA standard cell for power supply in which the metal under the first layer is provided on substantially the entire surface of the cell, the uppermost metal or the metal under the first layer is used as a power wiring, and the metal and the power line of the standard cell are connected. It is characterized by providing.
[0020]
  The standard cell of normal function is the uppermost metal or no connection relationship with the power line.With the top metalIt comprises so that the metal of the lower layer may be provided.
[0021]
As described above, when the power supply standard cell is a standard cell, it can be easily applied to a conventional flow. Once the power supply standard cell is created, the automatic placement and routing can be performed as usual.
[0022]
The power supply standard cell may be configured so as to include a transistor function element therein.
[0023]
  Transistor device inside with a power supply area next to the standard cellNohIf it is configured to include a child, the arrangement area increases, but there is sufficient connection with the power supply, so that the cell function can be guaranteed.
[0024]
In addition, by using a standard cell dedicated for power supply as a normal standard cell, there is no need to provide a power supply standard cell layout area, and the power supply standard cell can be applied without increasing the chip size. I can do it.
[0026]
  The present invention provides an uppermost metal layer having no connection relationship with the power supply line of the standard cell orWith the top metalA feature is that a slot is provided in the metal one layer below.
[0027]
With the structure as described above, a slot is generated only by arranging the standard cell, and it becomes a measure against metal stress. Such a structure is defined in the design rule, but in the present invention, the structure automatically satisfies the design rule in the standard cell region.
[0025]
What is necessary is just to selectively utilize each above-mentioned power supply standard cell according to a condition.
[0028]
  According to the present invention, at least one power supply standard cell according to claim 1 is arranged in the chip, and the uppermost metal or power supply standard cell to which the power supply standard cell is connected is provided.With the top metalWhat is necessary is just to comprise so that the metal of the lower layer may be used as a power supply wiring.
[0029]
By configuring as described above, a power-strap-less layout is possible, and no effort is required to pull the power-strap.
[0030]
Naturally, since there is no power supply strap, it is not necessary to consider time for estimation or the like for making the power supply strap have an appropriate width.
[0031]
In addition, the present invention may be configured such that the power supply standard cell is arranged in the vicinity of a cell with large power consumption.
[0032]
As described above, the cell performance can be guaranteed by arranging the power supply standard cell in the vicinity of the cell with large power consumption.
[0033]
Further, if the structure is such that power is supplied to the conventional standard cell (function), the function of the standard cell can be guaranteed.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same part as a prior art example.
[0037]
The embodiment of the present invention will be described using an example in which the uppermost metal (n) is a Power wiring and the wiring metal (n-1) one layer below the uppermost layer is a Ground wiring. In this example, six layers of multilayer wiring with n = 6 are shown.
[0038]
FIG. 6 shows a standard cell for power supply used in the present invention.
[0039]
  The power supply standard cell 4 includes a power wiring line (Power Rail) 21 as the uppermost metal layer and a ground wiring line (Ground Rail2) as a wiring metal (n-1) one layer below the uppermost layer.22Is connected. In FIG. 6, reference numeral 41 denotes a contact hole, 42 denotes a diffusion region, and 43 denotes a well.
[0040]
Then, as shown in FIG. 6A, diffusions 42 are respectively arranged under the power and ground rail (metal 1) metal located at both ends of the standard cell, and from the uppermost metal and the uppermost layer through the contact holes 41. Connect to the wiring metal one layer below. FIG. 2B shows a power supply standard cell, and FIG. 3C shows a ground supply standard cell.
[0041]
As shown in FIGS. 6B and 6C, the ground metal 22 is connected to the substrate through the diffusion 42, and the power metal 21 is connected to the well 43 through the diffusion 42. Both diffusions 42 and 42 can secure the potential of the substrate and the well 43.
[0042]
In the power supply standard cell 4 shown in FIG. 6B, the metal connected to the Power Rail (metal 1) of the basic standard cell (function) is connected to the uppermost layer.
[0043]
As shown in FIG. 6 (b), the Power-supplied standard cell 4 includes a first-layer ground rail (metal1), a first-layer via (via1), a second-layer metal (metal2), and two layers. Via (via 2), third layer metal (metal 3), third layer via (via 3), one layer below the uppermost layer metal (metal (n-1)), one layer below the uppermost layer It is connected to the uppermost metal layer n through vias (via (n−1)).
[0044]
  At this time, the wiring metal one layer below the uppermost layer is used as a ground wiring.bAs shown in FIG. 6, wiring is performed away from the periphery of the standard cell so as not to have a connection relationship even if other standard cells are arranged next to each other (FIG. 6 (bA part)).
[0045]
The ground-supplied standard cell shown in FIG. 6C is based on the standard cell Ground Rail (usually metal 1), the first layer via (via 1), the second layer metal (metal 2), the second layer via (via 2), 3 From the third layer metal (metal 3), the third layer via (via 3), the wiring metal (metal (n-2)) two layers below the top layer, and the via (via (n-2) two layers below the top layer )) To the metal n-1 which is one layer from the uppermost layer.
[0046]
At this time, whether or not the transistor (function) is included in the power supply standard cell 4 is matched to the intended use.
[0047]
  7 and 8 show an example in which a transistor (function) is provided in the power supply standard cell 4. FIG. 7 shows a region connected to the upper layer power supply wiring separately from the transistor arrangement portion 3.4aIt is configured with.
[0048]
Although the arrangement area is increased by arranging the standard cells as shown in FIG. 7, the cell function can be ensured because of sufficient connection with the power source.
[0049]
  FIG. 8 shows a structure in which the metals 23 to 26 are stacked with the same wiring width as that of the Power Rail part 21 or the Ground Rail part 22. In this example, the uppermost metal 27 is METAL6, and the metal 26 one layer below the uppermost layer is METAL5.As shown in FIG. 8, the METAL 6 is provided on the entire surface of the cell.As described above, the wiring metal one layer below the uppermost layer is used as a ground wiring. Therefore, in the example shown in FIG. 8, even if other standard cells are arranged next to each other, they have a connection relationship. The wiring is separated from the standard cell as shown by a in FIG.
[0050]
Further, by using a standard cell as shown in FIG. 8, it is not necessary to provide a power supply standard cell arrangement region, so that the power supply standard cell can be applied without increasing the chip size.
[0051]
FIG. 9 shows an example of a cell having a normal standard cell function used in the present invention.
[0052]
  As shown in FIG. 9, the normal standard cell includes a metal near the uppermost layer (the uppermost metal 27, one layer below the uppermost layer (the uppermost layer-1 metal) 26) that is not connected anywhere in the standard cell. .As shown in FIG. 9, the uppermost metal layer 27 and one layer below the uppermost layer (uppermost layer-1 metal) 26 are provided on the entire surface of the cell.
[0053]
FIG. 10 shows another example of a cell having a normal standard cell function used in the present invention. The example shown in FIG. 10 has a structure having slots 26b and 27b in wiring used for power supply wiring.
[0054]
By adopting the structure as shown in FIG. 10, a slot is generated only by arranging the standard cell, and it is a measure against metal stress. Such a structure is defined in the design rule, but in the present invention, the structure automatically satisfies the design rule in the standard cell region.
[0055]
In addition, for filler cells (also called feed cells) that fill the places where standard cells are not placed so as not to violate the design rules, the metal near the top layer that is not connected anywhere (top layer metal, top layer- 1) It has a structure with metal.
[0056]
11 and 12 show a basic embodiment using the standard cell of the present invention. FIG. 12 is a plan view showing an outline of the chip, and FIG. 13 is an enlarged view of a region surrounded by A in FIG. The configuration of the chip 1 is the same as the configuration shown in FIG. 1, and the present invention is applied to the standard cell region with respect to the example of the floor plan shown in FIG.
[0057]
FIG. 11 and FIG. 12 show an example in which one standard cell and one ground-supplied standard cell 4 a are arranged in the standard cell region 11.
[0058]
The standard cell region 11 has a standard cell (function), a power supply standard cell, and a filler cell (also referred to as a feed cell). The entire cell region 11 is wired with the uppermost layer metal 27 and the uppermost layer-1 metal 26. In FIG. 11, for the sake of simplicity, the uppermost metal layer 27 and the uppermost metal layer-1 26 are omitted for the sake of convenience.
[0059]
Comparing the paths from the power supply IO to the power supply standard cell in FIG. 11, in the conventional chip, the closest path is the path 1 (solid line), and in the present invention, the path 2 (dotted line). When the conventional chip and the chip of the present invention are compared, the path 2 (dotted line) of the present invention is closer to the conventional path (solid line).
[0060]
As shown in the enlarged view of FIG. 12, the PowerRail (metal 1) 21 of the power supply standard cell is connected to the power supply wiring (uppermost layer metal) 27 wired throughout the standard cell region 11 through the connection region 21a. . In addition, the Ground-Rail (metal 1) 22 of the ground supply standard cell is connected to the uppermost layer-1 metal 26 one layer lower than the uppermost layer metal wired in the entire standard cell region 11 through the connection region 22a.
[0061]
In addition, with respect to portions other than the standard region 11, after automatic placement and routing, the uppermost layer metal 27 and the uppermost layer-1 metal 26 are manually added, and the input / output portion of the power supply IO cell is set to an arbitrary metal (the uppermost layer metal, The top layer-1 metal) is connected. At this time, the macro cell is configured not to have the uppermost layer and the uppermost layer-1 metal.
[0062]
As described above, with regard to the power supply width as well, in the present invention, the power supply wiring (in this embodiment, metal5 and metal6) is made throughout the chip (CHIP), the single layer has the minimum resistance, and the power supply standard cell is reached. The effect of voltage drop can be reduced.
[0063]
The above-mentioned Power and Ground supply standard cells 4a may be inserted, for example, in consideration of a voltage drop or on the larger size side of the cells.
[0064]
Moreover, in the said embodiment, the noise cut effect is also acquired by covering the whole surface other than the IO cell of a chip | tip with the uppermost layer-1 metal 26. FIG.
[0065]
FIG. 13 shows a second embodiment using the standard cell of the present invention. FIG. 13 is a plan view showing the outline of the chip. In FIG. 13, cells indicated by white circlesButThe Power supply standard cell 41 and the cells indicated by white triangles are Ground supply standard cells.
[0066]
Power supply (PG) supply standard cells 41 and 42 are arranged as shown in FIG. At this time, the uppermost layer metal 27 and the uppermost layer-1 metal 26 are also wired to the entire chip excluding the IO cell regions 30 and 31 in the standard cell region. In FIG. 13, for the sake of simplicity, the uppermost metal layer and the uppermost metal layer-1 metal are omitted for the sake of convenience.
[0067]
The IO cell area 30 is a power cell area, and the IO cell area 31 is a ground cell area.
[0068]
A plurality of standard cells are arranged so as to have a predetermined width, or a large-size power supply standard cell is arranged. Further, power supply standard cells 41 and 42 are arranged in the power / ground supply source of the hard macrocells 12 and 12.
[0069]
By configuring as described above, the power supply wiring region that becomes the trunk line of the dotted line portion in FIG. 13 can be reduced without reducing the power supply amount as compared with the conventional chip (FIG. 1). As a result, as shown in the embodiment of FIG. 14 below, the chip size can be minimized without degrading the quality.
[0070]
FIG. 14 shows a third embodiment using the standard cell of the present invention. The third embodiment is an example in which the power supply wiring serving as a trunk line is removed from the second embodiment shown in FIG. In FIG. 14, the uppermost layer metal 27 and the uppermost layer-1 metal 26 are wired over the entire chip excluding the IO cell regions 30 and 31 also for the standard cell region 11 and the macrocell region 12. For this reason, even if the power supply wiring that becomes the trunk line is removed, power can be sufficiently supplied.
[0071]
In FIG. 14, for the sake of simplicity, the uppermost metal layer and the uppermost metal layer-1 metal are omitted for the sake of convenience.
[0072]
FIG. 15 shows a fourth embodiment using the standard cell of the present invention. In the fourth embodiment shown in FIG. 15, in addition to the third embodiment shown in FIG. 14, a plurality of power supply standard cells are arranged in the standard cell arrangement region 11 instead of the strap of the standard cell region. .
[0073]
If this invention is used, as shown in FIG. 15, the layout without a power supply strap becomes possible, and the effort which pulls a power supply strap is not required.
[0074]
Naturally, since there is no power supply strap, it is not necessary to consider time for estimation or the like for making the power supply strap have an appropriate width.
[0075]
In FIG. 15, the uppermost layer metal 27 and the uppermost layer-1 metal 26 are also provided for the standard cell region 11 and the macrocell region 12.IO cell areaWiring is performed throughout the entire chip. For this reason, even if the power supply wiring that becomes the trunk line is removed, power can be sufficiently supplied.
[0076]
In FIG. 15, for the sake of simplicity, the uppermost metal layer and the uppermost metal layer-1 metal are omitted for the sake of convenience.
[0077]
16 and 17 show a modification of the fourth embodiment using the standard cell of the present invention. In the embodiment shown in FIGS. 16 and 17, a cell 3 ′ with high power consumption is arranged in a region surrounded by A in the central portion. Then, as shown in the enlarged view of FIG. 17, the power supply standard cell 41 (42) is arranged so as to be adjacent to the cell.
[0078]
As described above, the cell performance can be guaranteed by arranging the power supply standard cell in the vicinity of the cell with large power consumption.
[0079]
Further, if the structure is such that power is supplied to the conventional standard cell (function) as shown in FIG. 7, the function of the standard cell can be guaranteed.
[0080]
In FIG. 16, the uppermost layer metal 27 and the uppermost layer-1 metal 26 are also wired to the entire chip except for the IO cell regions 30 and 31 with respect to the standard cell region 11 and the macrocell region 12. For this reason, even if the power supply wiring that becomes the trunk line is removed, power can be sufficiently supplied.
[0081]
In FIG. 16 as well, the top layer metal and the top layer-1 metal are omitted for the sake of convenience in order to simplify the drawing.
[0082]
In the above-described embodiment, the standard flow has been described. However, it is also possible to arrange and improve the power supply standard cell of the present invention for a place where the power supply seems to be weak after the current analysis of the chip. . In this way, even after the layout is completed, it can be easily inserted and arranged, so that it is possible to improve the performance by using the created layout for problems found in the power analysis.
[0083]
Moreover, although it is more effective to use the uppermost layer and the (uppermost layer-1) metal as the Power and Ground metal as in this embodiment, there are cases where only the uppermost layer is used as the power supply wiring.
[0084]
【The invention's effect】
As described above, according to the present invention, in the multiple metal process, the upper layer metal can be utilized as a power line so as not to obstruct the signal wiring line. Moreover, it can be easily incorporated into the conventional design flow by simply adding a power supply standard cell. In addition, the examination of the power supply strap and the like is reduced, and the construction period can be shortened.
[0085]
In addition, regarding the power supply width, the present invention can arrange power supply wiring over the entire chip (CHIP), has a minimum resistance in a single layer, and can reduce the influence of a voltage drop to the power supply standard cell.
[0086]
In addition, the power supply wiring region serving as the trunk line can be reduced without reducing the power supply amount as compared with the conventional chip.
[0087]
Furthermore, power source noise and EMI generated during circuit operation can be prevented by the capacitance between the power source (P / G) metals. In addition, resistance to noise from outside the semiconductor integrated circuit is also increased.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a conventional floor plan, which is a semiconductor integrated circuit device including a standard cell region and two macro cells.
FIG. 2 is a plan view showing a case where an upper layer metal is used as a power supply (PG) wiring in a conventional floor plan.
FIG. 3 is an enlarged view of a portion A in FIG.
FIG. 4 is a pattern diagram showing an example of an inverter as a standard cell.
FIG. 5 is an equivalent circuit diagram of the inverter of FIG. 4;
FIG. 6 is a plan view showing an example of a power supply standard cell of the present invention, where (a) is a part of Power and Ground Rail (metal 1), (b) is a standard cell for power supply, and (c) is a power supply standard cell. The standard cell for Ground supply is shown.
FIG. 7 is a plan view showing an example of a power supply standard cell according to the present invention, which has a region connected to a metal near the upper layer only in the region of Power or Ground Rail next to a normal standard cell.
FIG. 8 is an exploded perspective plan view showing an example of a power supply standard cell according to the present invention, in which a normal standard cell has a region connected to a metal near the upper layer only in the region of Power or Ground Rail.
FIG. 9 is an exploded perspective view showing a normal standard cell (function) used in the present invention, and includes a metal near the upper layer that has no connection relationship anywhere.
FIG. 10 is an exploded perspective view showing another example of a normal standard cell (function) used in the present invention, and includes an upper-layer near metal having no connection relationship anywhere.
11 is a plan view showing an example when the present invention is applied to a standard cell region with respect to the example of the floor plan shown in FIG. 1;
12 is an enlarged exploded perspective view of a region surrounded by A in FIG.
13 is a plan view showing an example in which a power supply standard cell is arranged in a portion for supplying power to a standard cell region and a macro cell in the floor plan shown in FIG. 12 according to the embodiment of the present invention.
14 is a plan view showing an example in which a power supply wiring region serving as a main line is removed from FIG. 13 according to the embodiment of the present invention. FIG.
FIG. 15 is a plan view showing an example in which a plurality of power supply standard cells are arranged instead of the strap in the standard cell area according to the embodiment of the present invention.
FIG. 16 is a plan view showing an example in which a power supply standard cell is arranged in the vicinity of a standard cell with a large current consumption according to the embodiment of the present invention.
17 is an enlarged plan view of a region surrounded by A in FIG. 16;
[Explanation of symbols]
1 chip
3 Standard cell
4 Power supply standard cell
21 Power line for power
22 Ground Power Line

Claims (6)

In the semiconductor integrated circuit device formed by a multilayer process in the automatic placement and routing using a standard cell, the top layer metal or a metal of the first layer under is provided on substantially the entire surface of cells in each standard cell, said uppermost metal or the top A semiconductor integrated circuit device comprising: a power supply standard cell in which an upper layer metal and a metal lower than the upper layer metal are used as a power supply wiring and the metal and a standard cell power line are connected. 2. The semiconductor integrated circuit device according to claim 1, wherein the standard cell having a normal function is provided with an uppermost metal having no connection relation to the power supply line, or the uppermost metal and a metal below the uppermost metal .   The semiconductor integrated circuit device according to claim 1, wherein the power supply standard cell includes a transistor function element therein. 3. The semiconductor integrated circuit device according to claim 2, wherein a slot is provided in an uppermost metal layer that does not have a connection relation with the power supply line of the standard cell, or in the uppermost metal layer and a metal below the uppermost metal layer. 2. At least one standard cell for power supply according to claim 1 is arranged inside a chip, and the uppermost metal or the uppermost metal to which the standard cell for power supply is connected and the metal under the first layer are used as power wiring. A semiconductor integrated circuit device.   6. The semiconductor integrated circuit device according to claim 1, wherein the power supply standard cell is disposed in the vicinity of a cell having large power consumption.

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