JP4628709B2 - Layout design method for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a layout design system and a layout design method thereof.

  In recent years, higher speed and higher integration of semiconductor integrated circuits have been increasingly advanced, and further miniaturization and multi-layering of semiconductor manufacturing processes are expected in response thereto. However, on the other hand, a voltage drop that causes a voltage drop in a part of the semiconductor integrated circuit has become remarkable.

  As the wiring resistance increases, the power consumed by the wiring increases. Therefore, the voltage applied to the functional circuit decreases, and there is a possibility that a malfunction such as a case where a predetermined function cannot be performed in the functional circuit or a malfunction occurs. In order to avoid such a problem, it is necessary to minimize the voltage drop caused by the wiring resistance in order to keep the voltage applied to the functional circuit as constant as possible.

As a design technique for reducing wiring resistance, a technique has been proposed in which the uppermost metal layer is used as the power supply wiring and a plurality of conductive parts connected to the lower wiring are provided to increase the number of power supply wiring paths. ing. In the technique described in Patent Document 1, as a design method therefor, a functional cell and a power supply functional cell having a conductive portion connected from an upper power supply wiring to a lower wiring are used as a library and used for layout design. Has been shown to do. In the technique described in Patent Document 1, the influence of the voltage drop due to the wiring resistance is suppressed by arranging the power supply function cell in a place where the resistance value needs to be lowered.
JP 2003-174086 A

  In the conventional layout design method described above, the bias of the current consumption distribution, such as a case where the current consumption locally increases on the semiconductor integrated circuit, has not been considered. Although it is desirable to optimize the width and interval of the power supply wiring in accordance with the bias in the current consumption distribution, such points have not been considered in the past. Therefore, there has been a problem of excessive power supply by local wiring or local power shortage.

  The present invention is a layout design method for a semiconductor integrated circuit in which a power supply connection cell for electrically connecting the uppermost layer wiring and the lower layer wiring is disposed, and a step of setting the layout of a plurality of functional blocks on the semiconductor integrated circuit; , A step of arranging a plurality of the power supply connection cells in a semiconductor integrated circuit formation region outside the functional block arrangement region, and a step of analyzing an influence of a voltage drop of the uppermost wiring based on the arrangement of the power supply connection cells. Have.

  Since the influence of the voltage drop (IR-Drop) is analyzed based on the arrangement of the power supply cells, the power supply wiring can be optimized.

  In addition, the layout design method for a semiconductor integrated circuit according to the present invention includes a step of replacing the power connection cell based on the result of the voltage drop analysis, thereby selecting a power connection cell pattern that is effective against the influence of the voltage drop. It becomes possible to do.

  Furthermore, by having the step of arranging the functional cell after the step of replacing the power connection cell, it becomes possible to determine the majority of the power supply system wiring network before the functional cell is arranged.

  On the other hand, the present invention is a layout design method for a semiconductor integrated circuit in which a power connection cell for connecting the uppermost layer wiring is arranged, the step of setting the arrangement of a plurality of functional blocks on the semiconductor integrated circuit, and the functional block arrangement A step of disposing a plurality of power connection cells in a semiconductor integrated circuit formation region outside the region; a step of subtracting a current consumed by the functional block from a consumption current of the semiconductor integrated circuit and allocating the power connection cell; and And analyzing the voltage drop of the uppermost wiring based on the current consumption allocated to the connection cell and the constraint condition regarding the influence of the arrangement of the power supply connection cell and the voltage drop given in advance.

  By considering that the current is consumed by the arranged power cells, the pattern of the power connection cells can be optimized.

  Furthermore, the present invention is a layout design method for a semiconductor integrated circuit in which a power supply connection cell for connecting the uppermost wiring and the lower layer wiring is arranged, the step of setting the arrangement of a plurality of functional blocks on the semiconductor integrated circuit, A step of disposing a plurality of the power connection cells based on a constraint condition relating to an influence of a voltage drop given in advance to a semiconductor integrated circuit formation region outside the functional block disposition region; a step of disposing a functional cell; Performing power simulation after placement to estimate current consumption, and voltage drop in the uppermost layer wiring based on the estimated current consumption, the placement of the power supply cell, and the constraints on the influence of the voltage drop given in advance And a step of replacing the power connection cell based on the result of the voltage drop analysis.

  The layout design can be shortened by considering the influence of the voltage drop at the power connection cell placement stage.

  The present invention has a cell library and is a system for automatically designing a layout of a semiconductor integrated circuit composed of a plurality of metal layers, and the cell library includes a functional cell pattern for performing a predetermined function, and A plurality of power connection cell patterns for connecting a power source to the functional cell are provided, and the plurality of power connection cell patterns are arranged based on a voltage drop analysis of a power supply wiring of a semiconductor integrated circuit. By having a plurality of power connection cell patterns, the power wiring network can be easily optimized.

  It is possible to design a semiconductor integrated circuit layout in which the influence of the voltage drop of the power supply wiring and the influence of the voltage drop due to local current bias are reduced.

  The structure of the power connection cell used in the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing an outline of a layout of a semiconductor integrated circuit designed in the present invention. In the semiconductor integrated circuit of the present invention, circuit blocks that perform a plurality of functions are arranged in the cell arrangement region 112. This circuit block includes macro cell areas 110 and 111 indicated by solid lines and other functional cell areas. In this functional cell area, a functional block 114 composed of a plurality of functional cells is arranged. Further, the power supply ring 101 and the ground ring 102 shown in FIG. 2 are formed on the outer periphery of the cell arrangement region 112.

  This semiconductor integrated circuit has a multilayer wiring structure composed of a metal 1 layer M1 (lowermost layer) to a metal 5 layer M5 (uppermost layer), and the wiring layer extending in the x direction shown in FIG. (1 layer M1, metal 3 layer M3, etc.) and the wiring layer extending in the y direction are configured using a metal even layer (for example, metal 2 layer M2, metal 4 layer M4, etc.) preferentially. A schematic diagram of this wiring structure is shown in FIG.

  The semiconductor integrated circuit shown in FIG. 2 has an uppermost layer power supply wiring 103 and an uppermost layer ground wiring 104 that extend in the x direction and are configured using a metal five layer M5. In addition, the second power wiring 105 and the second ground wiring 106 are formed in the y direction orthogonal to the uppermost power wiring 103 and the uppermost ground wiring 104. The second power supply wiring 105 and the second ground wiring 106 are formed by using the metal 4 layer M4 immediately below the uppermost layer wiring, and are formed to complement the uppermost power supply wiring 103 and the uppermost layer grounding wiring 104. Is. In general, the higher the layer is, the thicker the metal layer is and the wider it is, the lower the wiring resistance thereof. Therefore, in the semiconductor integrated circuit of the present invention, the power supply wiring network (power supply wiring, ground wiring) is formed by using the uppermost wiring metal 5 layer M5 and the wiring metal 4 layer M4 immediately below it. Other metal layers and portions not used for the power supply system wiring are appropriately used as signal wiring layers.

  FIG. 3 is a top view showing an enlarged structure of the broken line portion 113 in FIG. 2, a cross-sectional view in the xz direction, and a cross-sectional view in the yz direction. In general, the functional cell 109 shown in FIG. 3 is electrically connected to the lowermost layer power supply wiring 107 and the lowermost layer ground wiring 108 of the metal 1 layer M1 in the lowermost layer. A functional circuit element is formed in the semiconductor layer (diffusion layer) between these wirings. That is, the functional cell 109 is supplied with power from the lowermost layer power wiring 107 and the lowermost ground wiring 108 of the metal 1 layer M1. Those skilled in the art are familiar with the detailed structure of these functional cells themselves, and further description of the functional cells will be omitted.

  As can be seen from the xz sectional view shown in FIG. 3 (b), a metal 4 layer M4 to a metal 4 layer M4 are formed above the lowermost layer ground wiring 108 formed of the metal 1 layer M1. Has been. Via holes V1 to V3 are formed between the metal layers, and the metal layers are connected to each other. That is, the lowermost ground wiring 108 is connected to the second ground wiring layer 106. Further, as can be seen from the yz sectional view shown in (f), a via hole V4 is formed on the metal 4 layer M4, and the second ground wiring layer 106 is connected to the uppermost layer ground wiring 104 via the via hole V4. ing.

  Further, as can be seen from the xz sectional view shown in FIG. 3C, the metal layer M1 to the metal layer M5 are stacked on the lowermost layer power supply wiring 107 formed of the metal layer M1. Yes. Also, via holes V1 to V4 are formed on the lowermost layer power supply wiring 107, and the lowermost layer power supply wiring 107 and the uppermost layer power supply wiring 103 are connected. In the cross-sectional portion shown in FIG. 3A, the lowermost power supply wiring 107 and the second power supply wiring 105 are connected via via holes V1 to V3.

  The power connection cell used in the present invention is constructed based on the structure of the power supply wiring and the ground wiring shown in FIG. 3, and the uppermost power supply wiring and the lowermost power supply wiring, and the wiring layer and upper layer therebetween. The wiring layer and the lower wiring layer are electrically connected to each other. Each wiring layer and via hole between the uppermost layer wiring or the second power supply system wiring and the lowermost layer wiring form a columnar conductive portion, and the uppermost power supply system wiring or the second power supply system wiring and the lowermost power supply system wiring immediately below it. Is connected.

  In FIG. 3, the wiring structure around one functional cell 109 is shown as an overall view in order to understand the positional relationship of the wiring. However, the power connection cell in the present invention is an upper layer power supply surrounding at least one functional cell. The system wiring is divided and patterned at substantially the center. A diagram showing the pattern of the power connection cell is shown in FIG. As shown in FIG. 4, the pattern of the power connection cell is divided at the boundary portion with other adjacent functional cells, and the power connection cell corresponding to one functional cell is the uppermost layer wiring 103, 104, metal 4 It is stored as a pattern divided at the substantially central portion of the wirings 105 and 106 by the layer M4. That is, the power supply connection cell having the structure of the power supply wiring and the ground wiring shown in FIG. 3 is patterned as shown in FIG. 4 and registered as one cell in a cell library described later.

  Note that the connection using the via holes V1 to V4 shown in FIG. 3 is merely an example, and the patterns of the power supply wiring and the ground wiring may be reversed, or other modifications may be used. The power supply connection cell used in the present invention has a pattern in which the uppermost power supply system wiring and the lowermost power supply system wiring are electrically connected via via holes, and this power supply system wiring pattern is connected to one cell. Are treated as

  Note that the power connection cell used in the present invention is not limited to the structure shown in FIG. 4, and other power connection cells having the following structure are prepared. A power connection cell 202 shown in FIG. 5 is a power connection cell having a size doubled in the x direction and the y direction, respectively, from the power connection cell having a structure similar to that of the power connection cell shown in FIG. In the power connection cell 205 shown in FIG. 5, for example, the lowermost power supply wiring 107 is connected to the uppermost power supply wiring 103 through via holes V1 to V4 and metal layers M1 to M4 in the central portion 202A. In the four corners 202B, the second ground wiring 106 made of the metal 4 layer M4 is connected to the uppermost ground wiring 104. Further, in the portion 202C formed at two positions on the left side and the right side of the power connection cell 202, the lowermost layer ground wiring 108 is connected to the second ground wiring via via holes V1 to V3 and metal layers M1 to M3. Yes. Further, the lowermost power wiring 107 is connected to the second power wiring 105 via the via holes V1 to V3 and the metal layers M1 to M3 in the upper side and the lower side central portion 202D of the power connection cell 202.

  The power connection cell shown in FIGS. 6A and 6B is a power connection cell having a structure on the upper side and the left side when the power connection cell 202 is cut at the center in the x direction and the center in the y direction, respectively. . The power connection cell shown in FIG. 6A is a power connection cell having twice the length in the x direction with respect to the power connection cell shown in FIG. 4, and the power connection cell shown in FIG. 6B is the power supply cell shown in FIG. This is a power supply connection cell having twice the length in the y direction with respect to the connection cell.

  Although a specific example will be described later, the power connection cell of the present invention has a plurality of patterns in which the wiring width of the uppermost layer wiring M5 or the metal 4 layer M4 shown in FIG. In addition, the width of this wiring is not limited to the case where the wiring widths of all four sides shown in FIG. It is prepared as.

  As described above, a power supply system wiring (power supply wiring, ground wiring) having a different size and wiring width and a pattern having only a conductive portion for connecting a lower power supply system wiring from an upper power supply system wiring is used in the present invention. Power supply connection cell.

  Furthermore, the power connection cell used in the present invention is stored in the cell library in a state where it can be mirror-arranged or rotated. FIG. 7 is a top view showing respective structures when the power connection cell shown in FIG. It should be noted that the types of power connection cells prepared in the library can be reduced by holding them in the cell library as cells that can be mirrored and rotated.

  As described above, in the present invention, a plurality of types of power connection cells are prepared and used for layout design of a semiconductor integrated circuit. A layout design flow by the layout design system will be described below. A layout design system having a known structure can be used as the layout design system of the present invention, and an outline of the layout design system is shown in FIG. The layout design system includes a cell library that holds functional cell patterns and macro cell patterns, a netlist memory that stores netlist information, a control information memory that stores arrangement constraint information specified by the user, and the like. . Also, a layout generation unit that generates a layout from these pieces of information, a layout data output unit, and the like are provided. The power connection cells used in the present invention described so far are stored in advance in the cell library in the same manner as normal function cells, and are read from the cell library and used in the following flow. .

  FIG. 9 is a diagram showing a flow when designing the layout of a semiconductor integrated circuit according to the present invention. In step S1, a floor plan such as the arrangement of the macro cells 110 and 111 and the arrangement of the functional blocks 114 is performed. This step is a step of designating a group of function cells capable of executing a certain function or a layout of the layered function when designing the functions of the semiconductor integrated circuit in a hierarchy. Through this process, the floor plan on the semiconductor chip as shown in FIG. 1 is determined.

  In step S1, the current consumption of each of the macro cells 110 and 111 or the functional block 114 whose arrangement has been determined is set based on the current consumption information A1. In addition, in the area where only the normal function cell in which the macro cell and the functional block are not set in this step S1 is arranged, the remaining current obtained by subtracting the current consumed by the macro cell and the functional block from the current consumption of the entire circuit. Current value is set. This current consumption information A1 is information stored in the layout design system as information preliminarily associating each macro cell, functional block, etc. with the current consumption based on power simulation based on desktop calculation or virtual wiring prediction before layout execution. It is.

  Next, in step S2, the above-described automatic arrangement of the power connection cells is performed. The power connection cell is connected to the power supply ring 101 and the ground ring 102 arranged around the cell arrangement region 112. FIG. 10 is a diagram showing the connection between the power connection cell and the power ring 101 and the ground ring 102. The connection example shown in FIG. 10 shows a connection example in which the power supply ring 101 is formed on the metal 5 layer M5 and the ground ring 102 is formed on the metal 4 layer M4. That is, the uppermost layer power supply wiring 103 communicates with the power supply ring directly, and the second power supply wiring 105 is connected to the power supply ring 101 through the via hole. The uppermost layer ground wiring 104 is connected to the ground ring 102 through a via hole, and the second ground wiring 106 communicates directly with the ground ring 102. On the other hand, in the macro cells 110 and 111, for example, a power ring is formed around the macro cell, and power is supplied by connecting the power ring and the macro cell.

  Next, in step S3, the consumption current allocated to each region other than the macro in step S1 is considered to be consumed by the individual power connection cells arranged in step S2, and is consumed for each power connection cell. Allocate current. On the other hand, for the macro, the current consumption of the macro itself is assigned. That is, it is considered that the power connection cells arranged in the region where only the normal functional cells are arranged in step S1 are consuming a predetermined current, and the total consumption current of the power connection cells is determined as the step. It is estimated that the current is allocated in S1.

  Subsequently, in step S4, IR-Drop analysis is performed. This IR-Drop collectively refers to a decrease in power supply potential and an increase in ground potential at each location of the power supply system wiring, which is the product of current consumption and wiring resistance, due to wiring resistance. That is, in this analysis, an analysis of the influence of the voltage drop of the wiring resistance is performed. In this IR-Drop analysis, in addition to the power supply wiring data, wiring process parameters, and temperature conditions, the above-described consumption current information A1 and the IR-Drop restriction A2 given from the outside are considered. Here, the current to be considered is analyzed as consumed by the individual macros and the power supply connection cells as performed in step S3.

  If an IR-Drop violation occurs in step S4, the power supply width and interval are adjusted by replacing the type of the power supply cell in step S5. For example, in the state where the power connection cells shown in FIG. 4 are uniformly arranged, if the influence of the voltage drop due to the wiring to a specific power connection cell is large, the wiring of the power connection cell until reaching the power connection cell Reduce resistance. That is, it is replaced with a power supply connection cell in which the width of the uppermost layer wiring in the power supply connection cell up to that position is large. FIG. 11 shows an example of such an arrangement, and shows a configuration in which the power supply wiring width is increased from the lower left to the upper right of the drawing by the arrangement of the power connection cells 205 to 213.

  In step S5, the power connection cell is replaced in order to increase the resource (degree of freedom) of the signal wiring for a portion having a margin with respect to the IR-Drop restriction. That is, the power connection cell in which the supply of power is excessive is replaced with a power connection cell with less power supply. As an example, in FIG. 12, by arranging the power supply connection cells 214 to 220, signal wiring resources are increased by reducing via holes connecting the power supply and ground wirings of the upper layer and the metal 1 layer M1.

  In FIG. 12, the portion surrounded by the broken lines 401 and 402 is configured such that there is no via hole connecting the metal layer M4 and the metal layer M1, and the signal wiring resources increase accordingly. Similarly, in the portion surrounded by the broken lines 403 and 404, the number of vias connecting the metal layer M4 and the metal layer M1 is halved.

  FIG. 13 shows an example in which the space between the power supply and the ground wiring using the upper layer is widened by the arrangement of the power supply connection cells 221 to 223. In FIG. 13, the second power supply wiring 107 is reduced in a portion surrounded by a broken line 405. Similarly, the uppermost layer power supply wiring 103 is reduced in the portion surrounded by the broken line 406. As a result, the signal wiring resources of the metal 4 layer M4 and the metal 5 layer M5 are increased. This configuration can be implemented by disposing a plurality of power connection cells having different wiring widths as described above and having a power cell whose width of the power wiring corresponding to one side is zero. As described above, the pattern of the power cell to be arranged is determined based on the analysis result of the voltage drop that is considered that the power connection cell individually consumes the current, and the power supply wiring and the ground wiring are determined.

  After the power supply wiring and the ground wiring are determined from the above steps, functional cells are arranged in step S6. Thereafter, signal wiring is performed in step S7. Since step S6 and step S7 need to be executed in consideration of signal wiring resources (paths), generally, the signal wiring is efficient by being executed after the power supply and ground wiring are determined until step S5. Well designed.

  Up to the above, the layout and wiring of the semiconductor integrated circuit is performed once. The power simulation is performed in step S9 using the layout result, and the current consumption information of each macro and cell is reflected in the layout design to some extent. A3 is extracted. In the first embodiment, step S9 can be omitted.

  Subsequently, in step S8, IR-Drop analysis is performed as a final confirmation. In the present invention, since the power supply wiring and the ground wiring are optimized in step S4 and step S5, there is basically no violation in the IR-Drop verification in step S8. However, in the step S4, the consumption current A1 is a desktop calculation result or is obtained from a power simulation result based on the predicted wiring. For this reason, if an error from the power simulation due to the final placement and routing result occurs, an IR-Drop violation may be detected in step S8. In that case, step S15 for replacing the power source connection cell is performed as in step S4, and the power source wiring and the ground wiring are corrected. When a short circuit with the signal wiring or a design rule violation occurs locally due to the replacement of the power connection cell, the signal wiring is corrected.

  According to the present invention, the resistance of the power supply wiring network of the power supply wiring and the ground wiring of the semiconductor integrated circuit can be automatically adjusted with a small area unit easily and with high accuracy in consideration of current consumption. As a result, it is possible to greatly reduce the back work due to the IR-Drop violation and to shorten the time required for the layout work.

  In addition, since an optimal power supply system wiring network according to current consumption can be constructed, it is easy to secure wiring resources without requiring excessive power supply and ground wiring, and the degree of integration of the semiconductor integrated circuit can be improved.

  In the embodiment described above, priority is given to the flow description of the layout design, so that the power to be supplied to the macro cell is supplied from the power ring arranged in the surroundings. It is also possible to do. For example, it is possible to flexibly cope with the arrangement of the macro power supply terminals, such as configuring a power supply ring around the macro with the power supply cell itself. As an example, in FIG. 14, the power connection cells 224 to 226 are arranged so as to surround the macro cell. By disposing the power connection cell, a power ring is formed around the macro and power is supplied from the power ring to the macro power terminal 301. FIG. 15 shows an example in which the power supply terminal of the macro is configured to feed power from above the macro, not the outer periphery. In this configuration, the power connection cells 227 to 228 are arranged on the macro, a via hole is formed at the intersection of the power supply wiring inside the power connection cell and the macro power terminal 302, and power is supplied through the via hole.

In the case of power feeding to the power supply separation macro 111 having a power supply system from which the macro is separated, a configuration as shown in FIG. 16 can be adopted. The power connection cell 229 is arranged and connected to the power supply cell 116 and the macro power supply terminal or the macro circulation power supply ring.
Hereinafter, the layout design flow according to the second embodiment of the present invention will be described with reference to FIG. The same steps as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.
In the second embodiment, step S21 after the floor plan of step 1 is different. In the arrangement of the power supply connection cells in the second embodiment, the power supply connection cells are arranged in consideration of the IR-Drop constraint A2. Thereby, the process of step S3-S5 in Embodiment 1 is completed by step S21.

  Further, when the functional cell placement in step S6 is completed, the power simulation in step S9 is executed based on the schematic wiring information based on the placement result.

  Next, IR-Drop verification is performed in step S8, and if a violation occurs, step S15 is executed. Thereafter, signal wiring is executed in step S4.

  In the second embodiment, the processing in steps S3 to S5 in the first embodiment is configured without configuring the power supply and the ground wiring network without referring back to the IR-Drop constraint in step S21, thereby reducing the layout work time. Is planned.

  Further, the power simulation in step S9 is performed with the schematic wiring information based on the placement result. This rough wiring information is relatively close to the final wiring information as compared with the virtual wiring prediction before the placement. Therefore, after power simulation, IR-Drop verification in step S8 is performed, and if necessary, the power connection cell is replaced in step S15 to determine the power source and the ground wiring network. Thereby, after the signal wiring in step S7, the signal wiring correction accompanying the replacement of the power connection cell becomes unnecessary, and the layout work time can be shortened.

  As described above in detail, according to the present invention, a plurality of power connection cell patterns are prepared, the power connection cell pattern assumes the current, analyzes the influence of the voltage drop, and replaces the power cell pattern. Even when current consumption is uneven, uniform power supply can be performed.

1 is a layout schematic diagram of a semiconductor integrated circuit to which the present invention is applied. It is a figure which shows the wiring structure of a semiconductor integrated circuit. It is a principal part enlarged view of the wiring structure regarding the power supply connection cell of this invention. It is a basic structure figure of the power supply connection cell of this invention. It is another structural example of the power supply connection cell utilized by this invention. It is another structural example of the power supply connection cell utilized by this invention. It is the figure which showed the mirror arrangement | positioning and rotation arrangement | positioning of the power supply connection cell shown in FIG. It is the schematic of the layout design system of this invention. It is a figure which shows the layout design flow of Embodiment 1 of this invention. It is a figure which shows the connection of a power connection cell, a power supply ring, and a ground ring. This is an example in which a plurality of power supply connection rings having different upper-layer wiring widths are arranged. It is a figure which shows the example which reduced and arrange | positioned the via hole between wiring layers. It is a figure which shows the example which reduced the upper layer wiring. FIG. 6 is a layout diagram when a power ring is formed around a macro cell by power connection cells. It is a figure which shows the example which supplies a power supply from a macrocell upper part by a power supply connection cell. It is an example which shows the connection of a macrocell and a power supply in case a macrocell is a different power supply. It is a figure which shows the layout design bath e in Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Power ring 102 Ground ring 103 Top layer power wiring 104 Top layer ground wiring 105 Power wiring 106 Ground wiring 107 Bottom layer power wiring 108 Bottom layer ground wiring 109 Function cell 110, 111 Macro cell 112 Cell arrangement area 114 Function block

Claims (3)

A layout design method for a semiconductor integrated circuit in which a power connection cell for electrically connecting a top layer wiring and a lower layer wiring is disposed,
Arranging a plurality of functional blocks on the semiconductor integrated circuit;
Arranging a plurality of power connection cells in a semiconductor integrated circuit formation region other than a region in which the plurality of functional blocks are disposed;
Analyzing the influence of the voltage drop of the uppermost layer wiring based on the arrangement of the power connection cells;
Have
Based on the result of the voltage drop analysis, either the step of replacing the power connection cell or the step of arranging a functional cell and performing signal wiring of the semiconductor integrated circuit is selectively executed. A method for designing a layout of a semiconductor integrated circuit. A layout design method for a semiconductor integrated circuit in which a power connection cell for connecting an uppermost layer wiring and a lower layer wiring is disposed,
A step of setting an arrangement of a plurality of functional blocks on a semiconductor integrated circuit;
Arranging a plurality of the power connection cells in a semiconductor integrated circuit formation region outside the functional block arrangement region;
Subtracting the current consumed by the functional block from the current consumed by the semiconductor integrated circuit and assigning it to the power connection cell;
Analyzing the voltage drop of the uppermost layer wiring based on the current consumption allocated to the power connection cell and the constraint condition regarding the influence of the arrangement of the power connection cell and the voltage drop given in advance;
Have
When the result of the voltage drop analysis is good, function cells are arranged and signal wiring of the semiconductor integrated circuit is performed, and when the result of the voltage drop analysis is not good, the power connection cell is replaced. A method for designing a layout of a semiconductor integrated circuit. A layout design method for a semiconductor integrated circuit in which a power connection cell for connecting an uppermost layer wiring and a lower layer wiring is disposed,
A step of setting an arrangement of a plurality of functional blocks on a semiconductor integrated circuit;
A step of arranging a plurality of the power supply connection cells based on a restriction condition relating to an influence of a voltage drop given in advance to a semiconductor integrated circuit formation region outside the functional block arrangement region;
Placing functional cells;
Performing power simulation after placement of the functional cells and estimating current consumption;
Analyzing the voltage drop of the uppermost layer wiring based on the estimated current consumption, the arrangement of the power connection cell and the constraint on the influence of the voltage drop given in advance;
Have
A layout of a semiconductor integrated circuit, wherein one of a step of replacing the power supply connection cell and a step of signal wiring of the semiconductor integrated circuit is selectively executed based on a result of the voltage drop analysis Design method.

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